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Searched refs:APU_PCLI (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/xilinx/versal_net/include/
H A Dversal_net_def.h62 #define APU_PCLI (0xECB10000ULL) macro
77 #define APU_PCIL_CORE_X_ISR_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_WAKE_OFFSET + \
81 #define APU_PCIL_CORE_X_IEN_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_WAKE_OFFSET + \
85 #define APU_PCIL_CORE_X_IDS_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_WAKE_OFFSET + \
89 #define APU_PCIL_CORE_X_ISR_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_POWER_OFFSET + \
93 #define APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_POWER_OFFSET + \
97 #define APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_POWER_OFFSET + \
/rk3399_ARM-atf/plat/amd/versal2/include/
H A Ddef.h67 #define APU_PCLI (0xECB10000ULL) macro
82 #define APU_PCIL_CORE_X_ISR_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_WAKE_OFFSET + \
86 #define APU_PCIL_CORE_X_IEN_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_WAKE_OFFSET + \
90 #define APU_PCIL_CORE_X_IDS_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_WAKE_OFFSET + \
94 #define APU_PCIL_CORE_X_ISR_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_POWER_OFFSET + \
98 #define APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_POWER_OFFSET + \
102 #define APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_POWER_OFFSET + \
/rk3399_ARM-atf/plat/xilinx/versal_net/
H A Dplat_psci.c53 apu_pcli_cluster = APU_PCLI + APU_PCLI_CLUSTER_OFFSET + (cluster * APU_PCLI_CLUSTER_STEP); in zynqmp_nopmu_pwr_domain_on()
79 apu_pcli_base = APU_PCLI + (APU_PCLI_CPU_STEP * cpu) + in zynqmp_nopmu_pwr_domain_on()
/rk3399_ARM-atf/plat/amd/versal2/
H A Dplat_psci.c56 …apu_pcli_cluster = APU_PCLI + APU_PCLI_CLUSTER_OFFSET + ((uint64_t)cluster * APU_PCLI_CLUSTER_STEP… in zynqmp_nopmu_pwr_domain_on()
82 apu_pcli_base = APU_PCLI + (APU_PCLI_CPU_STEP * cpu) + in zynqmp_nopmu_pwr_domain_on()