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/optee_os/core/lib/libtomcrypt/src/ciphers/
H A Drc2.c152 unsigned x76, x54, x32, x10, i; in s_rc2_ecb_encrypt() local
163 x10 = ((unsigned)pt[1] << 8) + (unsigned)pt[0]; in s_rc2_ecb_encrypt()
166 x10 = (x10 + (x32 & ~x76) + (x54 & x76) + xkey[4*i+0]) & 0xFFFF; in s_rc2_ecb_encrypt()
167 x10 = ((x10 << 1) | (x10 >> 15)); in s_rc2_ecb_encrypt()
169 x32 = (x32 + (x54 & ~x10) + (x76 & x10) + xkey[4*i+1]) & 0xFFFF; in s_rc2_ecb_encrypt()
172 x54 = (x54 + (x76 & ~x32) + (x10 & x32) + xkey[4*i+2]) & 0xFFFF; in s_rc2_ecb_encrypt()
175 x76 = (x76 + (x10 & ~x54) + (x32 & x54) + xkey[4*i+3]) & 0xFFFF; in s_rc2_ecb_encrypt()
179 x10 = (x10 + xkey[x76 & 63]) & 0xFFFF; in s_rc2_ecb_encrypt()
180 x32 = (x32 + xkey[x10 & 63]) & 0xFFFF; in s_rc2_ecb_encrypt()
186 ct[0] = (unsigned char)x10; in s_rc2_ecb_encrypt()
[all …]
/optee_os/core/arch/arm/kernel/
H A Dcache_helpers_a64.S97 mov x10, xzr
109 add x2, x10, x10, lsr #1 // work out 3x current cache level
115 msr csselr_el1, x10 // select current cache level in csselr
148 add x10, x10, #2 // increment cache number
149 cmp x3, x10
179 sub x10, x3, #2
H A Darch_scall.c86 .x10 = pushed[11], in save_panic_regs_a32_ta()
H A Dthread_spmc_a64.S52 mov x10, #FFA_PARAM_MBZ
H A Dabort.c196 EMSG_RAW(" x10 %016" PRIx64 " x11 %016" PRIx64, in __print_abort_info()
197 ai->regs->x10, ai->regs->x11); in __print_abort_info()
/optee_os/core/arch/arm/plat-rcar/
H A Dromapi_call.S38 ldr x10, boot_mmu_config + CORE_MMU_CONFIG_MAP_OFFSET
39 add x9, x9, x10
51 ldr x10, boot_mmu_config + CORE_MMU_CONFIG_MAP_OFFSET
52 add x9, x9, x10
/optee_os/core/arch/arm/dts/
H A Dstm32mp157a-dk1.dts36 reg = <0xf0 0x10>;
H A Dstm32mp157c-dk2.dts38 reg = <0xf0 0x10>;
H A Dstm32mp131.dtsi232 reg = <0x50001000 0x10>;
372 reg = <0x10 0x4>;
397 reg = <0x170 0x10>;
647 st,syscfg-fmp = <&syscfg 0x4 0x10>;
H A Dsama5d2.dtsi688 reg = <0xf8048000 0x10>;
696 reg = <0xf8048010 0x10>;
707 reg = <0xf8048030 0x10>;
714 reg = <0xf8048040 0x10>;
H A Dstm32mp151.dtsi150 reg = <0x50001000 0x10>;
410 reg = <0x10 0x4>;
1074 st,syscfg-fmp = <&syscfg 0x4 0x10>;
1370 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
1403 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
1435 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
1775 reg = <0x50027000 0x4>, <0x500273f0 0x10>;
H A Dstm32mp157c-ed1.dts131 reg = <0xf0 0x10>;
H A Dat91-sama7g54_ek.dts235 reg = <0x10>;
H A Dsama7g5.dtsi352 reg = <0xe001d010 0x10>;
H A Dfsl-lx2160a.dtsi1369 reg = <0x10>;
/optee_os/core/arch/arm/include/kernel/
H A Dthread_arch.h202 uint64_t x10; /* r10_usr */ member
261 uint64_t x10; /* r10_usr */ member
/optee_os/core/arch/arm/crypto/
H A Dghash-ce-core_a64.S431 ldr x10, [sp]
432 ld1 {KS0.16b-KS1.16b}, [x10]
579 st1 {KS0.16b-KS1.16b}, [x10]
H A Dsm4_armv8a_ce_a64.S21 #define tw1h x10
H A Dsm4_armv8a_aese_a64.S30 #define tw1h x10
/optee_os/core/kernel/
H A Dldelf_loader.c271 arg->arm32.regs[10] = tsd->abort_regs.x10; in ldelf_dump_state()