11183a0aaSEtienne Carriere// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 21183a0aaSEtienne Carriere/* 3*41115447SGatien Chevallier * Copyright (C) STMicroelectronics 2019-2024 - All Rights Reserved 41183a0aaSEtienne Carriere * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. 51183a0aaSEtienne Carriere */ 61183a0aaSEtienne Carriere 71183a0aaSEtienne Carriere/dts-v1/; 81183a0aaSEtienne Carriere 91bf81340SEtienne Carriere#include "stm32mp157.dtsi" 101bf81340SEtienne Carriere#include "stm32mp15-pinctrl.dtsi" 111bf81340SEtienne Carriere#include "stm32mp15xxac-pinctrl.dtsi" 121bf81340SEtienne Carriere#include "stm32mp15xx-dkx.dtsi" 131183a0aaSEtienne Carriere 141183a0aaSEtienne Carriere/ { 151183a0aaSEtienne Carriere model = "STMicroelectronics STM32MP157A-DK1 Discovery Board"; 161183a0aaSEtienne Carriere compatible = "st,stm32mp157a-dk1", "st,stm32mp157"; 171183a0aaSEtienne Carriere 181183a0aaSEtienne Carriere aliases { 191183a0aaSEtienne Carriere ethernet0 = ðernet0; 201183a0aaSEtienne Carriere serial0 = &uart4; 2113bd79f4SJohann Neuhauser serial1 = &usart3; 2213bd79f4SJohann Neuhauser serial2 = &uart7; 231183a0aaSEtienne Carriere }; 241183a0aaSEtienne Carriere 251183a0aaSEtienne Carriere chosen { 261183a0aaSEtienne Carriere stdout-path = "serial0:115200n8"; 271183a0aaSEtienne Carriere }; 281183a0aaSEtienne Carriere}; 29ccc6e7c9SEtienne Carriere 304703bfe2SEtienne Carriere&bsec { 314703bfe2SEtienne Carriere board_id: board_id@ec { 324703bfe2SEtienne Carriere reg = <0xec 0x4>; 334703bfe2SEtienne Carriere st,non-secure-otp; 344703bfe2SEtienne Carriere }; 357723564bSNicolas Toromanoff huk_otp: huk-otp@f0 { 367723564bSNicolas Toromanoff reg = <0xf0 0x10>; 377723564bSNicolas Toromanoff }; 384703bfe2SEtienne Carriere}; 39*41115447SGatien Chevallier 40*41115447SGatien Chevallier&etzpc { 41*41115447SGatien Chevallier st,decprot = 42*41115447SGatien Chevallier <DECPROT(STM32MP1_ETZPC_USART1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 43*41115447SGatien Chevallier <DECPROT(STM32MP1_ETZPC_SPI6_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 44*41115447SGatien Chevallier <DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 45*41115447SGatien Chevallier <DECPROT(STM32MP1_ETZPC_I2C6_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 46*41115447SGatien Chevallier <DECPROT(STM32MP1_ETZPC_RNG1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 47*41115447SGatien Chevallier <DECPROT(STM32MP1_ETZPC_HASH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)>, 48*41115447SGatien Chevallier <DECPROT(STM32MP1_ETZPC_DDRCTRL_ID, DECPROT_NS_R_S_W, DECPROT_LOCK)>, 49*41115447SGatien Chevallier <DECPROT(STM32MP1_ETZPC_DDRPHYC_ID, DECPROT_NS_R_S_W, DECPROT_LOCK)>, 50*41115447SGatien Chevallier <DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_LOCK)>, 51*41115447SGatien Chevallier <DECPROT(STM32MP1_ETZPC_BKPSRAM_ID, DECPROT_S_RW, DECPROT_LOCK)>, 52*41115447SGatien Chevallier <DECPROT(STM32MP1_ETZPC_IWDG1_ID, DECPROT_S_RW, DECPROT_LOCK)>; 53*41115447SGatien Chevallier}; 54