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Searched refs:r0 (Results 1 – 25 of 66) sorted by relevance

123

/optee_os/core/arch/arm/kernel/
H A Dentry_a32.S43 mov r4, r0
46 cmp r0, #0
48 mov r0, r4
50 cmp r0, r4
56 ldr r0, =panic_boot_file
67 ldr r0, \va
94 lsl r0, r0, #2
97 str r2, [r1, r0]
105 ldr r0, =sem_cpu_sync
109 ldr r1, [r0]
[all …]
H A Dthread_a32.S33 mov sp, r0
42 mov sp, r0
51 mov sp, r0
60 mov sp, r0
69 mov r0, sp
78 mov r0, lr
87 mov lr, r0
95 add r12, r0, #(13 * 4) /* Restore registers r0-r12 later */
118 ldm r0, {r0-r12}
141 push {r0-r3}
[all …]
H A Dmisc_a32.S15 read_mpidr r0
22 mov r3, r0
31 tst r0, #MPIDR_MT_MASK
32 lsleq r3, r0, #MPIDR_AFFINITY_BITS
40 ubfx r0, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
42 add r0, r0, r1, LSL #(CFG_CORE_CLUSTER_SHIFT)
48 ubfx r0, r3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
52 add r0, r0, r1, LSL #(CFG_CORE_THREAD_SHIFT)
63 mov r1, r0
67 mrs r0, cpsr /* get cpsr with disabled its*/
[all …]
H A Dtz_ssvce_pl310_a32.S23 add r1, r0, #PL310_DCACHE_LOCKDOWN_BASE
24 ldr r2, [r0, #PL310_AUX_CTRL]
28 mov r0, #PL310_LOCKDOWN_NBREGS
32 subs r0, r0, #1
43 ldr \reg, [r0, #PL310_AUX_CTRL]
56 str r1, [r0, #PL310_FLUSH_BY_WAY]
60 ldr r2, [r0, #PL310_FLUSH_BY_WAY]
74 ldr r1, [r0, #PL310_SYNC]
79 str r1, [r0, #PL310_SYNC]
82 ldr r1, [r0, #PL310_SYNC]
[all …]
H A Dthread_optee_smc_a32.S50 mov r1, r0
51 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE
60 push {r0-r7}
61 mov r0, sp
64 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE
76 ldr r0, =TEESMC_OPTEED_RETURN_FIQ_DONE
87 mov r1, r0
88 ldr r0, =TEESMC_OPTEED_RETURN_ON_DONE
98 mov r1, r0
99 ldr r0, =TEESMC_OPTEED_RETURN_OFF_DONE
[all …]
H A Dcache_helpers_a32.S35 add r1, r0, r1
37 bic r0, r0, r3
39 write_\reg r0
40 add r0, r0, r2
41 cmp r0, r1
112 add r6, r11, r0, lsl #3 // cache op is 2x32-bit instructions
133 orr r0, r1, r9, LSL r5 // factor in the way number and cache level into r0
134 orr r0, r0, r7, LSL r10 // factor in the set number
154 write_dcisw r0
156 write_dccisw r0
[all …]
H A Dspin_lock_a32.S42 ldrex r1, [r0]
45 strexeq r1, r2, [r0]
55 mov r1, r0
57 ldrex r0, [r1]
58 cmp r0, #0
60 strex r0, r2, [r1]
61 cmp r0, #0
75 str r1, [r0]
H A Dvfp_a32.S14 vstm r0!, {d0-d15}
18 vstm r0, {d16-d31}
24 vldm r0!, {d0-d15}
28 vldm r0, {d16-d31}
34 vmsr fpexc, r0
40 vmrs r0, fpexc
46 vmsr fpscr, r0
52 vmrs r0, fpscr
/optee_os/core/arch/arm/plat-imx/
H A Da9_plat_init.S83 read_diag r0
84 orr r0, r0, #1 << 22
85 write_diag r0
95 mov r0, #SCR_AW
96 write_scr r0
120 mov_imm r0, 0x00004000
121 write_sctlr r0
124 mov_imm r0, 0x00000046
126 mov_imm r0, 0x00000047
128 write_actlr r0
[all …]
H A Da7_plat_init.S43 mov_imm r0, 0x00006040
44 write_actlr r0
46 mov_imm r0, 0x00040C00
47 write_nsacr r0
54 and r0, r0, #MPIDR_CPU_MASK
/optee_os/core/lib/libtomcrypt/src/ciphers/
H A Dserpent.c78 #define s_s0(i, r0, r1, r2, r3, r4) { \ argument
79 r3 ^= r0; \
83 r1 ^= r0; \
84 r0 |= r3; \
85 r0 ^= r4; \
94 r3 |= r0; \
99 #define s_i0(i, r0, r1, r2, r3, r4) { \ argument
102 r1 |= r0; \
107 r0 ^= r4; \
108 r2 ^= r0; \
[all …]
/optee_os/core/arch/arm/plat-stm/
H A Dtz_a9init.S31 str r1, [r0, #PL310_CTRL]
34 ldr r1, [r0, #PL310_AUX_CTRL]
36 read_actlr r0
37 orrne r0, r0, #(1 << 3) /* enable ACTLR[FLZW] */
38 write_actlr r0
53 mov_imm r0, SCR_AW
54 write_scr r0
56 mov_imm r0, CPU_SCTLR_INIT
57 write_sctlr r0
59 mov_imm r0, CPU_ACTLR_INIT
[all …]
/optee_os/core/arch/arm/sm/
H A Dsm_a32.S23 str r2, [r0], #4
24 str sp, [r0], #4
25 str lr, [r0], #4
32 str sp, [r0], #4
33 str lr, [r0], #4
43 stm r0!, {r2}
48 stm r0!, {r2}
56 ldr r2, [r0], #4
57 ldr sp, [r0], #4
58 ldr lr, [r0], #4
[all …]
H A Dpsci-helper.S12 read_actlr r0
13 bic r0, r0, #ACTLR_SMP
14 write_actlr r0
20 read_actlr r0
21 orr r0, r0, #ACTLR_SMP
22 write_actlr r0
31 mov r0, #DCACHE_OP_CLEAN_INV
35 read_sctlr r0
36 bic r0, r0, #SCTLR_C
37 write_sctlr r0
[all …]
H A Dpm_a32.S30 push {r0, r1}
33 add r0, sp, #8
37 pop {r0, pc}
42 mov r0, #(-1)
67 stmia r0!, {r4 - r5}
71 stmia r0!, {r4 - r5}
84 stmia r0!, {r4 - r11}
89 stmia r0, {r4 - r7}
99 adr r0, _core_pos
100 ldr r1, [r0]
[all …]
/optee_os/core/arch/arm/plat-sunxi/
H A Dplat_init.S36 read_nsacr r0
37 orr r0, r0, #NSACR_CP10
38 orr r0, r0, #NSACR_CP11
39 orr r0, r0, #NSACR_NS_SMP
40 write_nsacr r0
43 read_actlr r0
44 orr r0, r0, #ACTLR_SMP
45 write_actlr r0
/optee_os/core/arch/arm/plat-hisilicon/
H A Dhi3519av100_plat_init.S40 mrrc p15, 1, r0, r1, c15
41 orr r0, r0, #CPUECTLR_A53_SMPEN
42 mcrr p15, 1, r0, r1, c15
50 read_scr r0
51 orr r0, r0, #SCR_NS /* Set NS bit in SCR */
52 write_scr r0
60 bic r0, r0, #SCR_NS /* Clr NS bit in SCR */
61 write_scr r0
76 cmp r0, #0
78 ldr r0, =CCI_BASE
[all …]
/optee_os/core/arch/arm/plat-zynq7k/
H A Dplat_init.S68 mov r0, #SCR_AW
69 write_scr r0 /* write Secure Configuration Register */
91 mov_imm r0, 0x00004000
92 write_sctlr r0
94 mov_imm r0, 0x00000041
95 write_actlr r0
97 mov_imm r0, 0x00020C00
98 write_nsacr r0
100 mov_imm r0, 0x00000001
101 write_pcr r0
/optee_os/core/lib/libtomcrypt/src/stream/sosemanuk/
H A Dsosemanuk.c70 #define S0(r0, r1, r2, r3, r4) do { \ argument
71 r3 ^= r0; r4 = r1; \
73 r1 ^= r0; r0 |= r3; \
74 r0 ^= r4; r4 ^= r3; \
78 r1 ^= r4; r3 |= r0; \
82 #define S1(r0, r1, r2, r3, r4) do { \ argument
83 r0 = ~r0; r2 = ~r2; \
84 r4 = r0; r0 &= r1; \
85 r2 ^= r0; r0 |= r3; \
86 r3 ^= r2; r1 ^= r0; \
[all …]
/optee_os/lib/libutils/ext/arch/arm/
H A Dmcount_a32.S31 stmdb sp!, {r0-r3, lr}
33 ldr r0, [sp, #20] /* lr of instrumented func */
34 mcount_adj_pc r0, r0
40 ldr r0, [sp, #16]
41 mcount_adj_pc r0, r0
46 ldmia sp!, {r0-r3, ip, lr}
53 stmdb sp!, {r0-r3}
57 mov lr, r0
60 ldmia sp!, {r0-r3}
/optee_os/core/arch/arm/plat-ls/
H A Dplat_init.S62 mov r0, #SCR_AW
63 write_scr r0 /* write Secure Configuration Register */
77 mov_imm r0, 0x00000000
78 write_sctlr r0
80 mov_imm r0, 0x00000040
81 write_actlr r0
83 mov_imm r0, 0x00000C00
84 write_nsacr r0
/optee_os/core/arch/arm/plat-rzn1/
H A Da7_plat_init.S35 mov r0, #SCR_AW
36 write_scr r0
38 mov_imm r0, 0x00000000
39 write_sctlr r0
51 mov_imm r0, 0x00006040
52 write_actlr r0
60 mov_imm r0, 0x00000C00
61 write_nsacr r0
/optee_os/core/arch/arm/plat-vexpress/
H A Djuno_core_pos_a32.S13 and r1, r0, #MPIDR_CPU_MASK
14 and r0, r0, #MPIDR_CLUSTER_MASK
15 eor r0, r0, #(1 << MPIDR_CLUSTER_SHIFT)
16 add r0, r1, r0, LSR #6
/optee_os/lib/libutils/isoc/arch/arm/
H A Darm32_aeabi_ldivmod_a32.S16 push {r0-r3}
17 UNWIND( .save {r0-r3})
18 mov r0, sp
20 pop {r0-r3}
31 push {r0-r3}
32 UNWIND( .save {r0-r3})
33 mov r0, sp
35 pop {r0-r3}
/optee_os/core/arch/arm/plat-stm32mp1/
H A Dreset.S17 ldr r0, =SCR_SIF
18 write_scr r0
20 read_nsacr r0
22 and r0, r0, r1
23 write_nsacr r0

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