1*a30d4efbSEtienne Carriere/* SPDX-License-Identifier: BSD-3-Clause */ 2*a30d4efbSEtienne Carriere/* 3*a30d4efbSEtienne Carriere * Copyright (c) 2018, STMicroelectronics 4*a30d4efbSEtienne Carriere */ 5*a30d4efbSEtienne Carriere 6*a30d4efbSEtienne Carriere#include <arm32.h> 7*a30d4efbSEtienne Carriere#include <arm32_macros.S> 8*a30d4efbSEtienne Carriere#include <asm.S> 9*a30d4efbSEtienne Carriere 10*a30d4efbSEtienne Carriere.section .text 11*a30d4efbSEtienne Carriere.balign 4 12*a30d4efbSEtienne Carriere.code 32 13*a30d4efbSEtienne Carriere 14*a30d4efbSEtienne Carriere#define STM32MP1_NSACR_PRESERVE_MASK (0xfff << 20) 15*a30d4efbSEtienne Carriere 16*a30d4efbSEtienne CarriereFUNC plat_cpu_reset_early , : 17*a30d4efbSEtienne Carriere ldr r0, =SCR_SIF 18*a30d4efbSEtienne Carriere write_scr r0 19*a30d4efbSEtienne Carriere 20*a30d4efbSEtienne Carriere read_nsacr r0 21*a30d4efbSEtienne Carriere mov_imm r1, STM32MP1_NSACR_PRESERVE_MASK 22*a30d4efbSEtienne Carriere and r0, r0, r1 23*a30d4efbSEtienne Carriere write_nsacr r0 24*a30d4efbSEtienne Carriere 25*a30d4efbSEtienne Carriere isb 26*a30d4efbSEtienne Carriere bx lr 27*a30d4efbSEtienne CarriereEND_FUNC plat_cpu_reset_early 28