1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright (c) 2019, HiSilicon Technologies Co., Ltd. 4 */ 5 6/* 7 * Entry points for the Hi3519AV100 a53 aarch32 mode init. 8 * It is assumed no stack is available when these routines are called. 9 * It is assumed each routine is called with return address in LR 10 * and with ARM registers R0, R1, R2, R3 being scratched. 11 */ 12 13#include <arm.h> 14#include <arm32_macros.S> 15#include <asm.S> 16#include <platform_config.h> 17 18#define CCI_BASE 0x04528000 19#define CPUECTLR_A53_SMPEN BIT(6) 20#define ACTRL_CPUECTLR BIT(1) 21#define HACTRL_CPUECTLR BIT(1) 22 23.section .text 24.balign 4 25.code 32 26 27/* 28 * Hi3519AV100 a53 aarch32 configuration early configuration 29 * 30 * Use scratch registers R0-R3. 31 * No stack usage. 32 * LR store return address. 33 * Trap CPU in case of error. 34 */ 35FUNC plat_cpu_reset_early , : 36 /* 37 * Write the CPU Extended Control Register 38 * Set the SMPEN bit, this Cortex-A53 core's register 39 */ 40 mrrc p15, 1, r0, r1, c15 41 orr r0, r0, #CPUECTLR_A53_SMPEN 42 mcrr p15, 1, r0, r1, c15 43 44 /* 45 * Enable Non-Secure EL1 write access to CPUECTLR 46 */ 47 mrs r1, cpsr 48 cps #CPSR_MODE_MON 49 50 read_scr r0 51 orr r0, r0, #SCR_NS /* Set NS bit in SCR */ 52 write_scr r0 53 isb 54 55 /* Write HACTLR register */ 56 mrc p15, 4, r2, c1, c0, 1 57 orr r2, r2, #HACTRL_CPUECTLR 58 mcr p15, 4, r2, c1, c0, 1 59 60 bic r0, r0, #SCR_NS /* Clr NS bit in SCR */ 61 write_scr r0 62 isb 63 64 /* Write ACTLR register */ 65 mrc p15, 0, r2, c1, c0, 1 66 orr r2, r2, #ACTRL_CPUECTLR 67 mcr p15, 0, r2, c1, c0, 1 68 69 msr cpsr, r1 70 /* 71 * Enable cci for secondary core 72 */ 73 mov r3, lr 74 bl __get_core_pos 75 mov lr, r3 76 cmp r0, #0 77 beq out 78 ldr r0, =CCI_BASE 79 ldr r1, [r0] 80 orr r1, r1, #BIT(9) /* bit 9 set to 1 */ 81 str r1, [r0] 82out: 83 bx lr 84END_FUNC plat_cpu_reset_early 85