11bb92983SJerome Forissier/* SPDX-License-Identifier: BSD-2-Clause */ 2abe38974SJens Wiklander/* 39dc1c9edSEtienne Carriere * Copyright (c) 2014-2016, STMicroelectronics International N.V. 4abe38974SJens Wiklander */ 5abe38974SJens Wiklander 68b572859SEtienne Carriere#include <arm32.h> 7abe38974SJens Wiklander#include <arm32_macros.S> 885fe04ffSPeng Fan#include <arm32_macros_cortex_a9.S> 9a0fdab65SJens Wiklander#include <asm.S> 108b572859SEtienne Carriere#include <kernel/tz_ssvce_def.h> 118b572859SEtienne Carriere#include <platform_config.h> 12abe38974SJens Wiklander 13abe38974SJens Wiklander.section .text 14abe38974SJens Wiklander.balign 4 15abe38974SJens Wiklander.code 32 16abe38974SJens Wiklander 17abe38974SJens Wiklander/* 18aaf56f28SJens Wiklander * void arm_cl2_enable(vaddr_t pl310_base) - Memory Cache Level2 Enable Function 19abe38974SJens Wiklander * 20abe38974SJens Wiklander * If PL310 supports FZLW, enable also FZL in A9 core 21abe38974SJens Wiklander * 22abe38974SJens Wiklander * Use scratables registers R0-R3. 23abe38974SJens Wiklander * No stack usage. 24abe38974SJens Wiklander * LR store return address. 25abe38974SJens Wiklander * Trap CPU in case of error. 26abe38974SJens Wiklander * TODO: to be moved to PL310 code (tz_svce_pl310.S ?) 27abe38974SJens Wiklander */ 28a0fdab65SJens WiklanderFUNC arm_cl2_enable , : 29abe38974SJens Wiklander /* Enable PL310 ctrl -> only set lsb bit */ 30abe38974SJens Wiklander mov r1, #0x1 31aaf56f28SJens Wiklander str r1, [r0, #PL310_CTRL] 32abe38974SJens Wiklander 33abe38974SJens Wiklander /* if L2 FLZW enable, enable in L1 */ 34aaf56f28SJens Wiklander ldr r1, [r0, #PL310_AUX_CTRL] 35abe38974SJens Wiklander tst r1, #(1 << 0) /* test AUX_CTRL[FLZ] */ 369dc1c9edSEtienne Carriere read_actlr r0 37abe38974SJens Wiklander orrne r0, r0, #(1 << 3) /* enable ACTLR[FLZW] */ 389dc1c9edSEtienne Carriere write_actlr r0 39abe38974SJens Wiklander 40abe38974SJens Wiklander mov pc, lr 41a0fdab65SJens WiklanderEND_FUNC arm_cl2_enable 42abe38974SJens Wiklander 43abe38974SJens Wiklander/* 44abe38974SJens Wiklander * Cortex A9 configuration early configuration 45abe38974SJens Wiklander * 46abe38974SJens Wiklander * Use scratables registers R0-R3. 47abe38974SJens Wiklander * No stack usage. 48abe38974SJens Wiklander * LR store return address. 49abe38974SJens Wiklander * Trap CPU in case of error. 50abe38974SJens Wiklander */ 51a0fdab65SJens WiklanderFUNC plat_cpu_reset_early , : 52*665fa256SJens Wiklander /* CPSR.A can be modified in any security state. */ 53*665fa256SJens Wiklander mov_imm r0, SCR_AW 54*665fa256SJens Wiklander write_scr r0 55*665fa256SJens Wiklander 56234b9045SEtienne Carriere mov_imm r0, CPU_SCTLR_INIT 57abe38974SJens Wiklander write_sctlr r0 58abe38974SJens Wiklander 59234b9045SEtienne Carriere mov_imm r0, CPU_ACTLR_INIT 60abe38974SJens Wiklander write_actlr r0 61abe38974SJens Wiklander 62234b9045SEtienne Carriere mov_imm r0, CPU_NSACR_INIT 63abe38974SJens Wiklander write_nsacr r0 64abe38974SJens Wiklander 65234b9045SEtienne Carriere mov_imm r0, CPU_PCR_INIT 66abe38974SJens Wiklander write_pcr r0 67abe38974SJens Wiklander 689dc1c9edSEtienne Carriere mov pc, lr 69a0fdab65SJens WiklanderEND_FUNC plat_cpu_reset_early 70abe38974SJens Wiklander 71