1*1bb92983SJerome Forissier/* SPDX-License-Identifier: BSD-2-Clause */ 2cd629100Syanyan-wrs/* 3cd629100Syanyan-wrs * Copyright (c) 2016, Wind River Systems. 4cd629100Syanyan-wrs * All rights reserved. 5cd629100Syanyan-wrs * 6cd629100Syanyan-wrs * Redistribution and use in source and binary forms, with or without 7cd629100Syanyan-wrs * modification, are permitted provided that the following conditions are met: 8cd629100Syanyan-wrs * 9cd629100Syanyan-wrs * 1. Redistributions of source code must retain the above copyright notice, 10cd629100Syanyan-wrs * this list of conditions and the following disclaimer. 11cd629100Syanyan-wrs * 12cd629100Syanyan-wrs * 2. Redistributions in binary form must reproduce the above copyright notice, 13cd629100Syanyan-wrs * this list of conditions and the following disclaimer in the documentation 14cd629100Syanyan-wrs * and/or other materials provided with the distribution. 15cd629100Syanyan-wrs * 16cd629100Syanyan-wrs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17cd629100Syanyan-wrs * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18cd629100Syanyan-wrs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19cd629100Syanyan-wrs * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20cd629100Syanyan-wrs * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21cd629100Syanyan-wrs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22cd629100Syanyan-wrs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23cd629100Syanyan-wrs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24cd629100Syanyan-wrs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25cd629100Syanyan-wrs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26cd629100Syanyan-wrs * POSSIBILITY OF SUCH DAMAGE. 27cd629100Syanyan-wrs */ 28cd629100Syanyan-wrs 29cd629100Syanyan-wrs/* 30cd629100Syanyan-wrs * Entry points for the A9 inits, A9 revision specific or not. 31cd629100Syanyan-wrs * It is assume no stack is available when these routines are called. 32cd629100Syanyan-wrs * It is assume each routine is called with return address in LR 33cd629100Syanyan-wrs * and with ARM registers R0, R1, R2, R3 being scratchable. 34cd629100Syanyan-wrs */ 35cd629100Syanyan-wrs 36cd629100Syanyan-wrs#include <arm32.h> 37cd629100Syanyan-wrs#include <arm32_macros.S> 38cd629100Syanyan-wrs#include <asm.S> 39cd629100Syanyan-wrs#include <platform_config.h> 40cd629100Syanyan-wrs 41cd629100Syanyan-wrs.section .text 42cd629100Syanyan-wrs.balign 4 43cd629100Syanyan-wrs.code 32 44cd629100Syanyan-wrs 45cd629100Syanyan-wrs/* 46cd629100Syanyan-wrs * platform early configuration 47cd629100Syanyan-wrs * 48cd629100Syanyan-wrs * Use scratables registers R0-R3. 49cd629100Syanyan-wrs * No stack usage. 50cd629100Syanyan-wrs * LR store return address. 51cd629100Syanyan-wrs * Trap CPU in case of error. 52cd629100Syanyan-wrs */ 53cd629100Syanyan-wrsFUNC plat_cpu_reset_early , : 54cd629100Syanyan-wrs /* 55cd629100Syanyan-wrs * Disallow NSec to mask FIQ [bit4: FW=0] 56cd629100Syanyan-wrs * Allow NSec to manage Imprecise Abort [bit5: AW=1] 57cd629100Syanyan-wrs * Imprecise Abort trapped to Abort Mode [bit3: EA=0] 58cd629100Syanyan-wrs * In Sec world, FIQ trapped to FIQ Mode [bit2: FIQ=0] 59cd629100Syanyan-wrs * IRQ always trapped to IRQ Mode [bit1: IRQ=0] 60cd629100Syanyan-wrs * Secure World [bit0: NS=0] 61cd629100Syanyan-wrs */ 62cd629100Syanyan-wrs mov r0, #SCR_AW 63cd629100Syanyan-wrs write_scr r0 /* write Secure Configuration Register */ 64cd629100Syanyan-wrs 65cd629100Syanyan-wrs /* 66cd629100Syanyan-wrs * Mandated HW config loaded 67cd629100Syanyan-wrs * 68cd629100Syanyan-wrs * SCTLR = 0x00000000 69cd629100Syanyan-wrs * 705c42fc05SEtienne Carriere * ACTRL = 0x00000040 715c42fc05SEtienne Carriere * - core NOT booted in full SMP (FW bit0=0) 72cd629100Syanyan-wrs * 735c42fc05SEtienne Carriere * NSACR = 0x00000C00 74cd629100Syanyan-wrs * - NSec cannot change ACTRL.SMP (NS_SMP bit18=0) 75cd629100Syanyan-wrs * - NSec can use SIMD/VFP (CP10/CP11) (bit15:14=2b00, bit11:10=2b11) 76cd629100Syanyan-wrs */ 77234b9045SEtienne Carriere mov_imm r0, 0x00000000 78cd629100Syanyan-wrs write_sctlr r0 79cd629100Syanyan-wrs 80234b9045SEtienne Carriere mov_imm r0, 0x00000040 81cd629100Syanyan-wrs write_actlr r0 82cd629100Syanyan-wrs 83234b9045SEtienne Carriere mov_imm r0, 0x00000C00 84cd629100Syanyan-wrs write_nsacr r0 85cd629100Syanyan-wrs 86cd629100Syanyan-wrs mov pc, lr 87cd629100Syanyan-wrsEND_FUNC plat_cpu_reset_early 88