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Searched refs:cidcfgr (Results 1 – 11 of 11) sorted by relevance

/optee_os/core/include/drivers/
H A Dstm32_rif.h69 static inline bool stm32_rif_scid_ok(uint32_t cidcfgr, uint32_t scid_m, in stm32_rif_scid_ok() argument
72 return (cidcfgr & scid_m) == in stm32_rif_scid_ok()
74 !(cidcfgr & _CIDCFGR_SEMEN); in stm32_rif_scid_ok()
88 static inline bool stm32_rif_semaphore_enabled_and_ok(uint32_t cidcfgr, in stm32_rif_semaphore_enabled_and_ok() argument
91 return (cidcfgr & _CIDCFGR_CFEN) && (cidcfgr & _CIDCFGR_SEMEN) && in stm32_rif_semaphore_enabled_and_ok()
92 (cidcfgr & _CIDCFGR_SEMWL(cid_to_check)); in stm32_rif_semaphore_enabled_and_ok()
116 TEE_Result stm32_rif_check_access(uint32_t cidcfgr,
166 static inline bool stm32_rif_scid_ok(uint32_t cidcfgr __unused, in stm32_rif_scid_ok()
174 stm32_rif_semaphore_enabled_and_ok(uint32_t cidcfgr __unused, in stm32_rif_semaphore_enabled_and_ok()
189 stm32_rif_check_access(uint32_t cidcfgr __unused, in stm32_rif_check_access()
/optee_os/core/drivers/firewall/
H A Dstm32_rif.c37 TEE_Result stm32_rif_check_access(uint32_t cidcfgr, in stm32_rif_check_access() argument
44 if (!(cidcfgr & _CIDCFGR_CFEN)) in stm32_rif_check_access()
47 if (stm32_rif_scid_ok(cidcfgr, scid_mask, cid_to_check)) in stm32_rif_check_access()
50 if (stm32_rif_semaphore_enabled_and_ok(cidcfgr, cid_to_check)) { in stm32_rif_check_access()
H A Dstm32_rifsc.c746 uint32_t cidcfgr = 0; in stm32_rifsc_check_access() local
765 cidcfgr = io_read32(rifsc_base + _RIFSC_RISC_PER0_CIDCFGR + in stm32_rifsc_check_access()
779 if (!(cidcfgr & _CIDCFGR_CFEN)) in stm32_rifsc_check_access()
782 if ((cidcfgr & _CIDCFGR_SEMEN && in stm32_rifsc_check_access()
783 !stm32_rif_semaphore_enabled_and_ok(cidcfgr, cid_to_check)) || in stm32_rifsc_check_access()
784 (!(cidcfgr & _CIDCFGR_SEMEN) && in stm32_rifsc_check_access()
785 !stm32_rif_scid_ok(cidcfgr, RIFSC_RISC_CIDCFGR_SCID_MASK, in stm32_rifsc_check_access()
799 uint32_t cidcfgr = 0; in stm32_rifsc_acquire_access() local
820 cidcfgr = io_read32(rifsc_base + _RIFSC_RISC_PER0_CIDCFGR + in stm32_rifsc_acquire_access()
828 if (!(cidcfgr & _CIDCFGR_CFEN)) in stm32_rifsc_acquire_access()
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H A Dstm32_risab.c89 uint32_t cidcfgr; member
162 uint32_t cidcfgr = io_read32(risab_base(risab_d) + in regs_access_granted() local
170 if (!(cidcfgr & _RISAB_PG_CIDCFGR_CFEN)) in regs_access_granted()
174 if (is_tdcid && !(cidcfgr & _RISAB_PG_CIDCFGR_DCEN)) in regs_access_granted()
178 if (cidcfgr & _RISAB_PG_CIDCFGR_DCEN && in regs_access_granted()
179 ((cidcfgr & _RISAB_PG_CIDCFGR_DDCID_MASK) >> in regs_access_granted()
229 subr_cfg->cidcfgr); in set_cidcfgr()
424 subr_cfg->cidcfgr |= _RISAB_PG_CIDCFGR_CFEN; in parse_risab_rif_conf()
427 subr_cfg->cidcfgr |= _RISAB_PG_CIDCFGR_DCEN; in parse_risab_rif_conf()
437 subr_cfg->cidcfgr |= ddcid; in parse_risab_rif_conf()
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H A Dstm32_risaf.c566 uint32_t cidcfgr = 0; in stm32_risaf_acquire_access() local
605 cidcfgr = io_read32(base + _RISAF_REG_CIDCFGR(id)); in stm32_risaf_acquire_access()
617 (read && !_RISAF_REG_READ_OK(cidcfgr, RIF_CID1)) || in stm32_risaf_acquire_access()
618 (write && !_RISAF_REG_WRITE_OK(cidcfgr, RIF_CID1)))) { in stm32_risaf_acquire_access()
/optee_os/core/drivers/
H A Dstm32_fmc.c102 uint32_t cidcfgr = 0; in handle_available_semaphores() local
109 cidcfgr = io_read32(fmc_d->base + _FMC_CIDCFGR(i)); in handle_available_semaphores()
111 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) in handle_available_semaphores()
324 uint32_t cidcfgr = io_read32(fmc_d->base + _FMC_CIDCFGR(i)); in check_fmc_rif_conf() local
337 res = stm32_rif_check_access(cidcfgr, semcr, MAX_CID_SUPPORTED, in check_fmc_rif_conf()
351 uint32_t cidcfgr = 0; in configure_fmc() local
358 cidcfgr = io_read32(fmc_d->base + _FMC_CIDCFGR(0)); in configure_fmc()
364 if (stm32_rif_check_access(cidcfgr, semcr, MAX_CID_SUPPORTED, RIF_CID1)) in configure_fmc()
373 if (cidcfgr & _CIDCFGR_SEMEN && in configure_fmc()
H A Dstm32_gpio.c452 uint32_t cidcfgr = 0; in pin_is_accessible() local
460 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin)); in pin_is_accessible()
462 if (!(cidcfgr & _CIDCFGR_CFEN)) { in pin_is_accessible()
465 } else if (stm32_rif_scid_ok(cidcfgr, GPIO_CIDCFGR_SCID_MASK, in pin_is_accessible()
469 } else if (stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) { in pin_is_accessible()
483 uint32_t cidcfgr = 0; in acquire_rif_semaphore_if_needed() local
492 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin)); in acquire_rif_semaphore_if_needed()
494 if (stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) in acquire_rif_semaphore_if_needed()
515 uint32_t cidcfgr = 0; in release_rif_semaphore_if_acquired() local
524 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin)); in release_rif_semaphore_if_acquired()
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H A Dstm32_hpdma.c95 uint32_t cidcfgr = 0; in handle_available_semaphores() local
102 cidcfgr = io_read32(hpdma_d->base + _HPDMA_CIDCFGR(i)); in handle_available_semaphores()
104 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) in handle_available_semaphores()
H A Dstm32_rtc.c277 uint32_t cidcfgr = io_read32(get_base() + RTC_CIDCFGR(resource)); in cid1_has_access() local
279 return !(cidcfgr & _CIDCFGR_CFEN) || in cid1_has_access()
280 get_field_u32(cidcfgr, RTC_CIDCFGR_SCID_MASK) == RIF_CID1; in cid1_has_access()
/optee_os/core/drivers/clk/
H A Dclk-stm32mp21.c3487 uint32_t cidcfgr = 0; in handle_available_semaphores() local
3499 cidcfgr = io_read32(pdata->rcc_base + RCC_CIDCFGR(i)); in handle_available_semaphores()
3501 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) in handle_available_semaphores()
H A Dclk-stm32mp25.c3563 uint32_t cidcfgr = 0; in handle_available_semaphores() local
3574 cidcfgr = io_read32(pdata->rcc_base + RCC_CIDCFGR(i)); in handle_available_semaphores()
3576 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) in handle_available_semaphores()