452 	uint32_t cidcfgr = 0;  in pin_is_accessible()  local
460 	cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin));  in pin_is_accessible()
462 	if (!(cidcfgr & _CIDCFGR_CFEN)) {  in pin_is_accessible()
465 	} else if (stm32_rif_scid_ok(cidcfgr, GPIO_CIDCFGR_SCID_MASK,  in pin_is_accessible()
469 	} else if (stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) {  in pin_is_accessible()
483 	uint32_t cidcfgr = 0;  in acquire_rif_semaphore_if_needed()  local
492 	cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin));  in acquire_rif_semaphore_if_needed()
494 	if (stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1))  in acquire_rif_semaphore_if_needed()
515 	uint32_t cidcfgr = 0;  in release_rif_semaphore_if_acquired()  local
524 	cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin));  in release_rif_semaphore_if_acquired()
526 	if (stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1) &&  in release_rif_semaphore_if_acquired()
942 	uint32_t cidcfgr = 0;  in handle_available_semaphores()  local
949 		cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(i));  in handle_available_semaphores()
951 		if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1))  in handle_available_semaphores()