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Searched refs:GENMASK_32 (Results 1 – 25 of 120) sorted by relevance

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/optee_os/core/include/drivers/
H A Dstm32mp13_rcc.h245 #define RCC_MP_APRSTCR_RSTTO_MASK GENMASK_32(14, 8)
249 #define RCC_MP_APRSTSR_RSTTOV_MASK GENMASK_32(14, 8)
253 #define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK_32(21, 0)
343 #define RCC_BDCR_LSEDRV_MASK GENMASK_32(5, 4)
347 #define RCC_BDCR_RTCSRC_MASK GENMASK_32(17, 16)
362 #define RCC_RDLSICR_MRD_MASK GENMASK_32(20, 16)
364 #define RCC_RDLSICR_EADLY_MASK GENMASK_32(26, 24)
366 #define RCC_RDLSICR_SPARE_MASK GENMASK_32(31, 27)
410 #define RCC_HSICFGR_HSIDIV_MASK GENMASK_32(1, 0)
412 #define RCC_HSICFGR_HSITRIM_MASK GENMASK_32(14, 8)
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H A Dstm32mp1_rcc.h238 #define RCC_OFFSET_MASK GENMASK_32(11, 0)
245 #define RCC_SELR_SRC_MASK GENMASK_32(2, 0)
246 #define RCC_SELR_REFCLK_SRC_MASK GENMASK_32(1, 0)
272 #define RCC_DIVR_DIV_MASK GENMASK_32(5, 0)
276 #define RCC_APBXDIV_MASK GENMASK_32(2, 0)
277 #define RCC_MPUDIV_MASK GENMASK_32(2, 0)
278 #define RCC_AXIDIV_MASK GENMASK_32(2, 0)
279 #define RCC_MCUDIV_MASK GENMASK_32(3, 0)
295 #define RCC_BDCR_LSEDRV_MASK GENMASK_32(5, 4)
300 #define RCC_BDCR_RTCSRC_MASK GENMASK_32(17, 16)
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H A Daplic_priv.h32 #define APLIC_SOURCECFG_CHILDIDX_MASK GENMASK_32(9, 0)
33 #define APLIC_SOURCECFG_SM_MASK GENMASK_32(2, 0)
60 #define APLIC_TARGET_HART_IDX_MASK GENMASK_32(31, 18)
62 #define APLIC_TARGET_GUEST_IDX_MASK GENMASK_32(17, 12)
63 #define APLIC_TARGET_EIID_MASK GENMASK_32(10, 0)
64 #define APLIC_TARGET_IPRIO_MASK GENMASK_32(7, 0)
H A Dstm32mp21_rcc.h794 #define RCC_BDCR_LSEDRV_MASK GENMASK_32(5, 4)
800 #define RCC_BDCR_RTCSRC_MASK GENMASK_32(17, 16)
809 #define RCC_RDCR_MRD_MASK GENMASK_32(20, 16)
810 #define RCC_RDCR_EADLY_MASK GENMASK_32(27, 24)
813 #define RCC_C1MSRDCR_C1MSRD_MASK GENMASK_32(4, 0)
817 #define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK_32(21, 0)
964 #define RCC_HSICFGR_HSITRIM_MASK GENMASK_32(14, 8)
966 #define RCC_HSICFGR_HSICAL_MASK GENMASK_32(24, 16)
970 #define RCC_MSICFGR_MSITRIM_MASK GENMASK_32(12, 8)
972 #define RCC_MSICFGR_MSICAL_MASK GENMASK_32(23, 16)
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H A Dstm32mp25_rcc.h872 #define RCC_BDCR_LSEDRV_MASK GENMASK_32(5, 4)
879 #define RCC_BDCR_RTCSRC_MASK GENMASK_32(17, 16)
898 #define RCC_D3DCR_D3PERCKSEL_MASK GENMASK_32(17, 16)
903 #define RCC_D3DSR_D3STATE_MASK GENMASK_32(1, 0)
907 #define RCC_RDCR_MRD_MASK GENMASK_32(20, 16)
909 #define RCC_RDCR_EADLY_MASK GENMASK_32(27, 24)
913 #define RCC_C1MSRDCR_C1MSRD_MASK GENMASK_32(4, 0)
918 #define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK_32(21, 0)
1131 #define RCC_HSICFGR_HSITRIM_MASK GENMASK_32(14, 8)
1133 #define RCC_HSICFGR_HSICAL_MASK GENMASK_32(24, 16)
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H A Datmel_shdwc.h26 #define AT91_SHDW_WKUPDBC_MASK GENMASK_32(26, 24)
35 #define AT91_SHDW_WKUPIS_MASK GENMASK_32(31, 16)
40 #define AT91_SHDW_WKUPEN_MASK GENMASK_32(15, 0)
43 #define AT91_SHDW_WKUPT_MASK GENMASK_32(31, 16)
H A Dstpmic1.h88 #define LDO_VOLTAGE_MASK GENMASK_32(6, 2)
89 #define BUCK_VOLTAGE_MASK GENMASK_32(7, 2)
96 #define LDO_BUCK_PULL_DOWN_MASK GENMASK_32(1, 0)
137 #define VINLOW_HYST_MASK GENMASK_32(5, 4)
139 #define VINLOW_THRESHOLD_MASK GENMASK_32(3, 1)
142 #define VINLOW_CTRL_REG_MASK GENMASK_32(7, 0)
/optee_os/core/arch/arm/plat-imx/registers/
H A Dimx6.h127 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_MASK GENMASK_32(10, 5)
130 #define IOMUXC_GPR10_OCRAM_TZ_EN_MASK GENMASK_32(4, 4)
133 #define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_MASK GENMASK_32(20, 20)
135 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_MASK GENMASK_32(26, 21)
138 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_MASK_6UL GENMASK_32(15, 11)
140 #define IOMUXC_GPR10_OCRAM_TZ_EN_MASK_6UL GENMASK_32(10, 10)
143 #define IOMUXC_GPR10_OCRAM_TZ_EN_LOCK_MASK_6UL GENMASK_32(26, 26)
145 #define IOMUXC_GPR10_OCRAM_TZ_ADDR_LOCK_MASK_6UL GENMASK_32(31, 27)
H A Dimx7.h68 #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_MASK GENMASK_32(13, 11)
71 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_MASK GENMASK_32(10, 10)
74 #define IOMUXC_GPR11_OCRAM_S_TZ_EN_LOCK_MASK GENMASK_32(26, 26)
75 #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_LOCK_OFFSET GENMASK_32(29, 27)
/optee_os/core/include/dt-bindings/clock/
H A Dstm32mp21-clksrc.h38 #define FLEX_ID_MASK GENMASK_32(25, 20)
39 #define FLEX_SEL_MASK GENMASK_32(19, 16)
40 #define FLEX_PDIV_MASK GENMASK_32(15, 6)
41 #define FLEX_FDIV_MASK GENMASK_32(5, 0)
52 #define CLK_ADDR_MASK GENMASK_32(30, 16)
53 #define CLK_ADDR_VAL_MASK GENMASK_32(15, 0)
175 #define OBS_ID_MASK GENMASK_32(14, 14)
176 #define OBS_STATUS_MASK GENMASK_32(13, 13)
177 #define OBS_INTEXT_MASK GENMASK_32(12, 12)
178 #define OBS_DIV_MASK GENMASK_32(11, 9)
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H A Dstm32mp25-clksrc.h37 #define CLK_ID_MASK GENMASK_32(20, 12)
41 #define CLK_DIV_MASK GENMASK_32(10, 5)
45 #define CLK_SEL_MASK GENMASK_32(3, 0)
65 #define FLEX_ID_MASK GENMASK_32(18, 13)
66 #define FLEX_SEL_MASK GENMASK_32(12, 9)
67 #define FLEX_PDIV_MASK GENMASK_32(8, 6)
68 #define FLEX_FDIV_MASK GENMASK_32(5, 0)
222 #define OBS_ID_MASK GENMASK_32(14, 14)
223 #define OBS_STATUS_MASK GENMASK_32(13, 13)
224 #define OBS_INTEXT_MASK GENMASK_32(12, 12)
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/optee_os/core/arch/arm/plat-stm32mp2/
H A Dstm32_sysconf.h21 ((offset) & GENMASK_32(15, 0)))
58 #define CA35SS_SSC_PLL_FREQ1_FBDIV_MASK GENMASK_32(11, 0)
61 #define CA35SS_SSC_PLL_FREQ1_REFDIV_MASK GENMASK_32(21, 16)
70 #define CA35SS_SSC_PLL_FREQ2_POSTDIV1_MASK GENMASK_32(2, 0)
73 #define CA35SS_SSC_PLL_FREQ2_POSTDIV2_MASK GENMASK_32(5, 3)
76 #define CA35SS_SSC_PLL_FREQ2_MASK GENMASK_32(5, 0)
/optee_os/core/include/dt-bindings/firewall/
H A Dstm32mp25-risab.h31 #define RISAB_PLIST_MASK GENMASK_32(7, 0)
32 #define RISAB_RLIST_MASK GENMASK_32(15, 8)
33 #define RISAB_WLIST_MASK GENMASK_32(23, 16)
34 #define RISAB_DCCID_MASK GENMASK_32(30, 27)
H A Dstm32mp25-risaf.h30 #define DT_RISAF_ENC_MASK GENMASK_32(7, 6)
31 #define DT_RISAF_PRIV_MASK GENMASK_32(15, 8)
32 #define DT_RISAF_READ_MASK GENMASK_32(23, 16)
33 #define DT_RISAF_WRITE_MASK GENMASK_32(31, 24)
/optee_os/core/drivers/imx/mu/
H A Dimx_mu_8q.c21 #define MU_CR_GIE_MASK GENMASK_32(31, 28)
22 #define MU_CR_RIE_MASK GENMASK_32(27, 24)
23 #define MU_CR_TIE_MASK GENMASK_32(23, 20)
24 #define MU_CR_GIR_MASK GENMASK_32(19, 16)
25 #define MU_CR_F_MASK GENMASK_32(2, 0)
/optee_os/core/drivers/scmi-msg/
H A Dperf_domain.h35 #define SCMI_PERF_ATTRIBUTES_NUM_DOMAINS_MASK GENMASK_32(15, 0)
60 #define SCMI_PERF_DOMAIN_RATE_LIMIT_MASK GENMASK_32(15, 0)
77 #define SCMI_PERF_LEVEL_ATTRIBUTES_LATENCY_US_MASK GENMASK_32(15, 0)
90 #define SCMI_PERF_NUM_LEVELS_NUM_LEVELS_MASK GENMASK_32(11, 0)
91 #define SCMI_PERF_NUM_LEVELS_REMAINING_LEVELS_MASK GENMASK_32(31, 16)
H A Dvoltage_domain.h29 #define SCMI_VOLTAGE_DOMAIN_COUNT_MASK GENMASK_32(15, 0)
53 #define SCMI_VOLTD_LEVELS_REMAINING_MASK GENMASK_32(31, 16)
61 #define SCMI_VOLTD_LEVELS_COUNT_MASK GENMASK_32(11, 0)
101 #define SCMI_VOLTAGE_DOMAIN_CONFIG_MASK GENMASK_32(3, 0)
H A Dclock.h29 #define SCMI_CLOCK_CLOCK_COUNT_MASK GENMASK_32(15, 0)
30 #define SCMI_CLOCK_MAX_PENDING_TRANSITIONS_MASK GENMASK_32(23, 16)
118 #define SCMI_CLOCK_DESCRIBE_RATES_REMAINING_MASK GENMASK_32(31, 16)
124 #define SCMI_CLOCK_DESCRIBE_RATES_COUNT_MASK GENMASK_32(11, 0)
/optee_os/core/arch/arm/plat-sam/
H A Dsam_sfr.h28 #define AT91_UTMICKTRIM_FREQ GENMASK_32(1, 0)
30 #define AT91_OHCIICR_USB_SUSPEND GENMASK_32(10, 8)
33 #define AT91_SFR_AICREDIR_KEY_MASK GENMASK_32(31, 1)
/optee_os/core/drivers/
H A Dstm32_rtc.c54 #define RTC_TR_SU_MASK GENMASK_32(3, 0)
55 #define RTC_TR_ST_MASK GENMASK_32(6, 4)
57 #define RTC_TR_MNU_MASK GENMASK_32(11, 8)
59 #define RTC_TR_MNT_MASK GENMASK_32(14, 12)
61 #define RTC_TR_HU_MASK GENMASK_32(19, 16)
63 #define RTC_TR_HT_MASK GENMASK_32(21, 20)
67 #define RTC_DR_DU_MASK GENMASK_32(3, 0)
68 #define RTC_DR_DT_MASK GENMASK_32(5, 4)
70 #define RTC_DR_MU_MASK GENMASK_32(11, 8)
74 #define RTC_DR_WDU_MASK GENMASK_32(15, 13)
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H A Ddra7_rng.c49 #define RNG_CONTROL_STARTUP_CYCLES_MASK GENMASK_32(31, 16)
52 #define RNG_CONFIG_MAX_REFIL_CYCLES_MASK GENMASK_32(31, 16)
54 #define RNG_CONFIG_MIN_REFIL_CYCLES_MASK GENMASK_32(7, 0)
57 #define RNG_ALARMCNT_ALARM_TH_MASK GENMASK_32(7, 0)
59 #define RNG_ALARMCNT_SHUTDOWN_TH_MASK GENMASK_32(20, 16)
67 #define RNG_FRO_MASK GENMASK_32(23, 0)
H A Datmel_rtc.c34 #define RTC_MR_CORR_MASK GENMASK_32(6, 0)
65 #define RTC_TIME_HOUR_MASK GENMASK_32(5, 0)
67 #define RTC_TIME_MIN_MASK GENMASK_32(6, 0)
69 #define RTC_TIME_SEC_MASK GENMASK_32(6, 0)
73 #define RTC_CAL_DATE_MASK GENMASK_32(5, 0)
75 #define RTC_CAL_DAY_MASK GENMASK_32(2, 0)
77 #define RTC_CAL_MONTH_MASK GENMASK_32(4, 0)
79 #define RTC_CAL_YEAR_MASK GENMASK_32(7, 0)
81 #define RTC_CAL_CENT_MASK GENMASK_32(6, 0)
/optee_os/core/arch/arm/plat-k3/drivers/
H A Deip76d_trng.c42 #define RNG_CONTROL_STARTUP_CYCLES_MASK GENMASK_32(31, 16)
45 #define RNG_CONFIG_MAX_REFIL_CYCLES_MASK GENMASK_32(31, 16)
47 #define RNG_CONFIG_MIN_REFIL_CYCLES_MASK GENMASK_32(7, 0)
50 #define RNG_ALARMCNT_ALARM_TH_MASK GENMASK_32(7, 0)
52 #define RNG_ALARMCNT_SHUTDOWN_TH_MASK GENMASK_32(20, 16)
60 #define RNG_FRO_MASK GENMASK_32(23, 0)
/optee_os/core/drivers/firewall/
H A Dstm32_iac.c28 #define _IAC_HWCFGR2_CFG1_MASK GENMASK_32(3, 0)
30 #define _IAC_HWCFGR2_CFG2_MASK GENMASK_32(7, 4)
34 #define _IAC_HWCFGR1_CFG1_MASK GENMASK_32(3, 0)
36 #define _IAC_HWCFGR1_CFG2_MASK GENMASK_32(7, 4)
38 #define _IAC_HWCFGR1_CFG3_MASK GENMASK_32(11, 8)
40 #define _IAC_HWCFGR1_CFG4_MASK GENMASK_32(15, 12)
42 #define _IAC_HWCFGR1_CFG5_MASK GENMASK_32(24, 16)
46 #define _IAC_VERR_MINREV_MASK GENMASK_32(3, 0)
48 #define _IAC_VERR_MAJREV_MASK GENMASK_32(7, 4)
/optee_os/core/arch/arm/include/
H A Dffa.h105 #define FFA_FEATURES_FEATURE_ID_MASK GENMASK_32(7, 0)
128 #define FFA_MSG_TYPE_MASK GENMASK_32(7, 0)
169 #define FFA_MEM_PERM_DATA_PERM GENMASK_32(1, 0)
177 #define FFA_MEM_PERM_RESERVED GENMASK_32(31, 3)
221 #define FFA_MEMORY_HANDLE_PRTN_MASK GENMASK_32(16, 0)
228 #define FFA_BOOT_INFO_TYPE_ID_MASK GENMASK_32(6, 0)
233 #define FFA_BOOT_INFO_FLAG_NAME_FORMAT_MASK GENMASK_32(1, 0)
239 #define FFA_BOOT_INFO_FLAG_CONTENT_FORMAT_MASK GENMASK_32(3, 2)
247 #define FFA_CONSOLE_LOG_CHAR_COUNT_MASK GENMASK_32(7, 0)
253 #define FFA_MEMORY_TRANSACTION_TYPE_MASK GENMASK_32(4, 3)

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