1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (C) 2022-2024, STMicroelectronics 4 */ 5 6 #ifndef _DT_BINDINGS_FIREWALL_STM32MP25_RISAB_H 7 #define _DT_BINDINGS_FIREWALL_STM32MP25_RISAB_H 8 9 /* RISAB control modes */ 10 #define RIF_DDCID_DIS 0x0 11 #define RIF_DDCID_EN 0x1 12 13 #define RISAB_READ_LIST_SHIFT 8 14 #define RISAB_WRITE_LIST_SHIFT 16 15 #define RISAB_CFEN_SHIFT 24 16 #define RISAB_DPRIV_SHIFT 25 17 #define RISAB_SEC_SHIFT 26 18 #define RISAB_DCCID_SHIFT 27 19 #define RISAB_DCEN_SHIFT 31 20 21 #define RISABPROT(delegate_en, delegate_cid, sec, default_priv, \ 22 enabled, cid_read_list, cid_write_list, cid_priv_list) \ 23 (((delegate_en) << RISAB_DCEN_SHIFT) | \ 24 ((delegate_cid) << RISAB_DCCID_SHIFT) | \ 25 ((sec) << RISAB_SEC_SHIFT) | ((default_priv) << RISAB_DPRIV_SHIFT) | \ 26 ((enabled) << RISAB_CFEN_SHIFT) | \ 27 ((cid_write_list) << RISAB_WRITE_LIST_SHIFT) | \ 28 ((cid_read_list) << RISAB_READ_LIST_SHIFT) | (cid_priv_list)) 29 30 /* RISABPROT macro masks */ 31 #define RISAB_PLIST_MASK GENMASK_32(7, 0) 32 #define RISAB_RLIST_MASK GENMASK_32(15, 8) 33 #define RISAB_WLIST_MASK GENMASK_32(23, 16) 34 #define RISAB_DCCID_MASK GENMASK_32(30, 27) 35 36 #endif /* _DT_BINDINGS_FIREWALL_STM32MP25_RISAB_H */ 37