xref: /optee_os/core/drivers/scmi-msg/perf_domain.h (revision f1cec17a35226380e01b5d50ce42736f584827dd)
1*f1cec17aSPascal Paillet /* SPDX-License-Identifier: BSD-3-Clause */
2*f1cec17aSPascal Paillet /*
3*f1cec17aSPascal Paillet  * Copyright (c) 2015-2020, Arm Limited and Contributors. All rights reserved.
4*f1cec17aSPascal Paillet  * Copyright (c) 2021, Linaro Limited
5*f1cec17aSPascal Paillet  * Copyright (c) 2024, STMicroelectronics
6*f1cec17aSPascal Paillet  */
7*f1cec17aSPascal Paillet #ifndef SCMI_MSG_PERF_DOMAIN_H
8*f1cec17aSPascal Paillet #define SCMI_MSG_PERF_DOMAIN_H
9*f1cec17aSPascal Paillet 
10*f1cec17aSPascal Paillet #include <stdint.h>
11*f1cec17aSPascal Paillet #include <util.h>
12*f1cec17aSPascal Paillet 
13*f1cec17aSPascal Paillet #include "common.h"
14*f1cec17aSPascal Paillet 
15*f1cec17aSPascal Paillet #define SCMI_PROTOCOL_VERSION_PERF_DOMAIN	0x10000
16*f1cec17aSPascal Paillet 
17*f1cec17aSPascal Paillet /*
18*f1cec17aSPascal Paillet  * Identifiers of the SCMI Performance Domain Management Protocol commands
19*f1cec17aSPascal Paillet  */
20*f1cec17aSPascal Paillet enum scmi_perf_domain_command_id {
21*f1cec17aSPascal Paillet 	SCMI_PERF_DOMAIN_ATTRIBUTES = 0x3,
22*f1cec17aSPascal Paillet 	SCMI_PERF_DESCRIBE_LEVELS = 0x4,
23*f1cec17aSPascal Paillet 	SCMI_PERF_LIMITS_SET = 0x5,		/* Not supported */
24*f1cec17aSPascal Paillet 	SCMI_PERF_LIMITS_GET = 0x6,		/* Not supported */
25*f1cec17aSPascal Paillet 	SCMI_PERF_LEVEL_SET = 0x7,
26*f1cec17aSPascal Paillet 	SCMI_PERF_LEVEL_GET = 0x8,
27*f1cec17aSPascal Paillet 	SCMI_PERF_NOTIFY_LIMITS = 0x9,		/* Not supported */
28*f1cec17aSPascal Paillet 	SCMI_PERF_NOTIFY_LEVEL = 0xa,		/* Not supported */
29*f1cec17aSPascal Paillet };
30*f1cec17aSPascal Paillet 
31*f1cec17aSPascal Paillet /*
32*f1cec17aSPascal Paillet  * Payloads for SCMI_PROTOCOL_ATTRIBUTES for Performance Domains
33*f1cec17aSPascal Paillet  */
34*f1cec17aSPascal Paillet #define SCMI_PERF_ATTRIBUTES_POWER_MW_BIT	BIT(16)
35*f1cec17aSPascal Paillet #define SCMI_PERF_ATTRIBUTES_NUM_DOMAINS_MASK	GENMASK_32(15, 0)
36*f1cec17aSPascal Paillet 
37*f1cec17aSPascal Paillet #define SCMI_PERF_PROTOCOL_ATTRIBUTES(_power_mw, _num_domains) \
38*f1cec17aSPascal Paillet 	(((_power_mw) ? SCMI_PERF_ATTRIBUTES_POWER_MW_BIT : 0) | \
39*f1cec17aSPascal Paillet 	 ((_num_domains) & SCMI_PERF_ATTRIBUTES_NUM_DOMAINS_MASK))
40*f1cec17aSPascal Paillet 
41*f1cec17aSPascal Paillet struct scmi_perf_protocol_attributes_p2a {
42*f1cec17aSPascal Paillet 	int32_t status;
43*f1cec17aSPascal Paillet 	uint32_t attributes;
44*f1cec17aSPascal Paillet 	uint32_t statistics_address_low;
45*f1cec17aSPascal Paillet 	uint32_t statistics_address_high;
46*f1cec17aSPascal Paillet 	uint32_t statistics_len;
47*f1cec17aSPascal Paillet };
48*f1cec17aSPascal Paillet 
49*f1cec17aSPascal Paillet /*
50*f1cec17aSPascal Paillet  * Payloads for SCMI_PERF_DOMAIN_ATTRIBUTES
51*f1cec17aSPascal Paillet  */
52*f1cec17aSPascal Paillet struct scmi_perf_attributes_a2p {
53*f1cec17aSPascal Paillet 	uint32_t domain_id;
54*f1cec17aSPascal Paillet };
55*f1cec17aSPascal Paillet 
56*f1cec17aSPascal Paillet /* Macro for scmi_perf_domain_attributes_p2a:attributes */
57*f1cec17aSPascal Paillet #define SCMI_PERF_DOMAIN_ATTRIBUTES_CAN_SET_LEVEL	BIT(30)
58*f1cec17aSPascal Paillet 
59*f1cec17aSPascal Paillet /* Macro for scmi_perf_domain_attributes_p2a:rate_limit */
60*f1cec17aSPascal Paillet #define SCMI_PERF_DOMAIN_RATE_LIMIT_MASK	GENMASK_32(15, 0)
61*f1cec17aSPascal Paillet 
62*f1cec17aSPascal Paillet /* Macro for scmi_perf_domain_attributes_p2a:name */
63*f1cec17aSPascal Paillet #define SCMI_PERF_DOMAIN_ATTR_NAME_SZ		16
64*f1cec17aSPascal Paillet 
65*f1cec17aSPascal Paillet struct scmi_perf_attributes_p2a {
66*f1cec17aSPascal Paillet 	int32_t status;
67*f1cec17aSPascal Paillet 	uint32_t attributes;
68*f1cec17aSPascal Paillet 	uint32_t rate_limit;
69*f1cec17aSPascal Paillet 	uint32_t sustained_freq;
70*f1cec17aSPascal Paillet 	uint32_t sustained_perf_level;
71*f1cec17aSPascal Paillet 	char name[SCMI_PERF_DOMAIN_ATTR_NAME_SZ];
72*f1cec17aSPascal Paillet };
73*f1cec17aSPascal Paillet 
74*f1cec17aSPascal Paillet /*
75*f1cec17aSPascal Paillet  * Payloads for SCMI_PERF_DESCRIBE_LEVELS
76*f1cec17aSPascal Paillet  */
77*f1cec17aSPascal Paillet #define SCMI_PERF_LEVEL_ATTRIBUTES_LATENCY_US_MASK	GENMASK_32(15, 0)
78*f1cec17aSPascal Paillet 
79*f1cec17aSPascal Paillet struct scmi_perf_level {
80*f1cec17aSPascal Paillet 	uint32_t performance_level;
81*f1cec17aSPascal Paillet 	uint32_t power_cost;
82*f1cec17aSPascal Paillet 	uint32_t attributes;
83*f1cec17aSPascal Paillet };
84*f1cec17aSPascal Paillet 
85*f1cec17aSPascal Paillet struct scmi_perf_describe_levels_a2p {
86*f1cec17aSPascal Paillet 	uint32_t domain_id;
87*f1cec17aSPascal Paillet 	uint32_t level_index;
88*f1cec17aSPascal Paillet };
89*f1cec17aSPascal Paillet 
90*f1cec17aSPascal Paillet #define SCMI_PERF_NUM_LEVELS_NUM_LEVELS_MASK		GENMASK_32(11, 0)
91*f1cec17aSPascal Paillet #define SCMI_PERF_NUM_LEVELS_REMAINING_LEVELS_MASK	GENMASK_32(31, 16)
92*f1cec17aSPascal Paillet #define SCMI_PERF_NUM_LEVELS_REMAINING_LEVELS_POS	16
93*f1cec17aSPascal Paillet 
94*f1cec17aSPascal Paillet #define SCMI_PERF_NUM_LEVELS(_num_levels, _rem_levels) \
95*f1cec17aSPascal Paillet 	(((_num_levels) & SCMI_PERF_NUM_LEVELS_NUM_LEVELS_MASK) | \
96*f1cec17aSPascal Paillet 	 (((_rem_levels) << SCMI_PERF_NUM_LEVELS_REMAINING_LEVELS_POS) & \
97*f1cec17aSPascal Paillet 	  SCMI_PERF_NUM_LEVELS_REMAINING_LEVELS_MASK))
98*f1cec17aSPascal Paillet 
99*f1cec17aSPascal Paillet struct scmi_perf_describe_levels_p2a {
100*f1cec17aSPascal Paillet 	int32_t status;
101*f1cec17aSPascal Paillet 	uint32_t num_levels;
102*f1cec17aSPascal Paillet 	struct scmi_perf_level perf_levels[];
103*f1cec17aSPascal Paillet };
104*f1cec17aSPascal Paillet 
105*f1cec17aSPascal Paillet /* Payloads for SCMI_PERF_LEVEL_SET */
106*f1cec17aSPascal Paillet struct scmi_perf_level_set_a2p {
107*f1cec17aSPascal Paillet 	uint32_t domain_id;
108*f1cec17aSPascal Paillet 	uint32_t performance_level;
109*f1cec17aSPascal Paillet };
110*f1cec17aSPascal Paillet 
111*f1cec17aSPascal Paillet struct scmi_perf_level_set_p2a {
112*f1cec17aSPascal Paillet 	int32_t status;
113*f1cec17aSPascal Paillet };
114*f1cec17aSPascal Paillet 
115*f1cec17aSPascal Paillet /* Payloads for SCMI_PERF_LEVEL_GET */
116*f1cec17aSPascal Paillet struct scmi_perf_level_get_a2p {
117*f1cec17aSPascal Paillet 	uint32_t domain_id;
118*f1cec17aSPascal Paillet };
119*f1cec17aSPascal Paillet 
120*f1cec17aSPascal Paillet struct scmi_perf_level_get_p2a {
121*f1cec17aSPascal Paillet 	int32_t status;
122*f1cec17aSPascal Paillet 	uint32_t performance_level;
123*f1cec17aSPascal Paillet };
124*f1cec17aSPascal Paillet 
125*f1cec17aSPascal Paillet #ifdef CFG_SCMI_MSG_PERF_DOMAIN
126*f1cec17aSPascal Paillet /*
127*f1cec17aSPascal Paillet  * scmi_msg_get_perf_handler - Return a handler for a performance domain message
128*f1cec17aSPascal Paillet  * @msg - message to process
129*f1cec17aSPascal Paillet  * Return a function handler for the message or NULL
130*f1cec17aSPascal Paillet  */
131*f1cec17aSPascal Paillet scmi_msg_handler_t scmi_msg_get_perf_handler(struct scmi_msg *msg);
132*f1cec17aSPascal Paillet #else
133*f1cec17aSPascal Paillet static inline
scmi_msg_get_perf_handler(struct scmi_msg * msg __unused)134*f1cec17aSPascal Paillet scmi_msg_handler_t scmi_msg_get_perf_handler(struct scmi_msg *msg __unused)
135*f1cec17aSPascal Paillet {
136*f1cec17aSPascal Paillet 	return NULL;
137*f1cec17aSPascal Paillet }
138*f1cec17aSPascal Paillet #endif
139*f1cec17aSPascal Paillet #endif /* SCMI_MSG_PERF_DOMAIN_H */
140