12a128a33SClement Faure /* SPDX-License-Identifier: BSD-2-Clause */ 22a128a33SClement Faure /* 32a128a33SClement Faure * Copyright 2017-2019 NXP 42a128a33SClement Faure */ 52a128a33SClement Faure #ifndef __IMX7_H__ 62a128a33SClement Faure #define __IMX7_H__ 72a128a33SClement Faure 8e05236a9SClement Faure #include <registers/imx7-crm.h> 9f9bfeacbSCedric Neveux 102a128a33SClement Faure #define GIC_BASE 0x31000000 112a128a33SClement Faure #define GIC_SIZE 0x8000 122a128a33SClement Faure #define GICC_OFFSET 0x2000 132a128a33SClement Faure #define GICD_OFFSET 0x1000 142a128a33SClement Faure 152a128a33SClement Faure #define CAAM_BASE 0x30900000 162866fd96SClement Faure #define CAAM_SIZE 0x40000 172a128a33SClement Faure #define UART1_BASE 0x30860000 182a128a33SClement Faure #define UART2_BASE 0x30890000 192a128a33SClement Faure #define UART3_BASE 0x30880000 202a128a33SClement Faure #define UART4_BASE 0x30A60000 212a128a33SClement Faure #define UART5_BASE 0x30A70000 222a128a33SClement Faure 232a128a33SClement Faure #define AIPS1_BASE 0x30000000 242a128a33SClement Faure #define AIPS1_SIZE 0x400000 252a128a33SClement Faure #define AIPS2_BASE 0x30400000 262a128a33SClement Faure #define AIPS2_SIZE 0x400000 272a128a33SClement Faure #define AIPS3_BASE 0x30800000 282a128a33SClement Faure #define AIPS3_SIZE 0x400000 292a128a33SClement Faure 302a128a33SClement Faure #define WDOG_BASE 0x30280000 312a128a33SClement Faure #define LPSR_BASE 0x30270000 322a128a33SClement Faure #define IOMUXC_BASE 0x30330000 332d75eb94SClement Faure #define IOMUXC_SIZE 0x4000 342a128a33SClement Faure #define IOMUXC_GPR_BASE 0x30340000 352a128a33SClement Faure #define OCOTP_BASE 0x30350000 360a8e42ddSClement Faure #define OCOTP_SIZE 0x10000 372a128a33SClement Faure #define ANATOP_BASE 0x30360000 382a128a33SClement Faure #define SNVS_BASE 0x30370000 39c76da3baSClement Faure #define SNVS_SIZE 0x10000 402a128a33SClement Faure #define CCM_BASE 0x30380000 410a8e42ddSClement Faure #define CCM_SIZE 0x10000 422a128a33SClement Faure #define SRC_BASE 0x30390000 433ef1e5aeSClement Faure #define SRC_SIZE 0x4000 442a128a33SClement Faure #define GPC_BASE 0x303A0000 45*e7778701SClement Faure #define GPC_SIZE 0x4000 462a128a33SClement Faure #define CSU_BASE 0x303E0000 472a128a33SClement Faure #define TZASC_BASE 0x30780000 48a4928cf1SClement Faure #define TZASC_SIZE 0x10000 492a128a33SClement Faure #define DDRC_PHY_BASE 0x30790000 502a128a33SClement Faure #define MMDC_P0_BASE 0x307A0000 512a128a33SClement Faure #define DDRC_BASE 0x307A0000 522a128a33SClement Faure #define IRAM_BASE 0x00900000 532a128a33SClement Faure #define IRAM_S_BASE 0x00180000 542a128a33SClement Faure 552a128a33SClement Faure #define CSU_CSL_START 0x0 562a128a33SClement Faure #define CSU_CSL_END 0x100 572a128a33SClement Faure #define CSU_ACCESS_ALL 0x00FF00FF 582a128a33SClement Faure #define CSU_SETTING_LOCK 0x01000100 59cab01ed5SRouven Czerwinski #define CSU_SA 0x218 602a128a33SClement Faure 612a128a33SClement Faure #define TRUSTZONE_OCRAM_START 0x180000 622a128a33SClement Faure 632a128a33SClement Faure #define IOMUXC_GPR9_OFFSET 0x24 642a128a33SClement Faure #define IOMUXC_GPR9_TZASC1_MUX_CONTROL_OFFSET 0 652a128a33SClement Faure 662a128a33SClement Faure #define IOMUXC_GPR11_OFFSET 0x2C 672a128a33SClement Faure #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_OFFSET 11 682a128a33SClement Faure #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_MASK GENMASK_32(13, 11) 692a128a33SClement Faure 702a128a33SClement Faure #define IOMUXC_GPR11_OCRAM_S_TZ_EN_OFFSET 10 712a128a33SClement Faure #define IOMUXC_GPR11_OCRAM_S_TZ_EN_MASK GENMASK_32(10, 10) 722a128a33SClement Faure 732a128a33SClement Faure #define IOMUXC_GPR11_OCRAM_S_TZ_EN_LOCK_OFFSET 26 742a128a33SClement Faure #define IOMUXC_GPR11_OCRAM_S_TZ_EN_LOCK_MASK GENMASK_32(26, 26) 752a128a33SClement Faure #define IOMUXC_GPR11_OCRAM_S_TZ_ADDR_LOCK_OFFSET GENMASK_32(29, 27) 762a128a33SClement Faure 77247f081aSClement Faure #define DIGPROG_OFFSET 0x800 78247f081aSClement Faure 792a128a33SClement Faure #endif /* __IMX7_H__ */ 80