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Searched refs:rkisp_set_bits (Results 1 – 17 of 17) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/media/platform/rockchip/isp/
H A Dcommon.h168 void rkisp_set_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val, bool is_direct);
199 rkisp_set_bits(dev, reg, mask, val, is_direct); in rkisp_unite_set_bits()
H A Dbridge.c168 rkisp_set_bits(dev->ispdev, MI_WR_CTRL2, in init_buf()
172 rkisp_set_bits(dev->ispdev, CIF_VI_DPCL, 0, in init_buf()
175 rkisp_set_bits(dev->ispdev, MI_WR_CTRL, 0, in init_buf()
178 rkisp_set_bits(dev->ispdev, MI_IMSC, 0, in init_buf()
H A Dcapture_v32.c521 rkisp_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL2, mask, val, true); in stream_self_update()
729 rkisp_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false); in mp_config_mi()
750 rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false); in mp_config_mi()
822 rkisp_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false); in sp_config_mi()
841 rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false); in sp_config_mi()
890 rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false); in bp_config_mi()
922 rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false); in ds_config_mi()
943 rkisp_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false); in mp_enable_mi()
960 rkisp_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false); in sp_enable_mi()
994 rkisp_set_bits(dev, 0x1814, 0, BIT(0), false); in mp_disable_mi()
[all …]
H A Dbridge_v20.c524 rkisp_set_bits(dev->ispdev, MI_WR_CTRL2, in config_gain()
817 rkisp_set_bits(dev->ispdev, CTRL_SWS_CFG, in config_mpfbc()
829 rkisp_set_bits(dev->ispdev, MI_WR_CTRL, MI_LUM_BURST_MASK, in config_mpfbc()
884 rkisp_set_bits(dev->ispdev, CTRL_SWS_CFG, 0, in config_mp()
887 rkisp_set_bits(dev->ispdev, CIF_MI_CTRL, 0, in config_mp()
902 rkisp_set_bits(dev->ispdev, CIF_MI_CTRL, MI_CTRL_MP_FMT_MASK, in config_mp()
H A Dcapture_v21.c714 rkisp_set_bits(dev, CIF_MI_XTD_FORMAT_CTRL, CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP, in mp_config_mi()
717 rkisp_set_bits(dev, CIF_MI_CTRL, GENMASK(19, 16) | MI_CTRL_MP_FMT_MASK, in mp_config_mi()
787 rkisp_set_bits(dev, CIF_MI_XTD_FORMAT_CTRL, CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP, in sp_config_mi()
790 rkisp_set_bits(dev, CIF_MI_CTRL, GENMASK(19, 16) | MI_CTRL_SP_FMT_MASK, in sp_config_mi()
943 rkisp_set_bits(stream->ispdev, CIF_MI_CTRL, in mp_enable_mi()
957 rkisp_set_bits(stream->ispdev, CIF_MI_CTRL, mask, val, false); in sp_enable_mi()
H A Dbridge_v30.c187 rkisp_set_bits(dev->ispdev, CIF_MI_CTRL, MI_CTRL_MP_FMT_MASK, in config_mp()
H A Dcsi.c315 rkisp_set_bits(dev, CSI2RX_DATA_IDS_1, mask, val, true); in csi_config()
320 rkisp_set_bits(dev->hw_dev->isp[i], in csi_config()
H A Disp_params_v21.c2571 rkisp_set_bits(params_vdev->dev, ISP_CTRL1, in isp_hdrdrc_enable()
2732 rkisp_set_bits(params_vdev->dev, ISP_CTRL1, in isp_dhaz_enable()
2992 rkisp_set_bits(params_vdev->dev, ISP_CTRL1, in isp_ynr_enable()
3066 rkisp_set_bits(params_vdev->dev, ISP_CTRL1, in isp_cnr_enable()
3306 rkisp_set_bits(params_vdev->dev, MI_RD_CTRL2, in isp_bay3d_enable()
3308 rkisp_set_bits(params_vdev->dev, MI_WR_CTRL2, in isp_bay3d_enable()
3312 rkisp_set_bits(params_vdev->dev, ISP_CTRL1, in isp_bay3d_enable()
3998 rkisp_set_bits(params_vdev->dev, ISP_CTRL1, in rkisp_params_first_cfg_v2x()
H A Disp_stats_v32.c527 rkisp_set_bits(dev, reg, 0, ctrl, false); in rkisp_stats_info2ddr()
1063 rkisp_set_bits(dev, ISP3X_SWS_CFG, 0, ISP3X_3A_DDR_WRITE_EN, false); in rkisp_stats_first_ddr_config_v32()
H A Disp_stats_v21.c1093 rkisp_set_bits(stats_vdev->dev, CTRL_SWS_CFG, SW_3A_DDR_WRITE_EN, in rkisp_stats_isr_v21()
1145 rkisp_set_bits(stats_vdev->dev, CTRL_SWS_CFG, SW_3A_DDR_WRITE_EN, in rkisp_stats_first_ddr_config_v21()
H A Dcommon.c65 void rkisp_set_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val, bool is_direct) in rkisp_set_bits() function
H A Dregs.c105 rkisp_set_bits(dev, reg, 0, val, false); in rkisp_config_dcrop()
H A Disp_stats_v2x.c1389 rkisp_set_bits(stats_vdev->dev, CTRL_SWS_CFG, SW_3A_DDR_WRITE_EN, in rkisp_stats_isr_v2x()
1480 rkisp_set_bits(stats_vdev->dev, CTRL_SWS_CFG, SW_3A_DDR_WRITE_EN, in rkisp_stats_first_ddr_config_v2x()
H A Drkisp.c698 rkisp_set_bits(dev, MI_WR_CTRL2, 0, val, true); in rkisp_trigger_read_back()
1213 rkisp_set_bits(dev, CIF_ISP_IMSC, 0, CIF_ISP_DATA_LOSS | CIF_ISP_PIC_SIZE_ERROR, true); in rkisp_reset_handle_v2x()
2153 rkisp_set_bits(dev, CIF_ISP_IMSC, 0, ISP3X_OUT_FRM_HALF, false); in rkisp_isp_start()
H A Disp_params_v32.c77 rkisp_set_bits(params_vdev->dev, reg, 0, bit_mask, false); in isp3_param_set_bits()
4851 rkisp_set_bits(params_vdev->dev, ISP3X_ISP_CTRL1, 0, in rkisp_params_first_cfg_v32()
4871 rkisp_set_bits(dev, ISP3X_ISP_CTRL0, 0, CIF_ISP_CTRL_ISP_CFG_UPD, true); in rkisp_params_first_cfg_v32()
H A Dregs_v2x.h2702 rkisp_set_bits(stream->ispdev, MI_RD_CTRL2, 0, BIT(30), false); in mi_raw_length()
H A Disp_params_v3x.c91 rkisp_set_bits(params_vdev->dev, reg, 0, bit_mask, false); in isp3_param_set_bits()
4429 rkisp_set_bits(params_vdev->dev, ISP3X_ISP_CTRL1, 0, in rkisp_params_first_cfg_v3x()