1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2021 Rockchip Electronics Co., Ltd. */
3
4 #include <media/v4l2-common.h>
5 #include <media/v4l2-ioctl.h>
6 #include <media/videobuf2-core.h>
7 #include <media/videobuf2-vmalloc.h> /* for ISP params */
8 #include "dev.h"
9 #include "regs.h"
10 #include "isp_params_v3x.h"
11
12 #define ISP3X_MODULE_EN BIT(0)
13 #define ISP3X_SELF_FORCE_UPD BIT(31)
14 #define ISP3X_REG_WR_MASK BIT(31) //disable write protect
15 #define ISP3X_NOBIG_OVERFLOW_SIZE (2688 * 1536)
16 #define ISP3X_AUTO_BIGMODE_WIDTH 2688
17 #define ISP3X_VIR2_NOBIG_OVERFLOW_SIZE (1920 * 1080)
18 #define ISP3X_VIR2_AUTO_BIGMODE_WIDTH 1920
19 #define ISP3X_VIR4_NOBIG_OVERFLOW_SIZE (1280 * 800)
20 #define ISP3X_VIR4_AUTO_BIGMODE_WIDTH 1280
21
22 #define ISP3X_VIR2_MAX_WIDTH 3840
23 #define ISP3X_VIR2_MAX_SIZE (3840 * 2160)
24 #define ISP3X_VIR4_MAX_WIDTH 2560
25 #define ISP3X_VIR4_MAX_SIZE (2560 * 1536)
26
27 static inline void
isp3_param_write_direct(struct rkisp_isp_params_vdev * params_vdev,u32 value,u32 addr,u32 id)28 isp3_param_write_direct(struct rkisp_isp_params_vdev *params_vdev,
29 u32 value, u32 addr, u32 id)
30 {
31 if (id == ISP3_LEFT)
32 rkisp_write(params_vdev->dev, addr, value, true);
33 else
34 rkisp_next_write(params_vdev->dev, addr, value, true);
35 }
36
37 static inline void
isp3_param_write(struct rkisp_isp_params_vdev * params_vdev,u32 value,u32 addr,u32 id)38 isp3_param_write(struct rkisp_isp_params_vdev *params_vdev,
39 u32 value, u32 addr, u32 id)
40 {
41 if (id == ISP3_LEFT)
42 rkisp_write(params_vdev->dev, addr, value, false);
43 else
44 rkisp_next_write(params_vdev->dev, addr, value, false);
45 }
46
47 static inline u32
isp3_param_read_direct(struct rkisp_isp_params_vdev * params_vdev,u32 addr,u32 id)48 isp3_param_read_direct(struct rkisp_isp_params_vdev *params_vdev,
49 u32 addr, u32 id)
50 {
51 u32 val;
52
53 if (id == ISP3_LEFT)
54 val = rkisp_read(params_vdev->dev, addr, true);
55 else
56 val = rkisp_next_read(params_vdev->dev, addr, true);
57 return val;
58 }
59
60 static inline u32
isp3_param_read(struct rkisp_isp_params_vdev * params_vdev,u32 addr,u32 id)61 isp3_param_read(struct rkisp_isp_params_vdev *params_vdev,
62 u32 addr, u32 id)
63 {
64 u32 val;
65
66 if (id == ISP3_LEFT)
67 val = rkisp_read(params_vdev->dev, addr, false);
68 else
69 val = rkisp_next_read(params_vdev->dev, addr, false);
70 return val;
71 }
72
73 static inline u32
isp3_param_read_cache(struct rkisp_isp_params_vdev * params_vdev,u32 addr,u32 id)74 isp3_param_read_cache(struct rkisp_isp_params_vdev *params_vdev,
75 u32 addr, u32 id)
76 {
77 u32 val;
78
79 if (id == ISP3_LEFT)
80 val = rkisp_read_reg_cache(params_vdev->dev, addr);
81 else
82 val = rkisp_next_read_reg_cache(params_vdev->dev, addr);
83 return val;
84 }
85
86 static inline void
isp3_param_set_bits(struct rkisp_isp_params_vdev * params_vdev,u32 reg,u32 bit_mask,u32 id)87 isp3_param_set_bits(struct rkisp_isp_params_vdev *params_vdev,
88 u32 reg, u32 bit_mask, u32 id)
89 {
90 if (id == ISP3_LEFT)
91 rkisp_set_bits(params_vdev->dev, reg, 0, bit_mask, false);
92 else
93 rkisp_next_set_bits(params_vdev->dev, reg, 0, bit_mask, false);
94 }
95
96 static inline void
isp3_param_clear_bits(struct rkisp_isp_params_vdev * params_vdev,u32 reg,u32 bit_mask,u32 id)97 isp3_param_clear_bits(struct rkisp_isp_params_vdev *params_vdev,
98 u32 reg, u32 bit_mask, u32 id)
99 {
100 if (id == ISP3_LEFT)
101 rkisp_clear_bits(params_vdev->dev, reg, bit_mask, false);
102 else
103 rkisp_next_clear_bits(params_vdev->dev, reg, bit_mask, false);
104 }
105
106 static void
isp_dpcc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_dpcc_cfg * arg,u32 id)107 isp_dpcc_config(struct rkisp_isp_params_vdev *params_vdev,
108 const struct isp2x_dpcc_cfg *arg, u32 id)
109 {
110 u32 value;
111 int i;
112
113 value = isp3_param_read(params_vdev, ISP3X_DPCC0_MODE, id);
114 value &= ISP_DPCC_EN;
115
116 value |= (arg->stage1_enable & 0x01) << 2 |
117 (arg->grayscale_mode & 0x01) << 1;
118 isp3_param_write(params_vdev, value, ISP3X_DPCC0_MODE, id);
119 isp3_param_write(params_vdev, value, ISP3X_DPCC1_MODE, id);
120 isp3_param_write(params_vdev, value, ISP3X_DPCC2_MODE, id);
121
122 value = (arg->sw_rk_out_sel & 0x03) << 5 |
123 (arg->sw_dpcc_output_sel & 0x01) << 4 |
124 (arg->stage1_rb_3x3 & 0x01) << 3 |
125 (arg->stage1_g_3x3 & 0x01) << 2 |
126 (arg->stage1_incl_rb_center & 0x01) << 1 |
127 (arg->stage1_incl_green_center & 0x01);
128 isp3_param_write(params_vdev, value, ISP3X_DPCC0_OUTPUT_MODE, id);
129 isp3_param_write(params_vdev, value, ISP3X_DPCC1_OUTPUT_MODE, id);
130 isp3_param_write(params_vdev, value, ISP3X_DPCC2_OUTPUT_MODE, id);
131
132 value = (arg->stage1_use_fix_set & 0x01) << 3 |
133 (arg->stage1_use_set_3 & 0x01) << 2 |
134 (arg->stage1_use_set_2 & 0x01) << 1 |
135 (arg->stage1_use_set_1 & 0x01);
136 isp3_param_write(params_vdev, value, ISP3X_DPCC0_SET_USE, id);
137 isp3_param_write(params_vdev, value, ISP3X_DPCC1_SET_USE, id);
138 isp3_param_write(params_vdev, value, ISP3X_DPCC2_SET_USE, id);
139
140 value = (arg->sw_rk_red_blue1_en & 0x01) << 13 |
141 (arg->rg_red_blue1_enable & 0x01) << 12 |
142 (arg->rnd_red_blue1_enable & 0x01) << 11 |
143 (arg->ro_red_blue1_enable & 0x01) << 10 |
144 (arg->lc_red_blue1_enable & 0x01) << 9 |
145 (arg->pg_red_blue1_enable & 0x01) << 8 |
146 (arg->sw_rk_green1_en & 0x01) << 5 |
147 (arg->rg_green1_enable & 0x01) << 4 |
148 (arg->rnd_green1_enable & 0x01) << 3 |
149 (arg->ro_green1_enable & 0x01) << 2 |
150 (arg->lc_green1_enable & 0x01) << 1 |
151 (arg->pg_green1_enable & 0x01);
152 isp3_param_write(params_vdev, value, ISP3X_DPCC0_METHODS_SET_1, id);
153 isp3_param_write(params_vdev, value, ISP3X_DPCC1_METHODS_SET_1, id);
154 isp3_param_write(params_vdev, value, ISP3X_DPCC2_METHODS_SET_1, id);
155
156 value = (arg->sw_rk_red_blue2_en & 0x01) << 13 |
157 (arg->rg_red_blue2_enable & 0x01) << 12 |
158 (arg->rnd_red_blue2_enable & 0x01) << 11 |
159 (arg->ro_red_blue2_enable & 0x01) << 10 |
160 (arg->lc_red_blue2_enable & 0x01) << 9 |
161 (arg->pg_red_blue2_enable & 0x01) << 8 |
162 (arg->sw_rk_green2_en & 0x01) << 5 |
163 (arg->rg_green2_enable & 0x01) << 4 |
164 (arg->rnd_green2_enable & 0x01) << 3 |
165 (arg->ro_green2_enable & 0x01) << 2 |
166 (arg->lc_green2_enable & 0x01) << 1 |
167 (arg->pg_green2_enable & 0x01);
168 isp3_param_write(params_vdev, value, ISP3X_DPCC0_METHODS_SET_2, id);
169 isp3_param_write(params_vdev, value, ISP3X_DPCC1_METHODS_SET_2, id);
170 isp3_param_write(params_vdev, value, ISP3X_DPCC2_METHODS_SET_2, id);
171
172 value = (arg->sw_rk_red_blue3_en & 0x01) << 13 |
173 (arg->rg_red_blue3_enable & 0x01) << 12 |
174 (arg->rnd_red_blue3_enable & 0x01) << 11 |
175 (arg->ro_red_blue3_enable & 0x01) << 10 |
176 (arg->lc_red_blue3_enable & 0x01) << 9 |
177 (arg->pg_red_blue3_enable & 0x01) << 8 |
178 (arg->sw_rk_green3_en & 0x01) << 5 |
179 (arg->rg_green3_enable & 0x01) << 4 |
180 (arg->rnd_green3_enable & 0x01) << 3 |
181 (arg->ro_green3_enable & 0x01) << 2 |
182 (arg->lc_green3_enable & 0x01) << 1 |
183 (arg->pg_green3_enable & 0x01);
184 isp3_param_write(params_vdev, value, ISP3X_DPCC0_METHODS_SET_3, id);
185 isp3_param_write(params_vdev, value, ISP3X_DPCC1_METHODS_SET_3, id);
186 isp3_param_write(params_vdev, value, ISP3X_DPCC2_METHODS_SET_3, id);
187
188 value = ISP_PACK_4BYTE(arg->line_thr_1_g, arg->line_thr_1_rb,
189 arg->sw_mindis1_g, arg->sw_mindis1_rb);
190 isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_THRESH_1, id);
191 isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_THRESH_1, id);
192 isp3_param_write(params_vdev, value, ISP3X_DPCC2_LINE_THRESH_1, id);
193
194 value = ISP_PACK_4BYTE(arg->line_mad_fac_1_g, arg->line_mad_fac_1_rb,
195 arg->sw_dis_scale_max1, arg->sw_dis_scale_min1);
196 isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_MAD_FAC_1, id);
197 isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_MAD_FAC_1, id);
198 isp3_param_write(params_vdev, value, ISP3X_DPCC2_LINE_MAD_FAC_1, id);
199
200 value = ISP_PACK_4BYTE(arg->pg_fac_1_g, arg->pg_fac_1_rb, 0, 0);
201 isp3_param_write(params_vdev, value, ISP3X_DPCC0_PG_FAC_1, id);
202 isp3_param_write(params_vdev, value, ISP3X_DPCC1_PG_FAC_1, id);
203 isp3_param_write(params_vdev, value, ISP3X_DPCC2_PG_FAC_1, id);
204
205 value = ISP_PACK_4BYTE(arg->rnd_thr_1_g, arg->rnd_thr_1_rb, 0, 0);
206 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_THRESH_1, id);
207 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_THRESH_1, id);
208 isp3_param_write(params_vdev, value, ISP3X_DPCC2_RND_THRESH_1, id);
209
210 value = ISP_PACK_4BYTE(arg->rg_fac_1_g, arg->rg_fac_1_rb, 0, 0);
211 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RG_FAC_1, id);
212 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RG_FAC_1, id);
213 isp3_param_write(params_vdev, value, ISP3X_DPCC2_RG_FAC_1, id);
214
215 value = ISP_PACK_4BYTE(arg->line_thr_2_g, arg->line_thr_2_rb,
216 arg->sw_mindis2_g, arg->sw_mindis2_rb);
217 isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_THRESH_2, id);
218 isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_THRESH_2, id);
219 isp3_param_write(params_vdev, value, ISP3X_DPCC2_LINE_THRESH_2, id);
220
221 value = ISP_PACK_4BYTE(arg->line_mad_fac_2_g, arg->line_mad_fac_2_rb,
222 arg->sw_dis_scale_max2, arg->sw_dis_scale_min2);
223 isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_MAD_FAC_2, id);
224 isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_MAD_FAC_2, id);
225 isp3_param_write(params_vdev, value, ISP3X_DPCC2_LINE_MAD_FAC_2, id);
226
227 value = ISP_PACK_4BYTE(arg->pg_fac_2_g, arg->pg_fac_2_rb, 0, 0);
228 isp3_param_write(params_vdev, value, ISP3X_DPCC0_PG_FAC_2, id);
229 isp3_param_write(params_vdev, value, ISP3X_DPCC1_PG_FAC_2, id);
230 isp3_param_write(params_vdev, value, ISP3X_DPCC2_PG_FAC_2, id);
231
232 value = ISP_PACK_4BYTE(arg->rnd_thr_2_g, arg->rnd_thr_2_rb, 0, 0);
233 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_THRESH_2, id);
234 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_THRESH_2, id);
235 isp3_param_write(params_vdev, value, ISP3X_DPCC2_RND_THRESH_2, id);
236
237 value = ISP_PACK_4BYTE(arg->rg_fac_2_g, arg->rg_fac_2_rb, 0, 0);
238 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RG_FAC_2, id);
239 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RG_FAC_2, id);
240 isp3_param_write(params_vdev, value, ISP3X_DPCC2_RG_FAC_2, id);
241
242 value = ISP_PACK_4BYTE(arg->line_thr_3_g, arg->line_thr_3_rb,
243 arg->sw_mindis3_g, arg->sw_mindis3_rb);
244 isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_THRESH_3, id);
245 isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_THRESH_3, id);
246 isp3_param_write(params_vdev, value, ISP3X_DPCC2_LINE_THRESH_3, id);
247
248 value = ISP_PACK_4BYTE(arg->line_mad_fac_3_g, arg->line_mad_fac_3_rb,
249 arg->sw_dis_scale_max3, arg->sw_dis_scale_min3);
250 isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_MAD_FAC_3, id);
251 isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_MAD_FAC_3, id);
252 isp3_param_write(params_vdev, value, ISP3X_DPCC2_LINE_MAD_FAC_3, id);
253
254 value = ISP_PACK_4BYTE(arg->pg_fac_3_g, arg->pg_fac_3_rb, 0, 0);
255 isp3_param_write(params_vdev, value, ISP3X_DPCC0_PG_FAC_3, id);
256 isp3_param_write(params_vdev, value, ISP3X_DPCC1_PG_FAC_3, id);
257 isp3_param_write(params_vdev, value, ISP3X_DPCC2_PG_FAC_3, id);
258
259 value = ISP_PACK_4BYTE(arg->rnd_thr_3_g, arg->rnd_thr_3_rb, 0, 0);
260 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_THRESH_3, id);
261 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_THRESH_3, id);
262 isp3_param_write(params_vdev, value, ISP3X_DPCC2_RND_THRESH_3, id);
263
264 value = ISP_PACK_4BYTE(arg->rg_fac_3_g, arg->rg_fac_3_rb, 0, 0);
265 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RG_FAC_3, id);
266 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RG_FAC_3, id);
267 isp3_param_write(params_vdev, value, ISP3X_DPCC2_RG_FAC_3, id);
268
269 value = (arg->ro_lim_3_rb & 0x03) << 10 |
270 (arg->ro_lim_3_g & 0x03) << 8 |
271 (arg->ro_lim_2_rb & 0x03) << 6 |
272 (arg->ro_lim_2_g & 0x03) << 4 |
273 (arg->ro_lim_1_rb & 0x03) << 2 |
274 (arg->ro_lim_1_g & 0x03);
275 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RO_LIMITS, id);
276 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RO_LIMITS, id);
277 isp3_param_write(params_vdev, value, ISP3X_DPCC2_RO_LIMITS, id);
278
279 value = (arg->rnd_offs_3_rb & 0x03) << 10 |
280 (arg->rnd_offs_3_g & 0x03) << 8 |
281 (arg->rnd_offs_2_rb & 0x03) << 6 |
282 (arg->rnd_offs_2_g & 0x03) << 4 |
283 (arg->rnd_offs_1_rb & 0x03) << 2 |
284 (arg->rnd_offs_1_g & 0x03);
285 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_OFFS, id);
286 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_OFFS, id);
287 isp3_param_write(params_vdev, value, ISP3X_DPCC2_RND_OFFS, id);
288
289 value = (arg->bpt_rb_3x3 & 0x01) << 11 |
290 (arg->bpt_g_3x3 & 0x01) << 10 |
291 (arg->bpt_incl_rb_center & 0x01) << 9 |
292 (arg->bpt_incl_green_center & 0x01) << 8 |
293 (arg->bpt_use_fix_set & 0x01) << 7 |
294 (arg->bpt_use_set_3 & 0x01) << 6 |
295 (arg->bpt_use_set_2 & 0x01) << 5 |
296 (arg->bpt_use_set_1 & 0x01) << 4 |
297 (arg->bpt_cor_en & 0x01) << 1 |
298 (arg->bpt_det_en & 0x01);
299 isp3_param_write(params_vdev, value, ISP3X_DPCC0_BPT_CTRL, id);
300 isp3_param_write(params_vdev, value, ISP3X_DPCC1_BPT_CTRL, id);
301 isp3_param_write(params_vdev, value, ISP3X_DPCC2_BPT_CTRL, id);
302
303 isp3_param_write(params_vdev, arg->bp_number, ISP3X_DPCC0_BPT_NUMBER, id);
304 isp3_param_write(params_vdev, arg->bp_number, ISP3X_DPCC1_BPT_NUMBER, id);
305 isp3_param_write(params_vdev, arg->bp_number, ISP3X_DPCC2_BPT_NUMBER, id);
306 isp3_param_write(params_vdev, arg->bp_table_addr, ISP3X_DPCC0_BPT_ADDR, id);
307 isp3_param_write(params_vdev, arg->bp_table_addr, ISP3X_DPCC1_BPT_ADDR, id);
308 isp3_param_write(params_vdev, arg->bp_table_addr, ISP3X_DPCC2_BPT_ADDR, id);
309
310 value = ISP_PACK_2SHORT(arg->bpt_h_addr, arg->bpt_v_addr);
311 isp3_param_write(params_vdev, value, ISP3X_DPCC0_BPT_DATA, id);
312 isp3_param_write(params_vdev, value, ISP3X_DPCC1_BPT_DATA, id);
313 isp3_param_write(params_vdev, value, ISP3X_DPCC2_BPT_DATA, id);
314
315 isp3_param_write(params_vdev, arg->bp_cnt, ISP3X_DPCC0_BP_CNT, id);
316 isp3_param_write(params_vdev, arg->bp_cnt, ISP3X_DPCC1_BP_CNT, id);
317 isp3_param_write(params_vdev, arg->bp_cnt, ISP3X_DPCC2_BP_CNT, id);
318
319 isp3_param_write(params_vdev, arg->sw_pdaf_en, ISP3X_DPCC0_PDAF_EN, id);
320 isp3_param_write(params_vdev, arg->sw_pdaf_en, ISP3X_DPCC1_PDAF_EN, id);
321 isp3_param_write(params_vdev, arg->sw_pdaf_en, ISP3X_DPCC2_PDAF_EN, id);
322
323 value = 0;
324 for (i = 0; i < ISP3X_DPCC_PDAF_POINT_NUM; i++)
325 value |= (arg->pdaf_point_en[i] & 0x01) << i;
326 isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_POINT_EN, id);
327 isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_POINT_EN, id);
328 isp3_param_write(params_vdev, value, ISP3X_DPCC2_PDAF_POINT_EN, id);
329
330 value = ISP_PACK_2SHORT(arg->pdaf_offsetx, arg->pdaf_offsety);
331 isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_OFFSET, id);
332 isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_OFFSET, id);
333 isp3_param_write(params_vdev, value, ISP3X_DPCC2_PDAF_OFFSET, id);
334
335 value = ISP_PACK_2SHORT(arg->pdaf_wrapx, arg->pdaf_wrapy);
336 isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_WRAP, id);
337 isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_WRAP, id);
338 isp3_param_write(params_vdev, value, ISP3X_DPCC2_PDAF_WRAP, id);
339
340 value = ISP_PACK_2SHORT(arg->pdaf_wrapx_num, arg->pdaf_wrapy_num);
341 isp3_param_write(params_vdev, value, ISP_DPCC0_PDAF_SCOPE, id);
342 isp3_param_write(params_vdev, value, ISP_DPCC1_PDAF_SCOPE, id);
343 isp3_param_write(params_vdev, value, ISP_DPCC2_PDAF_SCOPE, id);
344
345 for (i = 0; i < ISP3X_DPCC_PDAF_POINT_NUM / 2; i++) {
346 value = ISP_PACK_4BYTE(arg->point[2 * i].x, arg->point[2 * i].y,
347 arg->point[2 * i + 1].x, arg->point[2 * i + 1].y);
348 isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_POINT_0 + 4 * i, id);
349 isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_POINT_0 + 4 * i, id);
350 isp3_param_write(params_vdev, value, ISP3X_DPCC2_PDAF_POINT_0 + 4 * i, id);
351 }
352
353 isp3_param_write(params_vdev, arg->pdaf_forward_med, ISP3X_DPCC0_PDAF_FORWARD_MED, id);
354 isp3_param_write(params_vdev, arg->pdaf_forward_med, ISP3X_DPCC1_PDAF_FORWARD_MED, id);
355 isp3_param_write(params_vdev, arg->pdaf_forward_med, ISP3X_DPCC2_PDAF_FORWARD_MED, id);
356 }
357
358 static void
isp_dpcc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)359 isp_dpcc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
360 {
361 u32 value;
362
363 value = isp3_param_read(params_vdev, ISP3X_DPCC0_MODE, id);
364 value &= ~ISP_DPCC_EN;
365
366 if (en)
367 value |= ISP_DPCC_EN;
368 isp3_param_write(params_vdev, value, ISP3X_DPCC0_MODE, id);
369 isp3_param_write(params_vdev, value, ISP3X_DPCC1_MODE, id);
370 isp3_param_write(params_vdev, value, ISP3X_DPCC2_MODE, id);
371 }
372
373 static void
isp_bls_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_bls_cfg * arg,u32 id)374 isp_bls_config(struct rkisp_isp_params_vdev *params_vdev,
375 const struct isp21_bls_cfg *arg, u32 id)
376 {
377 const struct isp2x_bls_fixed_val *pval;
378 u32 new_control, value;
379
380 new_control = isp3_param_read(params_vdev, ISP3X_BLS_CTRL, id);
381 new_control &= ISP_BLS_ENA;
382
383 pval = &arg->bls1_val;
384 if (arg->bls1_en) {
385 new_control |= ISP_BLS_BLS1_EN;
386
387 switch (params_vdev->raw_type) {
388 case RAW_BGGR:
389 isp3_param_write(params_vdev, pval->r, ISP_BLS1_D_FIXED, id);
390 isp3_param_write(params_vdev, pval->gr, ISP_BLS1_C_FIXED, id);
391 isp3_param_write(params_vdev, pval->gb, ISP_BLS1_B_FIXED, id);
392 isp3_param_write(params_vdev, pval->b, ISP_BLS1_A_FIXED, id);
393 break;
394 case RAW_GBRG:
395 isp3_param_write(params_vdev, pval->r, ISP_BLS1_C_FIXED, id);
396 isp3_param_write(params_vdev, pval->gr, ISP_BLS1_D_FIXED, id);
397 isp3_param_write(params_vdev, pval->gb, ISP_BLS1_A_FIXED, id);
398 isp3_param_write(params_vdev, pval->b, ISP_BLS1_B_FIXED, id);
399 break;
400 case RAW_GRBG:
401 isp3_param_write(params_vdev, pval->r, ISP_BLS1_B_FIXED, id);
402 isp3_param_write(params_vdev, pval->gr, ISP_BLS1_A_FIXED, id);
403 isp3_param_write(params_vdev, pval->gb, ISP_BLS1_D_FIXED, id);
404 isp3_param_write(params_vdev, pval->b, ISP_BLS1_C_FIXED, id);
405 break;
406 case RAW_RGGB:
407 default:
408 isp3_param_write(params_vdev, pval->r, ISP_BLS1_A_FIXED, id);
409 isp3_param_write(params_vdev, pval->gr, ISP_BLS1_B_FIXED, id);
410 isp3_param_write(params_vdev, pval->gb, ISP_BLS1_C_FIXED, id);
411 isp3_param_write(params_vdev, pval->b, ISP_BLS1_D_FIXED, id);
412 break;
413 }
414 }
415
416 /* fixed subtraction values */
417 pval = &arg->fixed_val;
418 if (!arg->enable_auto) {
419 switch (params_vdev->raw_type) {
420 case RAW_BGGR:
421 isp3_param_write(params_vdev, pval->r, ISP_BLS_D_FIXED, id);
422 isp3_param_write(params_vdev, pval->gr, ISP_BLS_C_FIXED, id);
423 isp3_param_write(params_vdev, pval->gb, ISP_BLS_B_FIXED, id);
424 isp3_param_write(params_vdev, pval->b, ISP_BLS_A_FIXED, id);
425 break;
426 case RAW_GBRG:
427 isp3_param_write(params_vdev, pval->r, ISP_BLS_C_FIXED, id);
428 isp3_param_write(params_vdev, pval->gr, ISP_BLS_D_FIXED, id);
429 isp3_param_write(params_vdev, pval->gb, ISP_BLS_A_FIXED, id);
430 isp3_param_write(params_vdev, pval->b, ISP_BLS_B_FIXED, id);
431 break;
432 case RAW_GRBG:
433 isp3_param_write(params_vdev, pval->r, ISP_BLS_B_FIXED, id);
434 isp3_param_write(params_vdev, pval->gr, ISP_BLS_A_FIXED, id);
435 isp3_param_write(params_vdev, pval->gb, ISP_BLS_D_FIXED, id);
436 isp3_param_write(params_vdev, pval->b, ISP_BLS_C_FIXED, id);
437 break;
438 case RAW_RGGB:
439 default:
440 isp3_param_write(params_vdev, pval->r, ISP_BLS_A_FIXED, id);
441 isp3_param_write(params_vdev, pval->gr, ISP_BLS_B_FIXED, id);
442 isp3_param_write(params_vdev, pval->gb, ISP_BLS_C_FIXED, id);
443 isp3_param_write(params_vdev, pval->b, ISP_BLS_D_FIXED, id);
444 break;
445 }
446 } else {
447 if (arg->en_windows & BIT(1)) {
448 isp3_param_write(params_vdev, arg->bls_window2.h_offs, ISP3X_BLS_H2_START, id);
449 value = arg->bls_window2.h_offs + arg->bls_window2.h_size;
450 isp3_param_write(params_vdev, value, ISP3X_BLS_H2_STOP, id);
451 isp3_param_write(params_vdev, arg->bls_window2.v_offs, ISP3X_BLS_V2_START, id);
452 value = arg->bls_window2.v_offs + arg->bls_window2.v_size;
453 isp3_param_write(params_vdev, value, ISP3X_BLS_V2_STOP, id);
454 new_control |= ISP_BLS_WINDOW_2;
455 }
456
457 if (arg->en_windows & BIT(0)) {
458 isp3_param_write(params_vdev, arg->bls_window1.h_offs, ISP3X_BLS_H1_START, id);
459 value = arg->bls_window1.h_offs + arg->bls_window1.h_size;
460 isp3_param_write(params_vdev, value, ISP3X_BLS_H1_STOP, id);
461 isp3_param_write(params_vdev, arg->bls_window1.v_offs, ISP3X_BLS_V1_START, id);
462 value = arg->bls_window1.v_offs + arg->bls_window1.v_size;
463 isp3_param_write(params_vdev, value, ISP3X_BLS_V1_STOP, id);
464 new_control |= ISP_BLS_WINDOW_1;
465 }
466
467 isp3_param_write(params_vdev, arg->bls_samples, ISP3X_BLS_SAMPLES, id);
468
469 new_control |= ISP_BLS_MODE_MEASURED;
470 }
471 isp3_param_write(params_vdev, new_control, ISP3X_BLS_CTRL, id);
472 }
473
474 static void
isp_bls_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)475 isp_bls_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
476 {
477 u32 new_control;
478
479 new_control = isp3_param_read(params_vdev, ISP3X_BLS_CTRL, id);
480 if (en)
481 new_control |= ISP_BLS_ENA;
482 else
483 new_control &= ~ISP_BLS_ENA;
484 isp3_param_write(params_vdev, new_control, ISP3X_BLS_CTRL, id);
485 }
486
487 static void
isp_sdg_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_sdg_cfg * arg,u32 id)488 isp_sdg_config(struct rkisp_isp_params_vdev *params_vdev,
489 const struct isp2x_sdg_cfg *arg, u32 id)
490 {
491 int i;
492
493 isp3_param_write(params_vdev, arg->xa_pnts.gamma_dx0, ISP3X_ISP_GAMMA_DX_LO, id);
494 isp3_param_write(params_vdev, arg->xa_pnts.gamma_dx1, ISP3X_ISP_GAMMA_DX_HI, id);
495
496 for (i = 0; i < ISP3X_DEGAMMA_CURVE_SIZE; i++) {
497 isp3_param_write(params_vdev, arg->curve_r.gamma_y[i],
498 ISP3X_ISP_GAMMA_R_Y_0 + i * 4, id);
499 isp3_param_write(params_vdev, arg->curve_g.gamma_y[i],
500 ISP3X_ISP_GAMMA_G_Y_0 + i * 4, id);
501 isp3_param_write(params_vdev, arg->curve_b.gamma_y[i],
502 ISP3X_ISP_GAMMA_B_Y_0 + i * 4, id);
503 }
504 }
505
506 static void
isp_sdg_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)507 isp_sdg_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
508 {
509 if (en) {
510 isp3_param_set_bits(params_vdev,
511 ISP3X_ISP_CTRL0,
512 CIF_ISP_CTRL_ISP_GAMMA_IN_ENA, id);
513 } else {
514 isp3_param_clear_bits(params_vdev,
515 ISP3X_ISP_CTRL0,
516 CIF_ISP_CTRL_ISP_GAMMA_IN_ENA, id);
517 }
518 }
519
520 static void
isp_lsc_matrix_cfg_sram(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_lsc_cfg * pconfig,bool is_check,u32 id)521 isp_lsc_matrix_cfg_sram(struct rkisp_isp_params_vdev *params_vdev,
522 const struct isp3x_lsc_cfg *pconfig,
523 bool is_check, u32 id)
524 {
525 struct rkisp_device *dev = params_vdev->dev;
526 u32 sram_addr, data, table;
527 int i, j;
528
529 if (is_check &&
530 !(isp3_param_read(params_vdev, ISP3X_LSC_CTRL, id) & ISP_LSC_EN))
531 return;
532
533 table = isp3_param_read_direct(params_vdev, ISP3X_LSC_STATUS, id);
534 table &= ISP3X_LSC_ACTIVE_TABLE;
535 /* default table 0 for multi device */
536 if (!dev->hw_dev->is_single)
537 table = ISP3X_LSC_ACTIVE_TABLE;
538
539 /* CIF_ISP_LSC_TABLE_ADDRESS_153 = ( 17 * 18 ) >> 1 */
540 sram_addr = table ? ISP3X_LSC_TABLE_ADDRESS_0 : CIF_ISP_LSC_TABLE_ADDRESS_153;
541 isp3_param_write_direct(params_vdev, sram_addr, ISP3X_LSC_R_TABLE_ADDR, id);
542 isp3_param_write_direct(params_vdev, sram_addr, ISP3X_LSC_GR_TABLE_ADDR, id);
543 isp3_param_write_direct(params_vdev, sram_addr, ISP3X_LSC_GB_TABLE_ADDR, id);
544 isp3_param_write_direct(params_vdev, sram_addr, ISP3X_LSC_B_TABLE_ADDR, id);
545
546 /* program data tables (table size is 9 * 17 = 153) */
547 for (i = 0; i < CIF_ISP_LSC_SECTORS_MAX * CIF_ISP_LSC_SECTORS_MAX;
548 i += CIF_ISP_LSC_SECTORS_MAX) {
549 /*
550 * 17 sectors with 2 values in one DWORD = 9
551 * DWORDs (2nd value of last DWORD unused)
552 */
553 for (j = 0; j < CIF_ISP_LSC_SECTORS_MAX - 1; j += 2) {
554 data = ISP_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i + j],
555 pconfig->r_data_tbl[i + j + 1]);
556 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_R_TABLE_DATA, id);
557
558 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i + j],
559 pconfig->gr_data_tbl[i + j + 1]);
560 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_GR_TABLE_DATA, id);
561
562 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i + j],
563 pconfig->gb_data_tbl[i + j + 1]);
564 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_GB_TABLE_DATA, id);
565
566 data = ISP_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i + j],
567 pconfig->b_data_tbl[i + j + 1]);
568 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_B_TABLE_DATA, id);
569 }
570
571 data = ISP_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i + j], 0);
572 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_R_TABLE_DATA, id);
573
574 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i + j], 0);
575 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_GR_TABLE_DATA, id);
576
577 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i + j], 0);
578 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_GB_TABLE_DATA, id);
579
580 data = ISP_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i + j], 0);
581 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_B_TABLE_DATA, id);
582 }
583 isp3_param_write_direct(params_vdev, !table, ISP3X_LSC_TABLE_SEL, id);
584 }
585
586 static void
isp_lsc_cfg_sram_task(unsigned long data)587 isp_lsc_cfg_sram_task(unsigned long data)
588 {
589 struct rkisp_isp_params_vdev *params_vdev =
590 (struct rkisp_isp_params_vdev *)data;
591 struct isp3x_isp_params_cfg *params = params_vdev->isp3x_params;
592
593 isp_lsc_matrix_cfg_sram(params_vdev, ¶ms->others.lsc_cfg, true, 0);
594 if (params_vdev->dev->hw_dev->is_unite) {
595 params++;
596 isp_lsc_matrix_cfg_sram(params_vdev, ¶ms->others.lsc_cfg, true, 1);
597 }
598 }
599
600 static void
isp_lsc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_lsc_cfg * arg,u32 id)601 isp_lsc_config(struct rkisp_isp_params_vdev *params_vdev,
602 const struct isp3x_lsc_cfg *arg, u32 id)
603 {
604 struct rkisp_isp_params_val_v3x *priv_val =
605 (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
606 struct isp3x_isp_params_cfg *params_rec = params_vdev->isp3x_params + id;
607 struct rkisp_device *dev = params_vdev->dev;
608 unsigned int data;
609 u32 lsc_ctrl;
610 int i;
611
612 lsc_ctrl = isp3_param_read(params_vdev, ISP3X_LSC_CTRL, id);
613 params_rec->others.lsc_cfg = *arg;
614 if (dev->hw_dev->is_single &&
615 (lsc_ctrl & ISP_LSC_EN) &&
616 (id == ISP3_LEFT))
617 /* latest config for ISP3_LEFT, unite isp or single isp */
618 tasklet_schedule(&priv_val->lsc_tasklet);
619
620 for (i = 0; i < ISP3X_LSC_SIZE_TBL_SIZE / 4; i++) {
621 /* program x size tables */
622 data = CIF_ISP_LSC_SECT_SIZE(arg->x_size_tbl[i * 2],
623 arg->x_size_tbl[i * 2 + 1]);
624 isp3_param_write(params_vdev, data, ISP3X_LSC_XSIZE_01 + i * 4, id);
625 data = CIF_ISP_LSC_SECT_SIZE(arg->x_size_tbl[i * 2 + 8],
626 arg->x_size_tbl[i * 2 + 9]);
627 isp3_param_write(params_vdev, data, ISP3X_LSC_XSIZE_89 + i * 4, id);
628
629 /* program x grad tables */
630 data = CIF_ISP_LSC_SECT_SIZE(arg->x_grad_tbl[i * 2],
631 arg->x_grad_tbl[i * 2 + 1]);
632 isp3_param_write(params_vdev, data, ISP3X_LSC_XGRAD_01 + i * 4, id);
633 data = CIF_ISP_LSC_SECT_SIZE(arg->x_grad_tbl[i * 2 + 8],
634 arg->x_grad_tbl[i * 2 + 9]);
635 isp3_param_write(params_vdev, data, ISP3X_LSC_XGRAD_89 + i * 4, id);
636
637 /* program y size tables */
638 data = CIF_ISP_LSC_SECT_SIZE(arg->y_size_tbl[i * 2],
639 arg->y_size_tbl[i * 2 + 1]);
640 isp3_param_write(params_vdev, data, ISP3X_LSC_YSIZE_01 + i * 4, id);
641 data = CIF_ISP_LSC_SECT_SIZE(arg->y_size_tbl[i * 2 + 8],
642 arg->y_size_tbl[i * 2 + 9]);
643 isp3_param_write(params_vdev, data, ISP3X_LSC_YSIZE_89 + i * 4, id);
644
645 /* program y grad tables */
646 data = CIF_ISP_LSC_SECT_SIZE(arg->y_grad_tbl[i * 2],
647 arg->y_grad_tbl[i * 2 + 1]);
648 isp3_param_write(params_vdev, data, ISP3X_LSC_YGRAD_01 + i * 4, id);
649 data = CIF_ISP_LSC_SECT_SIZE(arg->y_grad_tbl[i * 2 + 8],
650 arg->y_grad_tbl[i * 2 + 9]);
651 isp3_param_write(params_vdev, data, ISP3X_LSC_YGRAD_89 + i * 4, id);
652 }
653
654 if (arg->sector_16x16)
655 lsc_ctrl |= ISP3X_LSC_SECTOR_16X16;
656 else
657 lsc_ctrl &= ~ISP3X_LSC_SECTOR_16X16;
658 if (!dev->hw_dev->is_single)
659 lsc_ctrl |= ISP3X_LSC_PRE_RD_ST_MODE;
660 isp3_param_write(params_vdev, lsc_ctrl, ISP3X_LSC_CTRL, id);
661 }
662
663 static void
isp_lsc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)664 isp_lsc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
665 {
666 struct isp3x_isp_params_cfg *params_rec = params_vdev->isp3x_params + id;
667 u32 val = isp3_param_read(params_vdev, ISP3X_LSC_CTRL, id);
668
669 if (en == !!(val & ISP_LSC_EN))
670 return;
671
672 if (en) {
673 isp3_param_set_bits(params_vdev, ISP3X_LSC_CTRL, ISP_LSC_EN, id);
674 if (params_vdev->dev->hw_dev->is_single)
675 isp_lsc_matrix_cfg_sram(params_vdev,
676 ¶ms_rec->others.lsc_cfg, false, id);
677 } else {
678 isp3_param_clear_bits(params_vdev, ISP3X_LSC_CTRL, ISP_LSC_EN, id);
679 isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(8), id);
680 }
681 }
682
683 static void
isp_debayer_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_debayer_cfg * arg,u32 id)684 isp_debayer_config(struct rkisp_isp_params_vdev *params_vdev,
685 const struct isp2x_debayer_cfg *arg, u32 id)
686 {
687 u32 value;
688
689 value = isp3_param_read(params_vdev, ISP3X_DEBAYER_CONTROL, id);
690 value &= ISP_DEBAYER_EN;
691
692 value |= (arg->filter_c_en & 0x01) << 8 |
693 (arg->filter_g_en & 0x01) << 4;
694 isp3_param_write(params_vdev, value, ISP3X_DEBAYER_CONTROL, id);
695
696 value = (arg->thed1 & 0x0F) << 12 |
697 (arg->thed0 & 0x0F) << 8 |
698 (arg->dist_scale & 0x0F) << 4 |
699 (arg->max_ratio & 0x07) << 1 |
700 (arg->clip_en & 0x01);
701 isp3_param_write(params_vdev, value, ISP3X_DEBAYER_G_INTERP, id);
702
703 value = (arg->filter1_coe5 & 0x0F) << 16 |
704 (arg->filter1_coe4 & 0x0F) << 12 |
705 (arg->filter1_coe3 & 0x0F) << 8 |
706 (arg->filter1_coe2 & 0x0F) << 4 |
707 (arg->filter1_coe1 & 0x0F);
708 isp3_param_write(params_vdev, value, ISP3X_DEBAYER_G_INTERP_FILTER1, id);
709
710 value = (arg->filter2_coe5 & 0x0F) << 16 |
711 (arg->filter2_coe4 & 0x0F) << 12 |
712 (arg->filter2_coe3 & 0x0F) << 8 |
713 (arg->filter2_coe2 & 0x0F) << 4 |
714 (arg->filter2_coe1 & 0x0F);
715 isp3_param_write(params_vdev, value, ISP3X_DEBAYER_G_INTERP_FILTER2, id);
716
717 value = (arg->hf_offset & 0xFFFF) << 16 |
718 (arg->gain_offset & 0x0F) << 8 |
719 (arg->offset & 0x1F);
720 isp3_param_write(params_vdev, value, ISP3X_DEBAYER_OFFSET, id);
721
722 value = (arg->shift_num & 0x03) << 16 |
723 (arg->order_max & 0x1F) << 8 |
724 (arg->order_min & 0x1F);
725 isp3_param_write(params_vdev, value, ISP3X_DEBAYER_C_FILTER, id);
726 }
727
728 static void
isp_debayer_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)729 isp_debayer_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
730 {
731 if (en)
732 isp3_param_set_bits(params_vdev,
733 ISP3X_DEBAYER_CONTROL,
734 ISP3X_MODULE_EN, id);
735 else
736 isp3_param_clear_bits(params_vdev,
737 ISP3X_DEBAYER_CONTROL,
738 ISP3X_MODULE_EN, id);
739 }
740
741 static void
isp_awbgain_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_awb_gain_cfg * arg,u32 id)742 isp_awbgain_config(struct rkisp_isp_params_vdev *params_vdev,
743 const struct isp21_awb_gain_cfg *arg, u32 id)
744 {
745 struct rkisp_device *dev = params_vdev->dev;
746
747 if (!arg->gain0_red || !arg->gain0_blue ||
748 !arg->gain1_red || !arg->gain1_blue ||
749 !arg->gain2_red || !arg->gain2_blue ||
750 !arg->gain0_green_r || !arg->gain0_green_b ||
751 !arg->gain1_green_r || !arg->gain1_green_b ||
752 !arg->gain2_green_r || !arg->gain2_green_b) {
753 dev_err(dev->dev, "awb gain is zero!\n");
754 return;
755 }
756
757 isp3_param_write(params_vdev,
758 ISP_PACK_2SHORT(arg->gain0_green_b, arg->gain0_green_r),
759 ISP3X_ISP_AWB_GAIN0_G, id);
760 isp3_param_write(params_vdev,
761 ISP_PACK_2SHORT(arg->gain0_blue, arg->gain0_red),
762 ISP3X_ISP_AWB_GAIN0_RB, id);
763
764 isp3_param_write(params_vdev,
765 ISP_PACK_2SHORT(arg->gain1_green_b, arg->gain1_green_r),
766 ISP3X_ISP_AWB_GAIN1_G, id);
767 isp3_param_write(params_vdev,
768 ISP_PACK_2SHORT(arg->gain1_blue, arg->gain1_red),
769 ISP3X_ISP_AWB_GAIN1_RB, id);
770
771 isp3_param_write(params_vdev,
772 ISP_PACK_2SHORT(arg->gain2_green_b, arg->gain2_green_r),
773 ISP3X_ISP_AWB_GAIN2_G, id);
774 isp3_param_write(params_vdev,
775 ISP_PACK_2SHORT(arg->gain2_blue, arg->gain2_red),
776 ISP3X_ISP_AWB_GAIN2_RB, id);
777 }
778
779 static void
isp_awbgain_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)780 isp_awbgain_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
781 {
782 if (en)
783 isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL0,
784 CIF_ISP_CTRL_ISP_AWB_ENA, id);
785 else
786 isp3_param_clear_bits(params_vdev, ISP3X_ISP_CTRL0,
787 CIF_ISP_CTRL_ISP_AWB_ENA, id);
788 }
789
790 static void
isp_ccm_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_ccm_cfg * arg,u32 id)791 isp_ccm_config(struct rkisp_isp_params_vdev *params_vdev,
792 const struct isp21_ccm_cfg *arg, u32 id)
793 {
794 u32 value;
795 u32 i;
796
797 value = isp3_param_read(params_vdev, ISP3X_CCM_CTRL, id);
798 value &= ISP_CCM_EN;
799
800 value |= (arg->highy_adjust_dis & 0x01) << 1;
801 isp3_param_write(params_vdev, value, ISP3X_CCM_CTRL, id);
802
803 value = ISP_PACK_2SHORT(arg->coeff0_r, arg->coeff1_r);
804 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_R, id);
805
806 value = ISP_PACK_2SHORT(arg->coeff2_r, arg->offset_r);
807 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_R, id);
808
809 value = ISP_PACK_2SHORT(arg->coeff0_g, arg->coeff1_g);
810 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_G, id);
811
812 value = ISP_PACK_2SHORT(arg->coeff2_g, arg->offset_g);
813 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_G, id);
814
815 value = ISP_PACK_2SHORT(arg->coeff0_b, arg->coeff1_b);
816 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_B, id);
817
818 value = ISP_PACK_2SHORT(arg->coeff2_b, arg->offset_b);
819 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_B, id);
820
821 value = ISP_PACK_2SHORT(arg->coeff0_y, arg->coeff1_y);
822 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_Y, id);
823
824 value = ISP_PACK_2SHORT(arg->coeff2_y, 0);
825 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_Y, id);
826
827 for (i = 0; i < ISP3X_CCM_CURVE_NUM / 2; i++) {
828 value = ISP_PACK_2SHORT(arg->alp_y[2 * i], arg->alp_y[2 * i + 1]);
829 isp3_param_write(params_vdev, value, ISP3X_CCM_ALP_Y0 + 4 * i, id);
830 }
831 value = ISP_PACK_2SHORT(arg->alp_y[2 * i], 0);
832 isp3_param_write(params_vdev, value, ISP3X_CCM_ALP_Y0 + 4 * i, id);
833
834 value = arg->bound_bit & 0x0F;
835 isp3_param_write(params_vdev, value, ISP3X_CCM_BOUND_BIT, id);
836 }
837
838 static void
isp_ccm_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)839 isp_ccm_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
840 {
841 if (en)
842 isp3_param_set_bits(params_vdev, ISP3X_CCM_CTRL, ISP_CCM_EN, id);
843 else
844 isp3_param_clear_bits(params_vdev, ISP3X_CCM_CTRL, ISP_CCM_EN, id);
845 }
846
847 static void
isp_goc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_gammaout_cfg * arg,u32 id)848 isp_goc_config(struct rkisp_isp_params_vdev *params_vdev,
849 const struct isp3x_gammaout_cfg *arg, u32 id)
850 {
851 int i;
852 u32 value;
853
854 value = isp3_param_read(params_vdev, ISP3X_GAMMA_OUT_CTRL, id);
855 value &= ISP3X_GAMMA_OUT_EN;
856 value |= (arg->equ_segm & 0x1) << 1 |
857 (arg->finalx4_dense_en & 0x1) << 2;
858 isp3_param_write(params_vdev, value, ISP3X_GAMMA_OUT_CTRL, id);
859
860 isp3_param_write(params_vdev, arg->offset, ISP3X_GAMMA_OUT_OFFSET, id);
861 for (i = 0; i < ISP3X_GAMMA_OUT_MAX_SAMPLES / 2; i++) {
862 value = ISP_PACK_2SHORT(arg->gamma_y[2 * i],
863 arg->gamma_y[2 * i + 1]);
864 isp3_param_write(params_vdev, value, ISP3X_GAMMA_OUT_Y0 + i * 4, id);
865 }
866 isp3_param_write(params_vdev, arg->gamma_y[2 * i], ISP3X_GAMMA_OUT_Y0 + i * 4, id);
867 }
868
869 static void
isp_goc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)870 isp_goc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
871 {
872 if (en)
873 isp3_param_set_bits(params_vdev, ISP3X_GAMMA_OUT_CTRL,
874 ISP3X_GAMMA_OUT_EN, id);
875 else
876 isp3_param_clear_bits(params_vdev, ISP3X_GAMMA_OUT_CTRL,
877 ISP3X_GAMMA_OUT_EN, id);
878 }
879
880 static void
isp_cproc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_cproc_cfg * arg,u32 id)881 isp_cproc_config(struct rkisp_isp_params_vdev *params_vdev,
882 const struct isp2x_cproc_cfg *arg, u32 id)
883 {
884 u32 quantization = params_vdev->quantization;
885
886 isp3_param_write(params_vdev, arg->contrast, ISP3X_CPROC_CONTRAST, id);
887 isp3_param_write(params_vdev, arg->hue, ISP3X_CPROC_HUE, id);
888 isp3_param_write(params_vdev, arg->sat, ISP3X_CPROC_SATURATION, id);
889 isp3_param_write(params_vdev, arg->brightness, ISP3X_CPROC_BRIGHTNESS, id);
890
891 if (quantization != V4L2_QUANTIZATION_FULL_RANGE) {
892 isp3_param_clear_bits(params_vdev, ISP3X_CPROC_CTRL,
893 CIF_C_PROC_YOUT_FULL |
894 CIF_C_PROC_COUT_FULL, id);
895 } else {
896 isp3_param_set_bits(params_vdev, ISP3X_CPROC_CTRL,
897 CIF_C_PROC_YOUT_FULL |
898 CIF_C_PROC_YIN_FULL |
899 CIF_C_PROC_COUT_FULL, id);
900 }
901 }
902
903 static void
isp_cproc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)904 isp_cproc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
905 {
906 if (en)
907 isp3_param_set_bits(params_vdev, ISP3X_CPROC_CTRL,
908 CIF_C_PROC_CTR_ENABLE, id);
909 else
910 isp3_param_clear_bits(params_vdev, ISP3X_CPROC_CTRL,
911 CIF_C_PROC_CTR_ENABLE, id);
912 }
913
914 static void
isp_ie_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_ie_cfg * arg,u32 id)915 isp_ie_config(struct rkisp_isp_params_vdev *params_vdev,
916 const struct isp2x_ie_cfg *arg, u32 id)
917 {
918 u32 eff_ctrl;
919
920 eff_ctrl = isp3_param_read(params_vdev, ISP3X_IMG_EFF_CTRL, id);
921 eff_ctrl &= ~CIF_IMG_EFF_CTRL_MODE_MASK;
922
923 if (params_vdev->quantization == V4L2_QUANTIZATION_FULL_RANGE)
924 eff_ctrl |= CIF_IMG_EFF_CTRL_YCBCR_FULL;
925
926 switch (arg->effect) {
927 case V4L2_COLORFX_SEPIA:
928 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SEPIA;
929 break;
930 case V4L2_COLORFX_SET_CBCR:
931 isp3_param_write(params_vdev, arg->eff_tint, ISP3X_IMG_EFF_TINT, id);
932 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SEPIA;
933 break;
934 /*
935 * Color selection is similar to water color(AQUA):
936 * grayscale + selected color w threshold
937 */
938 case V4L2_COLORFX_AQUA:
939 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_COLOR_SEL;
940 isp3_param_write(params_vdev, arg->color_sel,
941 ISP3X_IMG_EFF_COLOR_SEL, id);
942 break;
943 case V4L2_COLORFX_EMBOSS:
944 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_EMBOSS;
945 isp3_param_write(params_vdev, arg->eff_mat_1,
946 CIF_IMG_EFF_MAT_1, id);
947 isp3_param_write(params_vdev, arg->eff_mat_2,
948 CIF_IMG_EFF_MAT_2, id);
949 isp3_param_write(params_vdev, arg->eff_mat_3,
950 CIF_IMG_EFF_MAT_3, id);
951 break;
952 case V4L2_COLORFX_SKETCH:
953 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SKETCH;
954 isp3_param_write(params_vdev, arg->eff_mat_3,
955 CIF_IMG_EFF_MAT_3, id);
956 isp3_param_write(params_vdev, arg->eff_mat_4,
957 CIF_IMG_EFF_MAT_4, id);
958 isp3_param_write(params_vdev, arg->eff_mat_5,
959 CIF_IMG_EFF_MAT_5, id);
960 break;
961 case V4L2_COLORFX_BW:
962 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_BLACKWHITE;
963 break;
964 case V4L2_COLORFX_NEGATIVE:
965 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_NEGATIVE;
966 break;
967 default:
968 break;
969 }
970
971 isp3_param_write(params_vdev, eff_ctrl, ISP3X_IMG_EFF_CTRL, id);
972 }
973
974 static void
isp_ie_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)975 isp_ie_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
976 {
977 if (en) {
978 isp3_param_set_bits(params_vdev, ISP3X_IMG_EFF_CTRL,
979 CIF_IMG_EFF_CTRL_CFG_UPD |
980 CIF_IMG_EFF_CTRL_ENABLE, id);
981 } else {
982 isp3_param_clear_bits(params_vdev, ISP3X_IMG_EFF_CTRL,
983 CIF_IMG_EFF_CTRL_ENABLE, id);
984 }
985 }
986
987 static void
isp_rawaebig_config_foraf(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_rawaf_meas_cfg * arg,u32 id)988 isp_rawaebig_config_foraf(struct rkisp_isp_params_vdev *params_vdev,
989 const struct isp3x_rawaf_meas_cfg *arg, u32 id)
990 {
991 u32 block_hsize, block_vsize;
992 u32 addr, value;
993 u32 wnd_num_idx = 2;
994 const u32 ae_wnd_num[] = {
995 1, 5, 15, 15
996 };
997
998 addr = ISP3X_RAWAE_BIG1_BASE;
999 value = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL, id);
1000 value &= ISP3X_RAWAE_BIG_EN;
1001
1002 value |= ISP3X_RAWAE_BIG_WND0_NUM(wnd_num_idx);
1003 isp3_param_write(params_vdev, value, addr + ISP3X_RAWAE_BIG_CTRL, id);
1004
1005 isp3_param_write(params_vdev,
1006 ISP_PACK_2SHORT(arg->win[0].h_offs, arg->win[0].v_offs),
1007 addr + ISP3X_RAWAE_BIG_OFFSET, id);
1008
1009 block_hsize = arg->win[0].h_size / ae_wnd_num[wnd_num_idx];
1010 block_vsize = arg->win[0].v_size / ae_wnd_num[wnd_num_idx];
1011 isp3_param_write(params_vdev,
1012 ISP_PACK_2SHORT(block_hsize, block_vsize),
1013 addr + ISP3X_RAWAE_BIG_BLK_SIZE, id);
1014 }
1015
1016 static void
isp_rawaf_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_rawaf_meas_cfg * arg,u32 id)1017 isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev,
1018 const struct isp3x_rawaf_meas_cfg *arg, u32 id)
1019 {
1020 u32 i, var, ctrl;
1021 u16 h_size, v_size;
1022 u16 h_offs, v_offs;
1023 u8 gaus_en, viir_en, v1_fir_sel;
1024 size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->win),
1025 arg->num_afm_win);
1026
1027 /* To config must be off, store the current status firstly */
1028 ctrl = isp3_param_read(params_vdev, ISP3X_RAWAF_CTRL, id);
1029 if (ctrl & ISP3X_RAWAF_EN) {
1030 var = ctrl;
1031 var &= ~ISP3X_REG_WR_MASK;
1032 var &= ~ISP3X_RAWAF_EN;
1033 isp3_param_write(params_vdev, var, ISP3X_RAWAF_CTRL, id);
1034 }
1035
1036 for (i = 0; i < num_of_win; i++) {
1037 h_size = arg->win[i].h_size;
1038 v_size = arg->win[i].v_size;
1039 h_offs = arg->win[i].h_offs < 2 ? 2 : arg->win[i].h_offs;
1040 v_offs = arg->win[i].v_offs < 1 ? 1 : arg->win[i].v_offs;
1041
1042 if (i == 0) {
1043 h_size = h_size / 15 * 15;
1044 v_size = v_size / 15 * 15;
1045 }
1046
1047 /*
1048 * (horizontal left row), value must be greater or equal 2
1049 * (vertical top line), value must be greater or equal 1
1050 */
1051 isp3_param_write(params_vdev,
1052 ISP_PACK_2SHORT(v_offs, h_offs),
1053 ISP3X_RAWAF_OFFSET_WINA + i * 8, id);
1054
1055 /*
1056 * value must be smaller than [width of picture -2]
1057 * value must be lower than (number of lines -2)
1058 */
1059 isp3_param_write(params_vdev,
1060 ISP_PACK_2SHORT(v_size, h_size),
1061 ISP3X_RAWAF_SIZE_WINA + i * 8, id);
1062 }
1063
1064 var = isp3_param_read(params_vdev, ISP3X_RAWAF_THRES, id);
1065 var &= ~0xFFFF;
1066 var |= arg->afm_thres;
1067 isp3_param_write(params_vdev, var, ISP3X_RAWAF_THRES, id);
1068
1069 var = (arg->lum_var_shift[1] & 0x7) << 20 | (arg->lum_var_shift[0] & 0x7) << 16 |
1070 (arg->afm_var_shift[1] & 0x7) << 4 | (arg->afm_var_shift[0] & 0x7);
1071 isp3_param_write(params_vdev, var, ISP3X_RAWAF_VAR_SHIFT, id);
1072
1073 for (i = 0; i < ISP3X_RAWAF_GAMMA_NUM / 2; i++) {
1074 var = ISP_PACK_2SHORT(arg->gamma_y[2 * i], arg->gamma_y[2 * i + 1]);
1075 isp3_param_write(params_vdev, var, ISP3X_RAWAF_GAMMA_Y0 + i * 4, id);
1076 }
1077 var = ISP_PACK_2SHORT(arg->gamma_y[16], 0);
1078 isp3_param_write(params_vdev, var, ISP3X_RAWAF_GAMMA_Y8, id);
1079
1080 var = (arg->v2iir_var_shift & 0x7) << 12 | (arg->v1iir_var_shift & 0x7) << 8 |
1081 (arg->h2iir_var_shift & 0x7) << 4 | (arg->h1iir_var_shift & 0x7);
1082 isp3_param_write(params_vdev, var, ISP3X_RAWAF_HVIIR_VAR_SHIFT, id);
1083
1084 var = ISP_PACK_2SHORT(arg->h_fv_thresh, arg->v_fv_thresh);
1085 isp3_param_write(params_vdev, var, ISP3X_RAWAF_HIIR_THRESH, id);
1086
1087 for (i = 0; i < ISP3X_RAWAF_VFIR_COE_NUM; i++) {
1088 var = ISP_PACK_2SHORT(arg->v1fir_coe[i], arg->v2fir_coe[i]);
1089 isp3_param_write(params_vdev, var, ISP3X_RAWAF_V_FIR_COE0 + i * 4, id);
1090 }
1091
1092 isp3_param_write(params_vdev, arg->highlit_thresh, ISP3X_RAWAF_HIGHLIT_THRESH, id);
1093
1094 viir_en = arg->viir_en;
1095 gaus_en = arg->gaus_en;
1096 v1_fir_sel = arg->v1_fir_sel;
1097 if (gaus_en == 0)
1098 viir_en = 0;
1099 if (viir_en == 0)
1100 v1_fir_sel = 0;
1101
1102 ctrl &= ISP3X_RAWAF_EN;
1103 if (arg->hiir_en) {
1104 ctrl |= ISP3X_RAWAF_HIIR_EN;
1105 for (i = 0; i < ISP3X_RAWAF_HIIR_COE_NUM / 2; i++) {
1106 var = ISP_PACK_2SHORT(arg->h1iir1_coe[i * 2], arg->h1iir1_coe[i * 2 + 1]);
1107 isp3_param_write(params_vdev, var, ISP3X_RAWAF_H1_IIR1_COE01 + i * 4, id);
1108 var = ISP_PACK_2SHORT(arg->h1iir2_coe[i * 2], arg->h1iir2_coe[i * 2 + 1]);
1109 isp3_param_write(params_vdev, var, ISP3X_RAWAF_H1_IIR2_COE01 + i * 4, id);
1110 var = ISP_PACK_2SHORT(arg->h2iir1_coe[i * 2], arg->h2iir1_coe[i * 2 + 1]);
1111 isp3_param_write(params_vdev, var, ISP3X_RAWAF_H2_IIR1_COE01 + i * 4, id);
1112 var = ISP_PACK_2SHORT(arg->h2iir2_coe[i * 2], arg->h2iir2_coe[i * 2 + 1]);
1113 isp3_param_write(params_vdev, var, ISP3X_RAWAF_H2_IIR2_COE01 + i * 4, id);
1114 }
1115 }
1116 if (viir_en) {
1117 ctrl |= ISP3X_RAWAF_VIIR_EN;
1118 for (i = 0; i < ISP3X_RAWAF_V2IIR_COE_NUM; i++) {
1119 var = ISP_PACK_2SHORT(arg->v1iir_coe[i], arg->v2iir_coe[i]);
1120 isp3_param_write(params_vdev, var, ISP3X_RAWAF_V_IIR_COE0 + i * 4, id);
1121 }
1122 for (; i < ISP3X_RAWAF_V1IIR_COE_NUM; i++) {
1123 var = ISP_PACK_2SHORT(arg->v1iir_coe[i], 0);
1124 isp3_param_write(params_vdev, var, ISP3X_RAWAF_V_IIR_COE0 + i * 4, id);
1125 }
1126 }
1127 if (arg->ldg_en) {
1128 ctrl |= ISP3X_RAWAF_LDG_EN;
1129 for (i = 0; i < ISP3X_RAWAF_CURVE_NUM; i++) {
1130 isp3_param_write(params_vdev,
1131 arg->curve_h[i].ldg_lumth |
1132 arg->curve_h[i].ldg_gain << 8 |
1133 arg->curve_h[i].ldg_gslp << 16,
1134 ISP3X_RAWAF_H_CURVEL + i * 16, id);
1135 isp3_param_write(params_vdev,
1136 arg->curve_v[i].ldg_lumth |
1137 arg->curve_v[i].ldg_gain << 8 |
1138 arg->curve_v[i].ldg_gslp << 16,
1139 ISP3X_RAWAF_V_CURVEL + i * 16, id);
1140 }
1141 }
1142
1143 ctrl |= (arg->y_mode & 0x1) << 13 |
1144 (arg->ae_mode & 0x1) << 12 |
1145 (arg->v2_fv_mode & 0x1) << 11 |
1146 (arg->v1_fv_mode & 0x1) << 10 |
1147 (arg->h2_fv_mode & 0x1) << 9 |
1148 (arg->h1_fv_mode & 0x1) << 8 |
1149 (arg->accu_8bit_mode & 0x1) << 6 |
1150 (v1_fir_sel & 0x1) << 3 |
1151 (gaus_en & 0x1) << 2 |
1152 (arg->gamma_en & 0x1) << 1;
1153 isp3_param_write(params_vdev, ctrl, ISP3X_RAWAF_CTRL, id);
1154
1155 ctrl = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH, id);
1156 ctrl &= ~(ISP3X_RAWAF_SEL(3));
1157 ctrl |= ISP3X_RAWAF_SEL(arg->rawaf_sel);
1158 isp3_param_write(params_vdev, ctrl, ISP3X_VI_ISP_PATH, id);
1159
1160 params_vdev->afaemode_en = arg->ae_mode;
1161 if (params_vdev->afaemode_en)
1162 isp_rawaebig_config_foraf(params_vdev, arg, id);
1163 }
1164
1165 static void
isp_rawaebig_enable_foraf(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)1166 isp_rawaebig_enable_foraf(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
1167 {
1168 u32 exp_ctrl;
1169 u32 addr = ISP3X_RAWAE_BIG1_BASE;
1170
1171 exp_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL, id);
1172 exp_ctrl &= ~ISP3X_REG_WR_MASK;
1173 if (en)
1174 exp_ctrl |= ISP3X_MODULE_EN;
1175 else
1176 exp_ctrl &= ~ISP3X_MODULE_EN;
1177
1178 isp3_param_write(params_vdev, exp_ctrl, addr + ISP3X_RAWAE_BIG_CTRL, id);
1179 }
1180
1181 static void
isp_rawaf_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)1182 isp_rawaf_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
1183 {
1184 u32 afm_ctrl = isp3_param_read(params_vdev, ISP3X_RAWAF_CTRL, id);
1185
1186 afm_ctrl &= ~ISP3X_REG_WR_MASK;
1187 if (en)
1188 afm_ctrl |= ISP3X_RAWAF_EN;
1189 else
1190 afm_ctrl &= ~ISP3X_RAWAF_EN;
1191
1192 isp3_param_write(params_vdev, afm_ctrl, ISP3X_RAWAF_CTRL, id);
1193 if (params_vdev->afaemode_en) {
1194 isp_rawaebig_enable_foraf(params_vdev, en, id);
1195 if (!en)
1196 params_vdev->afaemode_en = false;
1197 }
1198 }
1199
1200 static void
isp_rawaelite_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaelite_meas_cfg * arg,u32 id)1201 isp_rawaelite_config(struct rkisp_isp_params_vdev *params_vdev,
1202 const struct isp2x_rawaelite_meas_cfg *arg, u32 id)
1203 {
1204 struct rkisp_device *ispdev = params_vdev->dev;
1205 struct v4l2_rect *out_crop = &ispdev->isp_sdev.out_crop;
1206 u32 width = out_crop->width;
1207 u32 block_hsize, block_vsize, value;
1208 u32 wnd_num_idx = 0;
1209 const u32 ae_wnd_num[] = {1, 5};
1210
1211 value = isp3_param_read(params_vdev, ISP3X_RAWAE_LITE_CTRL, id);
1212 value &= ~(ISP3X_RAWAE_LITE_WNDNUM);
1213 if (arg->wnd_num) {
1214 value |= ISP3X_RAWAE_LITE_WNDNUM;
1215 wnd_num_idx = 1;
1216 }
1217 value &= ~ISP3X_REG_WR_MASK;
1218 isp3_param_write(params_vdev, value, ISP3X_RAWAE_LITE_CTRL, id);
1219
1220 isp3_param_write(params_vdev,
1221 ISP_PACK_2SHORT(arg->win.h_offs, arg->win.v_offs),
1222 ISP3X_RAWAE_LITE_OFFSET, id);
1223
1224 block_hsize = arg->win.h_size / ae_wnd_num[wnd_num_idx];
1225 value = block_hsize * ae_wnd_num[wnd_num_idx] + arg->win.h_offs;
1226 if (ispdev->hw_dev->is_unite)
1227 width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
1228 if (value + 1 > width)
1229 block_hsize -= 1;
1230 block_vsize = arg->win.v_size / ae_wnd_num[wnd_num_idx];
1231 value = block_vsize * ae_wnd_num[wnd_num_idx] + arg->win.v_offs;
1232 if (value + 2 > out_crop->height)
1233 block_vsize -= 1;
1234 if (block_vsize % 2)
1235 block_vsize -= 1;
1236 isp3_param_write(params_vdev,
1237 ISP_PACK_2SHORT(block_hsize, block_vsize),
1238 ISP3X_RAWAE_LITE_BLK_SIZ, id);
1239
1240 value = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH, id);
1241 value &= ~(ISP3X_RAWAE012_SEL(3));
1242 value |= ISP3X_RAWAE012_SEL(arg->rawae_sel);
1243 isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH, id);
1244 }
1245
1246 static void
isp_rawaelite_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)1247 isp_rawaelite_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
1248 {
1249 u32 exp_ctrl;
1250
1251 exp_ctrl = isp3_param_read(params_vdev, ISP3X_RAWAE_LITE_CTRL, id);
1252 exp_ctrl &= ~ISP3X_REG_WR_MASK;
1253 if (en)
1254 exp_ctrl |= ISP3X_RAWAE_LITE_EN;
1255 else
1256 exp_ctrl &= ~ISP3X_RAWAE_LITE_EN;
1257
1258 isp3_param_write(params_vdev, exp_ctrl, ISP3X_RAWAE_LITE_CTRL, id);
1259 }
1260
1261 static void
isp_rawaebig_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaebig_meas_cfg * arg,u32 blk_no,u32 id)1262 isp_rawaebig_config(struct rkisp_isp_params_vdev *params_vdev,
1263 const struct isp2x_rawaebig_meas_cfg *arg,
1264 u32 blk_no, u32 id)
1265 {
1266 struct rkisp_device *ispdev = params_vdev->dev;
1267 struct v4l2_rect *out_crop = &ispdev->isp_sdev.out_crop;
1268 u32 width = out_crop->width;
1269 u32 block_hsize, block_vsize;
1270 u32 addr, i, value, h_size, v_size;
1271 u32 wnd_num_idx = 0;
1272 const u32 ae_wnd_num[] = {
1273 1, 5, 15, 15
1274 };
1275
1276 switch (blk_no) {
1277 case 1:
1278 addr = ISP3X_RAWAE_BIG2_BASE;
1279 break;
1280 case 2:
1281 addr = ISP3X_RAWAE_BIG3_BASE;
1282 break;
1283 case 0:
1284 default:
1285 addr = ISP3X_RAWAE_BIG1_BASE;
1286 break;
1287 }
1288
1289 /* avoid to override the old enable value */
1290 value = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL, id);
1291 value &= ISP3X_RAWAE_BIG_EN;
1292
1293 wnd_num_idx = arg->wnd_num;
1294 value |= ISP3X_RAWAE_BIG_WND0_NUM(wnd_num_idx);
1295
1296 if (arg->subwin_en[0])
1297 value |= ISP3X_RAWAE_BIG_WND1_EN;
1298 if (arg->subwin_en[1])
1299 value |= ISP3X_RAWAE_BIG_WND2_EN;
1300 if (arg->subwin_en[2])
1301 value |= ISP3X_RAWAE_BIG_WND3_EN;
1302 if (arg->subwin_en[3])
1303 value |= ISP3X_RAWAE_BIG_WND4_EN;
1304
1305 isp3_param_write(params_vdev, value, addr + ISP3X_RAWAE_BIG_CTRL, id);
1306
1307 isp3_param_write(params_vdev,
1308 ISP_PACK_2SHORT(arg->win.h_offs, arg->win.v_offs),
1309 addr + ISP3X_RAWAE_BIG_OFFSET, id);
1310
1311 block_hsize = arg->win.h_size / ae_wnd_num[wnd_num_idx];
1312 value = block_hsize * ae_wnd_num[wnd_num_idx] + arg->win.h_offs;
1313 if (ispdev->hw_dev->is_unite)
1314 width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
1315 if (value + 1 > width)
1316 block_hsize -= 1;
1317 block_vsize = arg->win.v_size / ae_wnd_num[wnd_num_idx];
1318 value = block_vsize * ae_wnd_num[wnd_num_idx] + arg->win.v_offs;
1319 if (value + 2 > out_crop->height)
1320 block_vsize -= 1;
1321 if (block_vsize % 2)
1322 block_vsize -= 1;
1323 isp3_param_write(params_vdev,
1324 ISP_PACK_2SHORT(block_hsize, block_vsize),
1325 addr + ISP3X_RAWAE_BIG_BLK_SIZE, id);
1326
1327 for (i = 0; i < ISP3X_RAWAEBIG_SUBWIN_NUM; i++) {
1328 isp3_param_write(params_vdev,
1329 ISP_PACK_2SHORT(arg->subwin[i].h_offs, arg->subwin[i].v_offs),
1330 addr + ISP3X_RAWAE_BIG_WND1_OFFSET + 8 * i, id);
1331
1332 v_size = arg->subwin[i].v_size + arg->subwin[i].v_offs;
1333 h_size = arg->subwin[i].h_size + arg->subwin[i].h_offs;
1334 isp3_param_write(params_vdev,
1335 ISP_PACK_2SHORT(h_size, v_size),
1336 addr + ISP3X_RAWAE_BIG_WND1_SIZE + 8 * i, id);
1337 }
1338
1339 if (blk_no == 0) {
1340 value = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH, id);
1341 value &= ~(ISP3X_RAWAE3_SEL(3));
1342 value |= ISP3X_RAWAE3_SEL(arg->rawae_sel);
1343 isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH, id);
1344 } else {
1345 value = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH, id);
1346 value &= ~(ISP3X_RAWAE012_SEL(3));
1347 value |= ISP3X_RAWAE012_SEL(arg->rawae_sel);
1348 isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH, id);
1349 }
1350 }
1351
1352 static void
isp_rawaebig_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 blk_no,u32 id)1353 isp_rawaebig_enable(struct rkisp_isp_params_vdev *params_vdev,
1354 bool en, u32 blk_no, u32 id)
1355 {
1356 u32 exp_ctrl;
1357 u32 addr;
1358
1359 switch (blk_no) {
1360 case 1:
1361 addr = ISP3X_RAWAE_BIG2_BASE;
1362 break;
1363 case 2:
1364 addr = ISP3X_RAWAE_BIG3_BASE;
1365 break;
1366 case 0:
1367 default:
1368 addr = ISP3X_RAWAE_BIG1_BASE;
1369 break;
1370 }
1371
1372 exp_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL, id);
1373 exp_ctrl &= ~ISP3X_REG_WR_MASK;
1374 if (en)
1375 exp_ctrl |= ISP3X_MODULE_EN;
1376 else
1377 exp_ctrl &= ~ISP3X_MODULE_EN;
1378
1379 isp3_param_write(params_vdev, exp_ctrl, addr + ISP3X_RAWAE_BIG_CTRL, id);
1380 }
1381
1382 static void
isp_rawae1_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaebig_meas_cfg * arg,u32 id)1383 isp_rawae1_config(struct rkisp_isp_params_vdev *params_vdev,
1384 const struct isp2x_rawaebig_meas_cfg *arg, u32 id)
1385 {
1386 isp_rawaebig_config(params_vdev, arg, 1, id);
1387 }
1388
1389 static void
isp_rawae1_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)1390 isp_rawae1_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
1391 {
1392 isp_rawaebig_enable(params_vdev, en, 1, id);
1393 }
1394
1395 static void
isp_rawae2_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaebig_meas_cfg * arg,u32 id)1396 isp_rawae2_config(struct rkisp_isp_params_vdev *params_vdev,
1397 const struct isp2x_rawaebig_meas_cfg *arg, u32 id)
1398 {
1399 isp_rawaebig_config(params_vdev, arg, 2, id);
1400 }
1401
1402 static void
isp_rawae2_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)1403 isp_rawae2_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
1404 {
1405 isp_rawaebig_enable(params_vdev, en, 2, id);
1406 }
1407
1408 static void
isp_rawae3_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaebig_meas_cfg * arg,u32 id)1409 isp_rawae3_config(struct rkisp_isp_params_vdev *params_vdev,
1410 const struct isp2x_rawaebig_meas_cfg *arg, u32 id)
1411 {
1412 isp_rawaebig_config(params_vdev, arg, 0, id);
1413 }
1414
1415 static void
isp_rawae3_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)1416 isp_rawae3_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
1417 {
1418 isp_rawaebig_enable(params_vdev, en, 0, id);
1419 }
1420
1421 static void
isp_rawawb_cfg_sram(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_rawawb_meas_cfg * arg,bool is_check,u32 id)1422 isp_rawawb_cfg_sram(struct rkisp_isp_params_vdev *params_vdev,
1423 const struct isp3x_rawawb_meas_cfg *arg,
1424 bool is_check, u32 id)
1425 {
1426 u32 i, val = ISP3X_MODULE_EN;
1427
1428 if (is_check &&
1429 !(isp3_param_read(params_vdev, ISP3X_RAWAWB_CTRL, id) & val))
1430 return;
1431
1432 for (i = 0; i < ISP3X_RAWAWB_WEIGHT_NUM / 5; i++) {
1433 isp3_param_write(params_vdev,
1434 (arg->sw_rawawb_wp_blk_wei_w[5 * i] & 0x3f) << 0 |
1435 (arg->sw_rawawb_wp_blk_wei_w[5 * i + 1] & 0x3f) << 6 |
1436 (arg->sw_rawawb_wp_blk_wei_w[5 * i + 2] & 0x3f) << 12 |
1437 (arg->sw_rawawb_wp_blk_wei_w[5 * i + 3] & 0x3f) << 18 |
1438 (arg->sw_rawawb_wp_blk_wei_w[5 * i + 4] & 0x3f) << 24,
1439 ISP3X_RAWAWB_WRAM_DATA_BASE, id);
1440 }
1441 }
1442
1443 static void
isp_rawawb_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_rawawb_meas_cfg * arg,u32 id)1444 isp_rawawb_config(struct rkisp_isp_params_vdev *params_vdev,
1445 const struct isp3x_rawawb_meas_cfg *arg, u32 id)
1446 {
1447 struct isp3x_isp_params_cfg *params_rec = params_vdev->isp3x_params + id;
1448 struct isp3x_rawawb_meas_cfg *arg_rec = ¶ms_rec->meas.rawawb;
1449 u32 value;
1450
1451 isp3_param_write(params_vdev,
1452 (arg->sw_rawawb_blk_measure_enable & 0x1) |
1453 (arg->sw_rawawb_blk_measure_mode & 0x1) << 1 |
1454 (arg->sw_rawawb_blk_measure_xytype & 0x1) << 2 |
1455 (arg->sw_rawawb_blk_rtdw_measure_en & 0x1) << 3 |
1456 (arg->sw_rawawb_blk_measure_illu_idx & 0x7) << 4 |
1457 (arg->sw_rawawb_blk_with_luma_wei_en & 0x1) << 8,
1458 ISP3X_RAWAWB_BLK_CTRL, id);
1459
1460 isp3_param_write(params_vdev,
1461 ISP_PACK_2SHORT(arg->sw_rawawb_h_offs, arg->sw_rawawb_v_offs),
1462 ISP3X_RAWAWB_WIN_OFFS, id);
1463
1464 isp3_param_write(params_vdev,
1465 ISP_PACK_2SHORT(arg->sw_rawawb_h_size, arg->sw_rawawb_v_size),
1466 ISP3X_RAWAWB_WIN_SIZE, id);
1467
1468 isp3_param_write(params_vdev,
1469 ISP_PACK_2SHORT(arg->sw_rawawb_r_max, arg->sw_rawawb_g_max),
1470 ISP3X_RAWAWB_LIMIT_RG_MAX, id);
1471
1472 isp3_param_write(params_vdev,
1473 ISP_PACK_2SHORT(arg->sw_rawawb_b_max, arg->sw_rawawb_y_max),
1474 ISP3X_RAWAWB_LIMIT_BY_MAX, id);
1475
1476 isp3_param_write(params_vdev,
1477 ISP_PACK_2SHORT(arg->sw_rawawb_r_min, arg->sw_rawawb_g_min),
1478 ISP3X_RAWAWB_LIMIT_RG_MIN, id);
1479
1480 isp3_param_write(params_vdev,
1481 ISP_PACK_2SHORT(arg->sw_rawawb_b_min, arg->sw_rawawb_y_min),
1482 ISP3X_RAWAWB_LIMIT_BY_MIN, id);
1483
1484 isp3_param_write(params_vdev,
1485 (arg->sw_rawawb_wp_luma_wei_en0 & 0x1) |
1486 (arg->sw_rawawb_wp_luma_wei_en1 & 0x1) << 1 |
1487 (arg->sw_rawawb_wp_blk_wei_en0 & 0x1) << 2 |
1488 (arg->sw_rawawb_wp_blk_wei_en1 & 0x1) << 3 |
1489 (arg->sw_rawawb_wp_hist_xytype & 0x1) << 4,
1490 ISP3X_RAWAWB_WEIGHT_CURVE_CTRL, id);
1491
1492 isp3_param_write(params_vdev,
1493 ISP_PACK_4BYTE(arg->sw_rawawb_wp_luma_weicurve_y0,
1494 arg->sw_rawawb_wp_luma_weicurve_y1,
1495 arg->sw_rawawb_wp_luma_weicurve_y2,
1496 arg->sw_rawawb_wp_luma_weicurve_y3),
1497 ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR03, id);
1498
1499 isp3_param_write(params_vdev,
1500 ISP_PACK_4BYTE(arg->sw_rawawb_wp_luma_weicurve_y4,
1501 arg->sw_rawawb_wp_luma_weicurve_y5,
1502 arg->sw_rawawb_wp_luma_weicurve_y6,
1503 arg->sw_rawawb_wp_luma_weicurve_y7),
1504 ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR47, id);
1505
1506 isp3_param_write(params_vdev,
1507 arg->sw_rawawb_wp_luma_weicurve_y8,
1508 ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR8, id);
1509
1510 isp3_param_write(params_vdev,
1511 ISP_PACK_4BYTE(arg->sw_rawawb_wp_luma_weicurve_w0,
1512 arg->sw_rawawb_wp_luma_weicurve_w1,
1513 arg->sw_rawawb_wp_luma_weicurve_w2,
1514 arg->sw_rawawb_wp_luma_weicurve_w3),
1515 ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR03, id);
1516
1517 isp3_param_write(params_vdev,
1518 ISP_PACK_4BYTE(arg->sw_rawawb_wp_luma_weicurve_w4,
1519 arg->sw_rawawb_wp_luma_weicurve_w5,
1520 arg->sw_rawawb_wp_luma_weicurve_w6,
1521 arg->sw_rawawb_wp_luma_weicurve_w7),
1522 ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR47, id);
1523
1524 isp3_param_write(params_vdev,
1525 ISP_PACK_2SHORT(arg->sw_rawawb_wp_luma_weicurve_w8,
1526 arg->sw_rawawb_pre_wbgain_inv_r),
1527 ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR8, id);
1528
1529 isp3_param_write(params_vdev,
1530 ISP_PACK_2SHORT(arg->sw_rawawb_pre_wbgain_inv_g,
1531 arg->sw_rawawb_pre_wbgain_inv_b),
1532 ISP3X_RAWAWB_PRE_WBGAIN_INV, id);
1533
1534 isp3_param_write(params_vdev,
1535 ISP_PACK_2SHORT(arg->sw_rawawb_vertex0_u_0,
1536 arg->sw_rawawb_vertex0_v_0),
1537 ISP3X_RAWAWB_UV_DETC_VERTEX0_0, id);
1538
1539 isp3_param_write(params_vdev,
1540 ISP_PACK_2SHORT(arg->sw_rawawb_vertex1_u_0,
1541 arg->sw_rawawb_vertex1_v_0),
1542 ISP3X_RAWAWB_UV_DETC_VERTEX1_0, id);
1543
1544 isp3_param_write(params_vdev,
1545 ISP_PACK_2SHORT(arg->sw_rawawb_vertex2_u_0,
1546 arg->sw_rawawb_vertex2_v_0),
1547 ISP3X_RAWAWB_UV_DETC_VERTEX2_0, id);
1548
1549 isp3_param_write(params_vdev,
1550 ISP_PACK_2SHORT(arg->sw_rawawb_vertex3_u_0,
1551 arg->sw_rawawb_vertex3_v_0),
1552 ISP3X_RAWAWB_UV_DETC_VERTEX3_0, id);
1553
1554 isp3_param_write(params_vdev,
1555 arg->sw_rawawb_islope01_0,
1556 ISP3X_RAWAWB_UV_DETC_ISLOPE01_0, id);
1557
1558 isp3_param_write(params_vdev,
1559 arg->sw_rawawb_islope12_0,
1560 ISP3X_RAWAWB_UV_DETC_ISLOPE12_0, id);
1561
1562 isp3_param_write(params_vdev,
1563 arg->sw_rawawb_islope23_0,
1564 ISP3X_RAWAWB_UV_DETC_ISLOPE23_0, id);
1565
1566 isp3_param_write(params_vdev,
1567 arg->sw_rawawb_islope30_0,
1568 ISP3X_RAWAWB_UV_DETC_ISLOPE30_0, id);
1569
1570 isp3_param_write(params_vdev,
1571 ISP_PACK_2SHORT(arg->sw_rawawb_vertex0_u_1,
1572 arg->sw_rawawb_vertex0_v_1),
1573 ISP3X_RAWAWB_UV_DETC_VERTEX0_1, id);
1574
1575 isp3_param_write(params_vdev,
1576 ISP_PACK_2SHORT(arg->sw_rawawb_vertex1_u_1,
1577 arg->sw_rawawb_vertex1_v_1),
1578 ISP3X_RAWAWB_UV_DETC_VERTEX1_1, id);
1579
1580 isp3_param_write(params_vdev,
1581 ISP_PACK_2SHORT(arg->sw_rawawb_vertex2_u_1,
1582 arg->sw_rawawb_vertex2_v_1),
1583 ISP3X_RAWAWB_UV_DETC_VERTEX2_1, id);
1584
1585 isp3_param_write(params_vdev,
1586 ISP_PACK_2SHORT(arg->sw_rawawb_vertex3_u_1,
1587 arg->sw_rawawb_vertex3_v_1),
1588 ISP3X_RAWAWB_UV_DETC_VERTEX3_1, id);
1589
1590 isp3_param_write(params_vdev,
1591 arg->sw_rawawb_islope01_1,
1592 ISP3X_RAWAWB_UV_DETC_ISLOPE01_1, id);
1593
1594 isp3_param_write(params_vdev,
1595 arg->sw_rawawb_islope12_1,
1596 ISP3X_RAWAWB_UV_DETC_ISLOPE12_1, id);
1597
1598 isp3_param_write(params_vdev,
1599 arg->sw_rawawb_islope23_1,
1600 ISP3X_RAWAWB_UV_DETC_ISLOPE23_1, id);
1601
1602 isp3_param_write(params_vdev,
1603 arg->sw_rawawb_islope30_1,
1604 ISP3X_RAWAWB_UV_DETC_ISLOPE30_1, id);
1605
1606 isp3_param_write(params_vdev,
1607 ISP_PACK_2SHORT(arg->sw_rawawb_vertex0_u_2,
1608 arg->sw_rawawb_vertex0_v_2),
1609 ISP3X_RAWAWB_UV_DETC_VERTEX0_2, id);
1610
1611 isp3_param_write(params_vdev,
1612 ISP_PACK_2SHORT(arg->sw_rawawb_vertex1_u_2,
1613 arg->sw_rawawb_vertex1_v_2),
1614 ISP3X_RAWAWB_UV_DETC_VERTEX1_2, id);
1615
1616 isp3_param_write(params_vdev,
1617 ISP_PACK_2SHORT(arg->sw_rawawb_vertex2_u_2,
1618 arg->sw_rawawb_vertex2_v_2),
1619 ISP3X_RAWAWB_UV_DETC_VERTEX2_2, id);
1620
1621 isp3_param_write(params_vdev,
1622 ISP_PACK_2SHORT(arg->sw_rawawb_vertex3_u_2,
1623 arg->sw_rawawb_vertex3_v_2),
1624 ISP3X_RAWAWB_UV_DETC_VERTEX3_2, id);
1625
1626 isp3_param_write(params_vdev,
1627 arg->sw_rawawb_islope01_2,
1628 ISP3X_RAWAWB_UV_DETC_ISLOPE01_2, id);
1629
1630 isp3_param_write(params_vdev,
1631 arg->sw_rawawb_islope12_2,
1632 ISP3X_RAWAWB_UV_DETC_ISLOPE12_2, id);
1633
1634 isp3_param_write(params_vdev,
1635 arg->sw_rawawb_islope23_2,
1636 ISP3X_RAWAWB_UV_DETC_ISLOPE23_2, id);
1637
1638 isp3_param_write(params_vdev,
1639 arg->sw_rawawb_islope30_2,
1640 ISP3X_RAWAWB_UV_DETC_ISLOPE30_2, id);
1641
1642 isp3_param_write(params_vdev,
1643 ISP_PACK_2SHORT(arg->sw_rawawb_vertex0_u_3,
1644 arg->sw_rawawb_vertex0_v_3),
1645 ISP3X_RAWAWB_UV_DETC_VERTEX0_3, id);
1646
1647 isp3_param_write(params_vdev,
1648 ISP_PACK_2SHORT(arg->sw_rawawb_vertex1_u_3,
1649 arg->sw_rawawb_vertex1_v_3),
1650 ISP3X_RAWAWB_UV_DETC_VERTEX1_3, id);
1651
1652 isp3_param_write(params_vdev,
1653 ISP_PACK_2SHORT(arg->sw_rawawb_vertex2_u_3,
1654 arg->sw_rawawb_vertex2_v_3),
1655 ISP3X_RAWAWB_UV_DETC_VERTEX2_3, id);
1656
1657 isp3_param_write(params_vdev,
1658 ISP_PACK_2SHORT(arg->sw_rawawb_vertex3_u_3,
1659 arg->sw_rawawb_vertex3_v_3),
1660 ISP3X_RAWAWB_UV_DETC_VERTEX3_3, id);
1661
1662 isp3_param_write(params_vdev,
1663 arg->sw_rawawb_islope01_3,
1664 ISP3X_RAWAWB_UV_DETC_ISLOPE01_3, id);
1665
1666 isp3_param_write(params_vdev,
1667 arg->sw_rawawb_islope12_3,
1668 ISP3X_RAWAWB_UV_DETC_ISLOPE12_3, id);
1669
1670 isp3_param_write(params_vdev,
1671 arg->sw_rawawb_islope23_3,
1672 ISP3X_RAWAWB_UV_DETC_ISLOPE23_3, id);
1673
1674 isp3_param_write(params_vdev,
1675 arg->sw_rawawb_islope30_3,
1676 ISP3X_RAWAWB_UV_DETC_ISLOPE30_3, id);
1677
1678 isp3_param_write(params_vdev,
1679 ISP_PACK_2SHORT(arg->sw_rawawb_vertex0_u_4,
1680 arg->sw_rawawb_vertex0_v_4),
1681 ISP3X_RAWAWB_UV_DETC_VERTEX0_4, id);
1682
1683 isp3_param_write(params_vdev,
1684 ISP_PACK_2SHORT(arg->sw_rawawb_vertex1_u_4,
1685 arg->sw_rawawb_vertex1_v_4),
1686 ISP3X_RAWAWB_UV_DETC_VERTEX1_4, id);
1687
1688 isp3_param_write(params_vdev,
1689 ISP_PACK_2SHORT(arg->sw_rawawb_vertex2_u_4,
1690 arg->sw_rawawb_vertex2_v_4),
1691 ISP3X_RAWAWB_UV_DETC_VERTEX2_4, id);
1692
1693 isp3_param_write(params_vdev,
1694 ISP_PACK_2SHORT(arg->sw_rawawb_vertex3_u_4,
1695 arg->sw_rawawb_vertex3_v_4),
1696 ISP3X_RAWAWB_UV_DETC_VERTEX3_4, id);
1697
1698 isp3_param_write(params_vdev,
1699 arg->sw_rawawb_islope01_4,
1700 ISP3X_RAWAWB_UV_DETC_ISLOPE01_4, id);
1701
1702 isp3_param_write(params_vdev,
1703 arg->sw_rawawb_islope12_4,
1704 ISP3X_RAWAWB_UV_DETC_ISLOPE12_4, id);
1705
1706 isp3_param_write(params_vdev,
1707 arg->sw_rawawb_islope23_4,
1708 ISP3X_RAWAWB_UV_DETC_ISLOPE23_4, id);
1709
1710 isp3_param_write(params_vdev,
1711 arg->sw_rawawb_islope30_4,
1712 ISP3X_RAWAWB_UV_DETC_ISLOPE30_4, id);
1713
1714 isp3_param_write(params_vdev,
1715 ISP_PACK_2SHORT(arg->sw_rawawb_vertex0_u_5,
1716 arg->sw_rawawb_vertex0_v_5),
1717 ISP3X_RAWAWB_UV_DETC_VERTEX0_5, id);
1718
1719 isp3_param_write(params_vdev,
1720 ISP_PACK_2SHORT(arg->sw_rawawb_vertex1_u_5,
1721 arg->sw_rawawb_vertex1_v_5),
1722 ISP3X_RAWAWB_UV_DETC_VERTEX1_5, id);
1723
1724 isp3_param_write(params_vdev,
1725 ISP_PACK_2SHORT(arg->sw_rawawb_vertex2_u_5,
1726 arg->sw_rawawb_vertex2_v_5),
1727 ISP3X_RAWAWB_UV_DETC_VERTEX2_5, id);
1728
1729 isp3_param_write(params_vdev,
1730 ISP_PACK_2SHORT(arg->sw_rawawb_vertex3_u_5,
1731 arg->sw_rawawb_vertex3_v_5),
1732 ISP3X_RAWAWB_UV_DETC_VERTEX3_5, id);
1733
1734 isp3_param_write(params_vdev,
1735 arg->sw_rawawb_islope01_5,
1736 ISP3X_RAWAWB_UV_DETC_ISLOPE01_5, id);
1737
1738 isp3_param_write(params_vdev,
1739 arg->sw_rawawb_islope12_5,
1740 ISP3X_RAWAWB_UV_DETC_ISLOPE10_5, id);
1741
1742 isp3_param_write(params_vdev,
1743 arg->sw_rawawb_islope23_5,
1744 ISP3X_RAWAWB_UV_DETC_ISLOPE23_5, id);
1745
1746 isp3_param_write(params_vdev,
1747 arg->sw_rawawb_islope30_5,
1748 ISP3X_RAWAWB_UV_DETC_ISLOPE30_5, id);
1749
1750 isp3_param_write(params_vdev,
1751 ISP_PACK_2SHORT(arg->sw_rawawb_vertex0_u_6,
1752 arg->sw_rawawb_vertex0_v_6),
1753 ISP3X_RAWAWB_UV_DETC_VERTEX0_6, id);
1754
1755 isp3_param_write(params_vdev,
1756 ISP_PACK_2SHORT(arg->sw_rawawb_vertex1_u_6,
1757 arg->sw_rawawb_vertex1_v_6),
1758 ISP3X_RAWAWB_UV_DETC_VERTEX1_6, id);
1759
1760 isp3_param_write(params_vdev,
1761 ISP_PACK_2SHORT(arg->sw_rawawb_vertex2_u_6,
1762 arg->sw_rawawb_vertex2_v_6),
1763 ISP3X_RAWAWB_UV_DETC_VERTEX2_6, id);
1764
1765 isp3_param_write(params_vdev,
1766 ISP_PACK_2SHORT(arg->sw_rawawb_vertex3_u_6,
1767 arg->sw_rawawb_vertex3_v_6),
1768 ISP3X_RAWAWB_UV_DETC_VERTEX3_6, id);
1769
1770 isp3_param_write(params_vdev,
1771 arg->sw_rawawb_islope01_6,
1772 ISP3X_RAWAWB_UV_DETC_ISLOPE01_6, id);
1773
1774 isp3_param_write(params_vdev,
1775 arg->sw_rawawb_islope12_6,
1776 ISP3X_RAWAWB_UV_DETC_ISLOPE10_6, id);
1777
1778 isp3_param_write(params_vdev,
1779 arg->sw_rawawb_islope23_6,
1780 ISP3X_RAWAWB_UV_DETC_ISLOPE23_6, id);
1781
1782 isp3_param_write(params_vdev,
1783 arg->sw_rawawb_islope30_6,
1784 ISP3X_RAWAWB_UV_DETC_ISLOPE30_6, id);
1785
1786 isp3_param_write(params_vdev,
1787 ISP_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat0_y,
1788 arg->sw_rawawb_rgb2ryuvmat1_y),
1789 ISP3X_RAWAWB_YUV_RGB2ROTY_0, id);
1790
1791 isp3_param_write(params_vdev,
1792 ISP_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat2_y,
1793 arg->sw_rawawb_rgb2ryuvofs_y),
1794 ISP3X_RAWAWB_YUV_RGB2ROTY_1, id);
1795
1796 isp3_param_write(params_vdev,
1797 ISP_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat0_u,
1798 arg->sw_rawawb_rgb2ryuvmat1_u),
1799 ISP3X_RAWAWB_YUV_RGB2ROTU_0, id);
1800
1801
1802 isp3_param_write(params_vdev,
1803 ISP_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat2_u,
1804 arg->sw_rawawb_rgb2ryuvofs_u),
1805 ISP3X_RAWAWB_YUV_RGB2ROTU_1, id);
1806
1807 isp3_param_write(params_vdev,
1808 ISP_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat0_v,
1809 arg->sw_rawawb_rgb2ryuvmat1_v),
1810 ISP3X_RAWAWB_YUV_RGB2ROTV_0, id);
1811
1812 isp3_param_write(params_vdev,
1813 ISP_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat2_v,
1814 arg->sw_rawawb_rgb2ryuvofs_v),
1815 ISP3X_RAWAWB_YUV_RGB2ROTV_1, id);
1816
1817 isp3_param_write(params_vdev,
1818 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls0_y,
1819 arg->sw_rawawb_vec_x21_ls0_y),
1820 ISP3X_RAWAWB_YUV_X_COOR_Y_0, id);
1821
1822 isp3_param_write(params_vdev,
1823 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls0_u,
1824 arg->sw_rawawb_vec_x21_ls0_u),
1825 ISP3X_RAWAWB_YUV_X_COOR_U_0, id);
1826
1827 isp3_param_write(params_vdev,
1828 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls0_v,
1829 arg->sw_rawawb_vec_x21_ls0_v),
1830 ISP3X_RAWAWB_YUV_X_COOR_V_0, id);
1831
1832 isp3_param_write(params_vdev,
1833 ISP_PACK_4BYTE(arg->sw_rawawb_dis_x1x2_ls0,
1834 0,
1835 arg->sw_rawawb_rotu0_ls0,
1836 arg->sw_rawawb_rotu1_ls0),
1837 ISP3X_RAWAWB_YUV_X1X2_DIS_0, id);
1838
1839 isp3_param_write(params_vdev,
1840 ISP_PACK_4BYTE(arg->sw_rawawb_rotu2_ls0,
1841 arg->sw_rawawb_rotu3_ls0,
1842 arg->sw_rawawb_rotu4_ls0,
1843 arg->sw_rawawb_rotu5_ls0),
1844 ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_0, id);
1845
1846 isp3_param_write(params_vdev,
1847 ISP_PACK_2SHORT(arg->sw_rawawb_th0_ls0,
1848 arg->sw_rawawb_th1_ls0),
1849 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_0, id);
1850
1851 isp3_param_write(params_vdev,
1852 ISP_PACK_2SHORT(arg->sw_rawawb_th2_ls0,
1853 arg->sw_rawawb_th3_ls0),
1854 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_0, id);
1855
1856 isp3_param_write(params_vdev,
1857 ISP_PACK_2SHORT(arg->sw_rawawb_th4_ls0,
1858 arg->sw_rawawb_th5_ls0),
1859 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_0, id);
1860
1861 isp3_param_write(params_vdev,
1862 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls1_y,
1863 arg->sw_rawawb_vec_x21_ls1_y),
1864 ISP3X_RAWAWB_YUV_X_COOR_Y_1, id);
1865
1866 isp3_param_write(params_vdev,
1867 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls1_u,
1868 arg->sw_rawawb_vec_x21_ls1_u),
1869 ISP3X_RAWAWB_YUV_X_COOR_U_1, id);
1870
1871 isp3_param_write(params_vdev,
1872 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls1_v,
1873 arg->sw_rawawb_vec_x21_ls1_v),
1874 ISP3X_RAWAWB_YUV_X_COOR_V_1, id);
1875
1876 isp3_param_write(params_vdev,
1877 ISP_PACK_4BYTE(arg->sw_rawawb_dis_x1x2_ls1,
1878 0,
1879 arg->sw_rawawb_rotu0_ls1,
1880 arg->sw_rawawb_rotu1_ls1),
1881 ISP3X_RAWAWB_YUV_X1X2_DIS_1, id);
1882
1883 isp3_param_write(params_vdev,
1884 ISP_PACK_4BYTE(arg->sw_rawawb_rotu2_ls1,
1885 arg->sw_rawawb_rotu3_ls1,
1886 arg->sw_rawawb_rotu4_ls1,
1887 arg->sw_rawawb_rotu5_ls1),
1888 ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_1, id);
1889
1890 isp3_param_write(params_vdev,
1891 ISP_PACK_2SHORT(arg->sw_rawawb_th0_ls1,
1892 arg->sw_rawawb_th1_ls1),
1893 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_1, id);
1894
1895 isp3_param_write(params_vdev,
1896 ISP_PACK_2SHORT(arg->sw_rawawb_th2_ls1,
1897 arg->sw_rawawb_th3_ls1),
1898 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_1, id);
1899
1900 isp3_param_write(params_vdev,
1901 ISP_PACK_2SHORT(arg->sw_rawawb_th4_ls1,
1902 arg->sw_rawawb_th5_ls1),
1903 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_1, id);
1904
1905 isp3_param_write(params_vdev,
1906 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls2_y,
1907 arg->sw_rawawb_vec_x21_ls2_y),
1908 ISP3X_RAWAWB_YUV_X_COOR_Y_2, id);
1909
1910 isp3_param_write(params_vdev,
1911 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls2_u,
1912 arg->sw_rawawb_vec_x21_ls2_u),
1913 ISP3X_RAWAWB_YUV_X_COOR_U_2, id);
1914
1915 isp3_param_write(params_vdev,
1916 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls2_v,
1917 arg->sw_rawawb_vec_x21_ls2_v),
1918 ISP3X_RAWAWB_YUV_X_COOR_V_2, id);
1919
1920 isp3_param_write(params_vdev,
1921 ISP_PACK_4BYTE(arg->sw_rawawb_dis_x1x2_ls2,
1922 0,
1923 arg->sw_rawawb_rotu0_ls2,
1924 arg->sw_rawawb_rotu1_ls2),
1925 ISP3X_RAWAWB_YUV_X1X2_DIS_2, id);
1926
1927 isp3_param_write(params_vdev,
1928 ISP_PACK_4BYTE(arg->sw_rawawb_rotu2_ls2,
1929 arg->sw_rawawb_rotu3_ls2,
1930 arg->sw_rawawb_rotu4_ls2,
1931 arg->sw_rawawb_rotu5_ls2),
1932 ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_2, id);
1933
1934 isp3_param_write(params_vdev,
1935 ISP_PACK_2SHORT(arg->sw_rawawb_th0_ls2,
1936 arg->sw_rawawb_th1_ls2),
1937 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_2, id);
1938
1939 isp3_param_write(params_vdev,
1940 ISP_PACK_2SHORT(arg->sw_rawawb_th2_ls2,
1941 arg->sw_rawawb_th3_ls2),
1942 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_2, id);
1943
1944 isp3_param_write(params_vdev,
1945 ISP_PACK_2SHORT(arg->sw_rawawb_th4_ls2,
1946 arg->sw_rawawb_th5_ls2),
1947 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_2, id);
1948
1949 isp3_param_write(params_vdev,
1950 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls3_y,
1951 arg->sw_rawawb_vec_x21_ls3_y),
1952 ISP3X_RAWAWB_YUV_X_COOR_Y_3, id);
1953
1954 isp3_param_write(params_vdev,
1955 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls3_u,
1956 arg->sw_rawawb_vec_x21_ls3_u),
1957 ISP3X_RAWAWB_YUV_X_COOR_U_3, id);
1958
1959 isp3_param_write(params_vdev,
1960 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls3_v,
1961 arg->sw_rawawb_vec_x21_ls3_v),
1962 ISP3X_RAWAWB_YUV_X_COOR_V_3, id);
1963
1964 isp3_param_write(params_vdev,
1965 ISP_PACK_4BYTE(arg->sw_rawawb_dis_x1x2_ls3,
1966 0,
1967 arg->sw_rawawb_rotu0_ls3,
1968 arg->sw_rawawb_rotu1_ls3),
1969 ISP3X_RAWAWB_YUV_X1X2_DIS_3, id);
1970
1971 isp3_param_write(params_vdev,
1972 ISP_PACK_4BYTE(arg->sw_rawawb_rotu2_ls3,
1973 arg->sw_rawawb_rotu3_ls3,
1974 arg->sw_rawawb_rotu4_ls3,
1975 arg->sw_rawawb_rotu5_ls3),
1976 ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_3, id);
1977
1978 isp3_param_write(params_vdev,
1979 ISP_PACK_2SHORT(arg->sw_rawawb_th0_ls3,
1980 arg->sw_rawawb_th1_ls3),
1981 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_3, id);
1982
1983 isp3_param_write(params_vdev,
1984 ISP_PACK_2SHORT(arg->sw_rawawb_th2_ls3,
1985 arg->sw_rawawb_th3_ls3),
1986 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_3, id);
1987
1988 isp3_param_write(params_vdev,
1989 ISP_PACK_2SHORT(arg->sw_rawawb_th4_ls3,
1990 arg->sw_rawawb_th5_ls3),
1991 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_3, id);
1992
1993 isp3_param_write(params_vdev,
1994 ISP_PACK_2SHORT(arg->sw_rawawb_wt0,
1995 arg->sw_rawawb_wt1),
1996 ISP3X_RAWAWB_RGB2XY_WT01, id);
1997
1998 isp3_param_write(params_vdev,
1999 arg->sw_rawawb_wt2,
2000 ISP3X_RAWAWB_RGB2XY_WT2, id);
2001
2002 isp3_param_write(params_vdev,
2003 ISP_PACK_2SHORT(arg->sw_rawawb_mat0_x,
2004 arg->sw_rawawb_mat0_y),
2005 ISP3X_RAWAWB_RGB2XY_MAT0_XY, id);
2006
2007 isp3_param_write(params_vdev,
2008 ISP_PACK_2SHORT(arg->sw_rawawb_mat1_x,
2009 arg->sw_rawawb_mat1_y),
2010 ISP3X_RAWAWB_RGB2XY_MAT1_XY, id);
2011
2012 isp3_param_write(params_vdev,
2013 ISP_PACK_2SHORT(arg->sw_rawawb_mat2_x,
2014 arg->sw_rawawb_mat2_y),
2015 ISP3X_RAWAWB_RGB2XY_MAT2_XY, id);
2016
2017 isp3_param_write(params_vdev,
2018 ISP_PACK_2SHORT(arg->sw_rawawb_nor_x0_0,
2019 arg->sw_rawawb_nor_x1_0),
2020 ISP3X_RAWAWB_XY_DETC_NOR_X_0, id);
2021
2022 isp3_param_write(params_vdev,
2023 ISP_PACK_2SHORT(arg->sw_rawawb_nor_y0_0,
2024 arg->sw_rawawb_nor_y1_0),
2025 ISP3X_RAWAWB_XY_DETC_NOR_Y_0, id);
2026
2027 isp3_param_write(params_vdev,
2028 ISP_PACK_2SHORT(arg->sw_rawawb_big_x0_0,
2029 arg->sw_rawawb_big_x1_0),
2030 ISP3X_RAWAWB_XY_DETC_BIG_X_0, id);
2031
2032 isp3_param_write(params_vdev,
2033 ISP_PACK_2SHORT(arg->sw_rawawb_big_y0_0,
2034 arg->sw_rawawb_big_y1_0),
2035 ISP3X_RAWAWB_XY_DETC_BIG_Y_0, id);
2036
2037 isp3_param_write(params_vdev,
2038 ISP_PACK_2SHORT(arg->sw_rawawb_nor_x0_1,
2039 arg->sw_rawawb_nor_x1_1),
2040 ISP3X_RAWAWB_XY_DETC_NOR_X_1, id);
2041
2042 isp3_param_write(params_vdev,
2043 ISP_PACK_2SHORT(arg->sw_rawawb_nor_y0_1,
2044 arg->sw_rawawb_nor_y1_1),
2045 ISP3X_RAWAWB_XY_DETC_NOR_Y_1, id);
2046
2047 isp3_param_write(params_vdev,
2048 ISP_PACK_2SHORT(arg->sw_rawawb_big_x0_1,
2049 arg->sw_rawawb_big_x1_1),
2050 ISP3X_RAWAWB_XY_DETC_BIG_X_1, id);
2051
2052 isp3_param_write(params_vdev,
2053 ISP_PACK_2SHORT(arg->sw_rawawb_big_y0_1,
2054 arg->sw_rawawb_big_y1_1),
2055 ISP3X_RAWAWB_XY_DETC_BIG_Y_1, id);
2056
2057 isp3_param_write(params_vdev,
2058 ISP_PACK_2SHORT(arg->sw_rawawb_nor_x0_2,
2059 arg->sw_rawawb_nor_x1_2),
2060 ISP3X_RAWAWB_XY_DETC_NOR_X_2, id);
2061
2062 isp3_param_write(params_vdev,
2063 ISP_PACK_2SHORT(arg->sw_rawawb_nor_y0_2,
2064 arg->sw_rawawb_nor_y1_2),
2065 ISP3X_RAWAWB_XY_DETC_NOR_Y_2, id);
2066
2067 isp3_param_write(params_vdev,
2068 ISP_PACK_2SHORT(arg->sw_rawawb_big_x0_2,
2069 arg->sw_rawawb_big_x1_2),
2070 ISP3X_RAWAWB_XY_DETC_BIG_X_2, id);
2071
2072 isp3_param_write(params_vdev,
2073 ISP_PACK_2SHORT(arg->sw_rawawb_big_y0_2,
2074 arg->sw_rawawb_big_y1_2),
2075 ISP3X_RAWAWB_XY_DETC_BIG_Y_2, id);
2076
2077 isp3_param_write(params_vdev,
2078 ISP_PACK_2SHORT(arg->sw_rawawb_nor_x0_3,
2079 arg->sw_rawawb_nor_x1_3),
2080 ISP3X_RAWAWB_XY_DETC_NOR_X_3, id);
2081
2082 isp3_param_write(params_vdev,
2083 ISP_PACK_2SHORT(arg->sw_rawawb_nor_y0_3,
2084 arg->sw_rawawb_nor_y1_3),
2085 ISP3X_RAWAWB_XY_DETC_NOR_Y_3, id);
2086
2087 isp3_param_write(params_vdev,
2088 ISP_PACK_2SHORT(arg->sw_rawawb_big_x0_3,
2089 arg->sw_rawawb_big_x1_3),
2090 ISP3X_RAWAWB_XY_DETC_BIG_X_3, id);
2091
2092 isp3_param_write(params_vdev,
2093 ISP_PACK_2SHORT(arg->sw_rawawb_big_y0_3,
2094 arg->sw_rawawb_big_y1_3),
2095 ISP3X_RAWAWB_XY_DETC_BIG_Y_3, id);
2096
2097 isp3_param_write(params_vdev,
2098 ISP_PACK_2SHORT(arg->sw_rawawb_nor_x0_4,
2099 arg->sw_rawawb_nor_x1_4),
2100 ISP3X_RAWAWB_XY_DETC_NOR_X_4, id);
2101
2102 isp3_param_write(params_vdev,
2103 ISP_PACK_2SHORT(arg->sw_rawawb_nor_y0_4,
2104 arg->sw_rawawb_nor_y1_4),
2105 ISP3X_RAWAWB_XY_DETC_NOR_Y_4, id);
2106
2107 isp3_param_write(params_vdev,
2108 ISP_PACK_2SHORT(arg->sw_rawawb_big_x0_4,
2109 arg->sw_rawawb_big_x1_4),
2110 ISP3X_RAWAWB_XY_DETC_BIG_X_4, id);
2111
2112 isp3_param_write(params_vdev,
2113 ISP_PACK_2SHORT(arg->sw_rawawb_big_y0_4,
2114 arg->sw_rawawb_big_y1_4),
2115 ISP3X_RAWAWB_XY_DETC_BIG_Y_4, id);
2116
2117 isp3_param_write(params_vdev,
2118 ISP_PACK_2SHORT(arg->sw_rawawb_nor_x0_5,
2119 arg->sw_rawawb_nor_x1_5),
2120 ISP3X_RAWAWB_XY_DETC_NOR_X_5, id);
2121
2122 isp3_param_write(params_vdev,
2123 ISP_PACK_2SHORT(arg->sw_rawawb_nor_y0_5,
2124 arg->sw_rawawb_nor_y1_5),
2125 ISP3X_RAWAWB_XY_DETC_NOR_Y_5, id);
2126
2127 isp3_param_write(params_vdev,
2128 ISP_PACK_2SHORT(arg->sw_rawawb_big_x0_5,
2129 arg->sw_rawawb_big_x1_5),
2130 ISP3X_RAWAWB_XY_DETC_BIG_X_5, id);
2131
2132 isp3_param_write(params_vdev,
2133 ISP_PACK_2SHORT(arg->sw_rawawb_big_y0_5,
2134 arg->sw_rawawb_big_y1_5),
2135 ISP3X_RAWAWB_XY_DETC_BIG_Y_5, id);
2136
2137 isp3_param_write(params_vdev,
2138 ISP_PACK_2SHORT(arg->sw_rawawb_nor_x0_6,
2139 arg->sw_rawawb_nor_x1_6),
2140 ISP3X_RAWAWB_XY_DETC_NOR_X_6, id);
2141
2142 isp3_param_write(params_vdev,
2143 ISP_PACK_2SHORT(arg->sw_rawawb_nor_y0_6,
2144 arg->sw_rawawb_nor_y1_6),
2145 ISP3X_RAWAWB_XY_DETC_NOR_Y_6, id);
2146
2147 isp3_param_write(params_vdev,
2148 ISP_PACK_2SHORT(arg->sw_rawawb_big_x0_6,
2149 arg->sw_rawawb_big_x1_6),
2150 ISP3X_RAWAWB_XY_DETC_BIG_X_6, id);
2151
2152 isp3_param_write(params_vdev,
2153 ISP_PACK_2SHORT(arg->sw_rawawb_big_y0_6,
2154 arg->sw_rawawb_big_y1_6),
2155 ISP3X_RAWAWB_XY_DETC_BIG_Y_6, id);
2156
2157 isp3_param_write(params_vdev,
2158 (arg->sw_rawawb_exc_wp_region0_excen0 & 0x1) << 0 |
2159 (arg->sw_rawawb_exc_wp_region0_excen1 & 0x1) << 1 |
2160 (arg->sw_rawawb_exc_wp_region0_measen & 0x1) << 2 |
2161 (arg->sw_rawawb_exc_wp_region0_domain & 0x1) << 3 |
2162 (arg->sw_rawawb_exc_wp_region1_excen0 & 0x1) << 4 |
2163 (arg->sw_rawawb_exc_wp_region1_excen1 & 0x1) << 5 |
2164 (arg->sw_rawawb_exc_wp_region1_measen & 0x1) << 6 |
2165 (arg->sw_rawawb_exc_wp_region1_domain & 0x1) << 7 |
2166 (arg->sw_rawawb_exc_wp_region2_excen0 & 0x1) << 8 |
2167 (arg->sw_rawawb_exc_wp_region2_excen1 & 0x1) << 9 |
2168 (arg->sw_rawawb_exc_wp_region2_measen & 0x1) << 10 |
2169 (arg->sw_rawawb_exc_wp_region2_domain & 0x1) << 11 |
2170 (arg->sw_rawawb_exc_wp_region3_excen0 & 0x1) << 12 |
2171 (arg->sw_rawawb_exc_wp_region3_excen1 & 0x1) << 13 |
2172 (arg->sw_rawawb_exc_wp_region3_measen & 0x1) << 14 |
2173 (arg->sw_rawawb_exc_wp_region3_domain & 0x1) << 15 |
2174 (arg->sw_rawawb_exc_wp_region4_excen0 & 0x1) << 16 |
2175 (arg->sw_rawawb_exc_wp_region4_excen1 & 0x1) << 17 |
2176 (arg->sw_rawawb_exc_wp_region4_domain & 0x1) << 19 |
2177 (arg->sw_rawawb_exc_wp_region5_excen0 & 0x1) << 20 |
2178 (arg->sw_rawawb_exc_wp_region5_excen1 & 0x1) << 21 |
2179 (arg->sw_rawawb_exc_wp_region5_domain & 0x1) << 23 |
2180 (arg->sw_rawawb_exc_wp_region6_excen0 & 0x1) << 24 |
2181 (arg->sw_rawawb_exc_wp_region6_excen1 & 0x1) << 25 |
2182 (arg->sw_rawawb_exc_wp_region6_domain & 0x1) << 27 |
2183 (arg->sw_rawawb_multiwindow_en & 0x1) << 31,
2184 ISP3X_RAWAWB_MULTIWINDOW_EXC_CTRL, id);
2185
2186 isp3_param_write(params_vdev,
2187 ISP_PACK_2SHORT(arg->sw_rawawb_multiwindow0_h_offs,
2188 arg->sw_rawawb_multiwindow0_v_offs),
2189 ISP3X_RAWAWB_MULTIWINDOW0_OFFS, id);
2190 isp3_param_write(params_vdev,
2191 ISP_PACK_2SHORT(arg->sw_rawawb_multiwindow0_h_size,
2192 arg->sw_rawawb_multiwindow0_v_size),
2193 ISP3X_RAWAWB_MULTIWINDOW0_SIZE, id);
2194 isp3_param_write(params_vdev,
2195 ISP_PACK_2SHORT(arg->sw_rawawb_multiwindow1_h_offs,
2196 arg->sw_rawawb_multiwindow1_v_offs),
2197 ISP3X_RAWAWB_MULTIWINDOW1_OFFS, id);
2198 isp3_param_write(params_vdev,
2199 ISP_PACK_2SHORT(arg->sw_rawawb_multiwindow1_h_size,
2200 arg->sw_rawawb_multiwindow1_v_size),
2201 ISP3X_RAWAWB_MULTIWINDOW1_SIZE, id);
2202 isp3_param_write(params_vdev,
2203 ISP_PACK_2SHORT(arg->sw_rawawb_multiwindow2_h_offs,
2204 arg->sw_rawawb_multiwindow2_v_offs),
2205 ISP3X_RAWAWB_MULTIWINDOW2_OFFS, id);
2206 isp3_param_write(params_vdev,
2207 ISP_PACK_2SHORT(arg->sw_rawawb_multiwindow2_h_size,
2208 arg->sw_rawawb_multiwindow2_v_size),
2209 ISP3X_RAWAWB_MULTIWINDOW2_SIZE, id);
2210 isp3_param_write(params_vdev,
2211 ISP_PACK_2SHORT(arg->sw_rawawb_multiwindow3_h_offs,
2212 arg->sw_rawawb_multiwindow3_v_offs),
2213 ISP3X_RAWAWB_MULTIWINDOW3_OFFS, id);
2214 isp3_param_write(params_vdev,
2215 ISP_PACK_2SHORT(arg->sw_rawawb_multiwindow3_h_size,
2216 arg->sw_rawawb_multiwindow3_v_size),
2217 ISP3X_RAWAWB_MULTIWINDOW3_SIZE, id);
2218
2219 isp3_param_write(params_vdev,
2220 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region0_xu0,
2221 arg->sw_rawawb_exc_wp_region0_xu1),
2222 ISP3X_RAWAWB_EXC_WP_REGION0_XU, id);
2223
2224 isp3_param_write(params_vdev,
2225 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region0_yv0,
2226 arg->sw_rawawb_exc_wp_region0_yv1),
2227 ISP3X_RAWAWB_EXC_WP_REGION0_YV, id);
2228
2229 isp3_param_write(params_vdev,
2230 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region1_xu0,
2231 arg->sw_rawawb_exc_wp_region1_xu1),
2232 ISP3X_RAWAWB_EXC_WP_REGION1_XU, id);
2233
2234 isp3_param_write(params_vdev,
2235 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region1_yv0,
2236 arg->sw_rawawb_exc_wp_region1_yv1),
2237 ISP3X_RAWAWB_EXC_WP_REGION1_YV, id);
2238
2239 isp3_param_write(params_vdev,
2240 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region2_xu0,
2241 arg->sw_rawawb_exc_wp_region2_xu1),
2242 ISP3X_RAWAWB_EXC_WP_REGION2_XU, id);
2243
2244 isp3_param_write(params_vdev,
2245 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region2_yv0,
2246 arg->sw_rawawb_exc_wp_region2_yv1),
2247 ISP3X_RAWAWB_EXC_WP_REGION2_YV, id);
2248
2249 isp3_param_write(params_vdev,
2250 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region3_xu0,
2251 arg->sw_rawawb_exc_wp_region3_xu1),
2252 ISP3X_RAWAWB_EXC_WP_REGION3_XU, id);
2253
2254 isp3_param_write(params_vdev,
2255 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region3_yv0,
2256 arg->sw_rawawb_exc_wp_region3_yv1),
2257 ISP3X_RAWAWB_EXC_WP_REGION3_YV, id);
2258
2259 isp3_param_write(params_vdev,
2260 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region4_xu0,
2261 arg->sw_rawawb_exc_wp_region4_xu1),
2262 ISP3X_RAWAWB_EXC_WP_REGION4_XU, id);
2263
2264 isp3_param_write(params_vdev,
2265 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region4_yv0,
2266 arg->sw_rawawb_exc_wp_region4_yv1),
2267 ISP3X_RAWAWB_EXC_WP_REGION4_YV, id);
2268
2269 isp3_param_write(params_vdev,
2270 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region5_xu0,
2271 arg->sw_rawawb_exc_wp_region5_xu1),
2272 ISP3X_RAWAWB_EXC_WP_REGION5_XU, id);
2273
2274 isp3_param_write(params_vdev,
2275 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region5_yv0,
2276 arg->sw_rawawb_exc_wp_region5_yv1),
2277 ISP3X_RAWAWB_EXC_WP_REGION5_YV, id);
2278
2279 isp3_param_write(params_vdev,
2280 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region6_xu0,
2281 arg->sw_rawawb_exc_wp_region6_xu1),
2282 ISP3X_RAWAWB_EXC_WP_REGION6_XU, id);
2283
2284 isp3_param_write(params_vdev,
2285 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region6_yv0,
2286 arg->sw_rawawb_exc_wp_region6_yv1),
2287 ISP3X_RAWAWB_EXC_WP_REGION6_YV, id);
2288
2289 if (params_vdev->dev->hw_dev->is_single)
2290 isp_rawawb_cfg_sram(params_vdev, arg, false, id);
2291 else
2292 memcpy(arg_rec->sw_rawawb_wp_blk_wei_w,
2293 arg->sw_rawawb_wp_blk_wei_w,
2294 ISP3X_RAWAWB_WEIGHT_NUM);
2295
2296 /* avoid to override the old enable value */
2297 value = isp3_param_read(params_vdev, ISP3X_RAWAWB_CTRL, id);
2298 value &= ISP3X_MODULE_EN;
2299 isp3_param_write(params_vdev,
2300 value |
2301 (arg->sw_rawawb_uv_en0 & 0x1) << 1 |
2302 (arg->sw_rawawb_xy_en0 & 0x1) << 2 |
2303 (arg->sw_rawawb_3dyuv_en0 & 0x1) << 3 |
2304 (arg->sw_rawawb_3dyuv_ls_idx0 & 0x7) << 4 |
2305 (arg->sw_rawawb_3dyuv_ls_idx1 & 0x7) << 7 |
2306 (arg->sw_rawawb_3dyuv_ls_idx2 & 0x7) << 10 |
2307 (arg->sw_rawawb_3dyuv_ls_idx3 & 0x7) << 13 |
2308 (arg->sw_rawawb_wind_size & 0x1) << 18 |
2309 (arg->sw_rawlsc_bypass_en & 0x1) << 19 |
2310 (arg->sw_rawawb_light_num & 0x7) << 20 |
2311 (arg->sw_rawawb_uv_en1 & 0x1) << 24 |
2312 (arg->sw_rawawb_xy_en1 & 0x1) << 25 |
2313 (arg->sw_rawawb_3dyuv_en1 & 0x1) << 26,
2314 ISP3X_RAWAWB_CTRL, id);
2315
2316 value = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH, id);
2317 value &= ~(ISP3X_RAWAWB_SEL(3));
2318 value |= ISP3X_RAWAWB_SEL(arg->rawawb_sel);
2319 isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH, id);
2320 }
2321
2322 static void
isp_rawawb_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)2323 isp_rawawb_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
2324 {
2325 u32 awb_ctrl;
2326
2327 awb_ctrl = isp3_param_read(params_vdev, ISP3X_RAWAWB_CTRL, id);
2328 awb_ctrl &= ~ISP3X_REG_WR_MASK;
2329 if (en)
2330 awb_ctrl |= ISP3X_MODULE_EN;
2331 else
2332 awb_ctrl &= ~ISP3X_MODULE_EN;
2333
2334 isp3_param_write(params_vdev, awb_ctrl, ISP3X_RAWAWB_CTRL, id);
2335 }
2336
2337 static void
isp_rawhstlite_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistlite_cfg * arg,u32 id)2338 isp_rawhstlite_config(struct rkisp_isp_params_vdev *params_vdev,
2339 const struct isp2x_rawhistlite_cfg *arg, u32 id)
2340 {
2341 u32 i;
2342 u32 value;
2343 u32 hist_ctrl;
2344 u32 block_hsize, block_vsize;
2345
2346 /* avoid to override the old enable value */
2347 hist_ctrl = isp3_param_read(params_vdev, ISP3X_RAWHIST_LITE_CTRL, id);
2348 hist_ctrl &= ISP3X_RAWHIST_EN;
2349 hist_ctrl = hist_ctrl |
2350 ISP3X_RAWHIST_MODE(arg->mode) |
2351 ISP3X_RAWHIST_DATASEL(arg->data_sel) |
2352 ISP3X_RAWHIST_WATERLINE(arg->waterline) |
2353 ISP3X_RAWHIST_STEPSIZE(arg->stepsize);
2354 isp3_param_write(params_vdev, hist_ctrl, ISP3X_RAWHIST_LITE_CTRL, id);
2355
2356 isp3_param_write(params_vdev,
2357 ISP_PACK_2SHORT(arg->win.h_offs, arg->win.v_offs),
2358 ISP3X_RAWHIST_LITE_OFFS, id);
2359
2360 block_hsize = arg->win.h_size / ISP3X_RAWHISTLITE_ROW_NUM - 1;
2361 block_vsize = arg->win.v_size / ISP3X_RAWHISTLITE_COLUMN_NUM - 1;
2362 block_hsize &= 0xFFFE;
2363 block_vsize &= 0xFFFE;
2364 isp3_param_write(params_vdev,
2365 ISP_PACK_2SHORT(block_hsize, block_vsize),
2366 ISP3X_RAWHIST_LITE_SIZE, id);
2367
2368 isp3_param_write(params_vdev,
2369 ISP_PACK_4BYTE(arg->rcc, arg->gcc, arg->bcc, arg->off),
2370 ISP3X_RAWHIST_LITE_RAW2Y_CC, id);
2371
2372 for (i = 0; i < (ISP3X_RAWHISTLITE_WEIGHT_REG_SIZE / 4); i++) {
2373 value = ISP_PACK_4BYTE(arg->weight[4 * i + 0],
2374 arg->weight[4 * i + 1],
2375 arg->weight[4 * i + 2],
2376 arg->weight[4 * i + 3]);
2377 isp3_param_write(params_vdev, value,
2378 ISP3X_RAWHIST_LITE_WEIGHT + 4 * i, id);
2379 }
2380
2381 value = ISP_PACK_4BYTE(arg->weight[4 * i + 0], 0, 0, 0);
2382 isp3_param_write(params_vdev, value,
2383 ISP3X_RAWHIST_LITE_WEIGHT + 4 * i, id);
2384 }
2385
2386 static void
isp_rawhstlite_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)2387 isp_rawhstlite_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
2388 {
2389 u32 hist_ctrl;
2390
2391 hist_ctrl = isp3_param_read(params_vdev, ISP3X_RAWHIST_LITE_CTRL, id);
2392 hist_ctrl &= ~(ISP3X_MODULE_EN | ISP3X_REG_WR_MASK);
2393
2394 if (en)
2395 hist_ctrl |= ISP3X_MODULE_EN;
2396
2397 isp3_param_write(params_vdev, hist_ctrl, ISP3X_RAWHIST_LITE_CTRL, id);
2398 }
2399
2400 static void
isp_rawhstbig_cfg_sram(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg,u32 blk_no,bool is_check,u32 id)2401 isp_rawhstbig_cfg_sram(struct rkisp_isp_params_vdev *params_vdev,
2402 const struct isp2x_rawhistbig_cfg *arg,
2403 u32 blk_no, bool is_check, u32 id)
2404 {
2405 u32 i, j, wnd_num_idx, value;
2406 u8 weight15x15[ISP3X_RAWHISTBIG_WEIGHT_REG_SIZE];
2407 const u32 hist_wnd_num[] = {5, 5, 15, 15};
2408 u32 addr;
2409
2410 switch (blk_no) {
2411 case 1:
2412 addr = ISP3X_RAWHIST_BIG2_BASE;
2413 break;
2414 case 2:
2415 addr = ISP3X_RAWHIST_BIG3_BASE;
2416 break;
2417 case 0:
2418 default:
2419 addr = ISP3X_RAWHIST_BIG1_BASE;
2420 break;
2421 }
2422
2423 value = ISP3X_RAWHIST_EN;
2424 if (is_check &&
2425 !(isp3_param_read(params_vdev, addr + ISP3X_RAWHIST_BIG_CTRL, id) & value))
2426 return;
2427
2428 wnd_num_idx = arg->wnd_num;
2429 memset(weight15x15, 0, sizeof(weight15x15));
2430 for (i = 0; i < hist_wnd_num[wnd_num_idx]; i++) {
2431 for (j = 0; j < hist_wnd_num[wnd_num_idx]; j++) {
2432 weight15x15[i * ISP3X_RAWHISTBIG_ROW_NUM + j] =
2433 arg->weight[i * hist_wnd_num[wnd_num_idx] + j];
2434 }
2435 }
2436
2437 for (i = 0; i < (ISP3X_RAWHISTBIG_WEIGHT_REG_SIZE / 5); i++) {
2438 value = (weight15x15[5 * i + 0] & 0x3f) |
2439 (weight15x15[5 * i + 1] & 0x3f) << 6 |
2440 (weight15x15[5 * i + 2] & 0x3f) << 12 |
2441 (weight15x15[5 * i + 3] & 0x3f) << 18 |
2442 (weight15x15[5 * i + 4] & 0x3f) << 24;
2443 isp3_param_write_direct(params_vdev, value,
2444 addr + ISP3X_RAWHIST_BIG_WEIGHT_BASE, id);
2445 }
2446 }
2447
2448 static void
isp_rawhstbig_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg,u32 blk_no,u32 id)2449 isp_rawhstbig_config(struct rkisp_isp_params_vdev *params_vdev,
2450 const struct isp2x_rawhistbig_cfg *arg, u32 blk_no, u32 id)
2451 {
2452 struct isp3x_isp_params_cfg *params_rec = params_vdev->isp3x_params + id;
2453 struct rkisp_device *dev = params_vdev->dev;
2454 struct isp2x_rawhistbig_cfg *arg_rec;
2455 u32 hist_ctrl, block_hsize, block_vsize, wnd_num_idx;
2456 const u32 hist_wnd_num[] = {5, 5, 15, 15};
2457 u32 addr;
2458
2459 switch (blk_no) {
2460 case 1:
2461 addr = ISP3X_RAWHIST_BIG2_BASE;
2462 arg_rec = ¶ms_rec->meas.rawhist1;
2463 break;
2464 case 2:
2465 addr = ISP3X_RAWHIST_BIG3_BASE;
2466 arg_rec = ¶ms_rec->meas.rawhist2;
2467 break;
2468 case 0:
2469 default:
2470 addr = ISP3X_RAWHIST_BIG1_BASE;
2471 arg_rec = ¶ms_rec->meas.rawhist3;
2472 break;
2473 }
2474
2475 wnd_num_idx = arg->wnd_num;
2476 /* avoid to override the old enable value */
2477 hist_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWHIST_BIG_CTRL, id);
2478 hist_ctrl &= ISP3X_RAWHIST_EN;
2479 hist_ctrl = hist_ctrl |
2480 ISP3X_RAWHIST_MODE(arg->mode) |
2481 ISP3X_RAWHIST_DATASEL(arg->data_sel) |
2482 ISP3X_RAWHIST_WATERLINE(arg->waterline) |
2483 ISP3X_RAWHIST_WND_NUM(arg->wnd_num) |
2484 ISP3X_RAWHIST_STEPSIZE(arg->stepsize);
2485 isp3_param_write(params_vdev, hist_ctrl, addr + ISP3X_RAWHIST_BIG_CTRL, id);
2486
2487 isp3_param_write(params_vdev,
2488 ISP_PACK_2SHORT(arg->win.h_offs, arg->win.v_offs),
2489 addr + ISP3X_RAWHIST_BIG_OFFS, id);
2490
2491 block_hsize = arg->win.h_size / hist_wnd_num[wnd_num_idx] - 1;
2492 block_vsize = arg->win.v_size / hist_wnd_num[wnd_num_idx] - 1;
2493 block_hsize &= 0xFFFE;
2494 block_vsize &= 0xFFFE;
2495 isp3_param_write(params_vdev,
2496 ISP_PACK_2SHORT(block_hsize, block_vsize),
2497 addr + ISP3X_RAWHIST_BIG_SIZE, id);
2498
2499 isp3_param_write(params_vdev,
2500 ISP_PACK_4BYTE(arg->rcc, arg->gcc, arg->bcc, arg->off),
2501 addr + ISP3X_RAWHIST_BIG_RAW2Y_CC, id);
2502
2503 if (dev->hw_dev->is_single)
2504 isp_rawhstbig_cfg_sram(params_vdev, arg, blk_no, false, id);
2505 else
2506 *arg_rec = *arg;
2507 }
2508
2509 static void
isp_rawhstbig_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 blk_no,u32 id)2510 isp_rawhstbig_enable(struct rkisp_isp_params_vdev *params_vdev,
2511 bool en, u32 blk_no, u32 id)
2512 {
2513 u32 hist_ctrl;
2514 u32 addr;
2515
2516 switch (blk_no) {
2517 case 1:
2518 addr = ISP3X_RAWHIST_BIG2_BASE;
2519 break;
2520 case 2:
2521 addr = ISP3X_RAWHIST_BIG3_BASE;
2522 break;
2523 case 0:
2524 default:
2525 addr = ISP3X_RAWHIST_BIG1_BASE;
2526 break;
2527 }
2528
2529 hist_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWHIST_BIG_CTRL, id);
2530 hist_ctrl &= ~(ISP3X_RAWHIST_EN | ISP3X_REG_WR_MASK);
2531 if (en)
2532 hist_ctrl |= ISP3X_RAWHIST_EN;
2533
2534 isp3_param_write(params_vdev, hist_ctrl, addr + ISP3X_RAWHIST_BIG_CTRL, id);
2535 }
2536
2537 static void
isp_rawhst1_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg,u32 id)2538 isp_rawhst1_config(struct rkisp_isp_params_vdev *params_vdev,
2539 const struct isp2x_rawhistbig_cfg *arg, u32 id)
2540 {
2541 isp_rawhstbig_config(params_vdev, arg, 1, id);
2542 }
2543
2544 static void
isp_rawhst1_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)2545 isp_rawhst1_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
2546 {
2547 isp_rawhstbig_enable(params_vdev, en, 1, id);
2548 }
2549
2550 static void
isp_rawhst2_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg,u32 id)2551 isp_rawhst2_config(struct rkisp_isp_params_vdev *params_vdev,
2552 const struct isp2x_rawhistbig_cfg *arg, u32 id)
2553 {
2554 isp_rawhstbig_config(params_vdev, arg, 2, id);
2555 }
2556
2557 static void
isp_rawhst2_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)2558 isp_rawhst2_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
2559 {
2560 isp_rawhstbig_enable(params_vdev, en, 2, id);
2561 }
2562
2563 static void
isp_rawhst3_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg,u32 id)2564 isp_rawhst3_config(struct rkisp_isp_params_vdev *params_vdev,
2565 const struct isp2x_rawhistbig_cfg *arg, u32 id)
2566 {
2567 isp_rawhstbig_config(params_vdev, arg, 0, id);
2568 }
2569
2570 static void
isp_rawhst3_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)2571 isp_rawhst3_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
2572 {
2573 isp_rawhstbig_enable(params_vdev, en, 0, id);
2574 }
2575
2576 static void
isp_hdrmge_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_hdrmge_cfg * arg,enum rkisp_params_type type,u32 id)2577 isp_hdrmge_config(struct rkisp_isp_params_vdev *params_vdev,
2578 const struct isp3x_hdrmge_cfg *arg,
2579 enum rkisp_params_type type, u32 id)
2580 {
2581 u32 value;
2582 int i;
2583
2584 if (type == RKISP_PARAMS_SHD || type == RKISP_PARAMS_ALL) {
2585 value = ISP_PACK_2SHORT(arg->gain0, arg->gain0_inv);
2586 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_GAIN0, id);
2587
2588 value = ISP_PACK_2SHORT(arg->gain1, arg->gain1_inv);
2589 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_GAIN1, id);
2590
2591 value = arg->gain2;
2592 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_GAIN2, id);
2593
2594 value = isp3_param_read_cache(params_vdev, ISP3X_HDRMGE_CTRL, id);
2595 if (arg->s_base)
2596 value |= BIT(1);
2597 else
2598 value &= ~BIT(1);
2599 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_CTRL, id);
2600 }
2601
2602 if (type == RKISP_PARAMS_IMD || type == RKISP_PARAMS_ALL) {
2603 value = ISP_PACK_4BYTE(arg->ms_dif_0p8, arg->ms_diff_0p15,
2604 arg->lm_dif_0p9, arg->lm_dif_0p15);
2605 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_LIGHTZ, id);
2606 value = (arg->ms_scl & 0x7ff) |
2607 (arg->ms_thd0 & 0x3ff) << 12 |
2608 (arg->ms_thd1 & 0x3ff) << 22;
2609 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_MS_DIFF, id);
2610 value = (arg->lm_scl & 0x7ff) |
2611 (arg->lm_thd0 & 0x3ff) << 12 |
2612 (arg->lm_thd1 & 0x3ff) << 22;
2613 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_LM_DIFF, id);
2614
2615 for (i = 0; i < ISP3X_HDRMGE_L_CURVE_NUM; i++) {
2616 value = ISP_PACK_2SHORT(arg->curve.curve_0[i], arg->curve.curve_1[i]);
2617 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_DIFF_Y0 + 4 * i, id);
2618 }
2619
2620 for (i = 0; i < ISP3X_HDRMGE_E_CURVE_NUM; i++) {
2621 value = arg->e_y[i];
2622 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_OVER_Y0 + 4 * i, id);
2623 }
2624 }
2625 }
2626
2627 static void
isp_hdrmge_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)2628 isp_hdrmge_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
2629 {
2630 }
2631
2632 static void
isp_hdrdrc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_drc_cfg * arg,enum rkisp_params_type type,u32 id)2633 isp_hdrdrc_config(struct rkisp_isp_params_vdev *params_vdev,
2634 const struct isp3x_drc_cfg *arg,
2635 enum rkisp_params_type type, u32 id)
2636 {
2637 u32 i, value;
2638
2639 if (type == RKISP_PARAMS_IMD)
2640 return;
2641
2642 value = (arg->offset_pow2 & 0x0F) << 28 |
2643 (arg->compres_scl & 0x1FFF) << 14 |
2644 (arg->position & 0x03FFF);
2645 isp3_param_write(params_vdev, value, ISP3X_DRC_CTRL1, id);
2646
2647 value = (arg->delta_scalein & 0xFF) << 24 |
2648 (arg->hpdetail_ratio & 0xFFF) << 12 |
2649 (arg->lpdetail_ratio & 0xFFF);
2650 isp3_param_write(params_vdev, value, ISP3X_DRC_LPRATIO, id);
2651
2652 value = ISP_PACK_4BYTE(arg->bilat_wt_off, 0, arg->weipre_frame, arg->weicur_pix);
2653 isp3_param_write(params_vdev, value, ISP3X_DRC_EXPLRATIO, id);
2654
2655 value = (arg->force_sgm_inv0 & 0xFFFF) << 16 |
2656 (arg->motion_scl & 0xFF) << 8 |
2657 (arg->edge_scl & 0xFF);
2658 isp3_param_write(params_vdev, value, ISP3X_DRC_SIGMA, id);
2659
2660 value = ISP_PACK_2SHORT(arg->space_sgm_inv0, arg->space_sgm_inv1);
2661 isp3_param_write(params_vdev, value, ISP3X_DRC_SPACESGM, id);
2662
2663 value = ISP_PACK_2SHORT(arg->range_sgm_inv0, arg->range_sgm_inv1);
2664 isp3_param_write(params_vdev, value, ISP3X_DRC_RANESGM, id);
2665
2666 value = (arg->weig_bilat & 0x1f) | (arg->weig_maxl & 0x1f) << 8 |
2667 (arg->bilat_soft_thd & 0x3fff) << 16;
2668 if (arg->enable_soft_thd)
2669 value |= BIT(31);
2670 isp3_param_write(params_vdev, value, ISP3X_DRC_BILAT, id);
2671
2672 for (i = 0; i < ISP3X_DRC_Y_NUM / 2; i++) {
2673 value = ISP_PACK_2SHORT(arg->gain_y[2 * i],
2674 arg->gain_y[2 * i + 1]);
2675 isp3_param_write(params_vdev, value, ISP3X_DRC_GAIN_Y0 + 4 * i, id);
2676 }
2677 value = ISP_PACK_2SHORT(arg->gain_y[2 * i], 0);
2678 isp3_param_write(params_vdev, value, ISP3X_DRC_GAIN_Y0 + 4 * i, id);
2679
2680 for (i = 0; i < ISP3X_DRC_Y_NUM / 2; i++) {
2681 value = ISP_PACK_2SHORT(arg->compres_y[2 * i],
2682 arg->compres_y[2 * i + 1]);
2683 isp3_param_write(params_vdev, value, ISP3X_DRC_COMPRES_Y0 + 4 * i, id);
2684 }
2685 value = ISP_PACK_2SHORT(arg->compres_y[2 * i], 0);
2686 isp3_param_write(params_vdev, value, ISP3X_DRC_COMPRES_Y0 + 4 * i, id);
2687
2688 for (i = 0; i < ISP3X_DRC_Y_NUM / 2; i++) {
2689 value = ISP_PACK_2SHORT(arg->scale_y[2 * i],
2690 arg->scale_y[2 * i + 1]);
2691 isp3_param_write(params_vdev, value, ISP3X_DRC_SCALE_Y0 + 4 * i, id);
2692 }
2693 value = ISP_PACK_2SHORT(arg->scale_y[2 * i], 0);
2694 isp3_param_write(params_vdev, value, ISP3X_DRC_SCALE_Y0 + 4 * i, id);
2695
2696 value = ISP_PACK_2SHORT(arg->min_ogain, arg->iir_weight);
2697 isp3_param_write(params_vdev, value, ISP3X_DRC_IIRWG_GAIN, id);
2698 }
2699
2700 static void
isp_hdrdrc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)2701 isp_hdrdrc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
2702 {
2703 u32 value;
2704 bool real_en;
2705
2706 value = isp3_param_read(params_vdev, ISP3X_DRC_CTRL0, id);
2707 real_en = !!(value & ISP3X_MODULE_EN);
2708 if ((en && real_en) || (!en && !real_en))
2709 return;
2710
2711 if (en) {
2712 value |= ISP3X_MODULE_EN;
2713 isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1,
2714 ISP3X_ADRC_FST_FRAME, id);
2715 } else {
2716 value = 0;
2717 isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(12), id);
2718 }
2719 isp3_param_write(params_vdev, value, ISP3X_DRC_CTRL0, id);
2720 }
2721
2722 static void
isp_gic_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_gic_cfg * arg,u32 id)2723 isp_gic_config(struct rkisp_isp_params_vdev *params_vdev,
2724 const struct isp21_gic_cfg *arg, u32 id)
2725 {
2726 u32 value;
2727 s32 i;
2728
2729 value = (arg->regmingradthrdark2 & 0x03FF) << 20 |
2730 (arg->regmingradthrdark1 & 0x03FF) << 10 |
2731 (arg->regminbusythre & 0x03FF);
2732 isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA1, id);
2733
2734 value = (arg->regdarkthre & 0x07FF) << 21 |
2735 (arg->regmaxcorvboth & 0x03FF) << 11 |
2736 (arg->regdarktthrehi & 0x07FF);
2737 isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA2, id);
2738
2739 value = (arg->regkgrad2dark & 0x0F) << 28 |
2740 (arg->regkgrad1dark & 0x0F) << 24 |
2741 (arg->regstrengthglobal_fix & 0xFF) << 16 |
2742 (arg->regdarkthrestep & 0x0F) << 12 |
2743 (arg->regkgrad2 & 0x0F) << 8 |
2744 (arg->regkgrad1 & 0x0F) << 4 |
2745 (arg->reggbthre & 0x0F);
2746 isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA3, id);
2747
2748 value = (arg->regmaxcorv & 0x03FF) << 20 |
2749 (arg->regmingradthr2 & 0x03FF) << 10 |
2750 (arg->regmingradthr1 & 0x03FF);
2751 isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA4, id);
2752
2753 value = (arg->gr_ratio & 0x03) << 28 |
2754 (arg->noise_scale & 0x7F) << 12 |
2755 (arg->noise_base & 0xFFF);
2756 isp3_param_write(params_vdev, value, ISP3X_GIC_NOISE_PARA1, id);
2757
2758 isp3_param_write(params_vdev, arg->diff_clip, ISP3X_GIC_NOISE_PARA2, id);
2759
2760 for (i = 0; i < ISP3X_GIC_SIGMA_Y_NUM / 2; i++) {
2761 value = ISP_PACK_2SHORT(arg->sigma_y[2 * i], arg->sigma_y[2 * i + 1]);
2762 isp3_param_write(params_vdev, value, ISP3X_GIC_SIGMA_VALUE0 + 4 * i, id);
2763 }
2764 value = ISP_PACK_2SHORT(arg->sigma_y[2 * i], 0);
2765 isp3_param_write(params_vdev, value, ISP3X_GIC_SIGMA_VALUE0 + 4 * i, id);
2766 }
2767
2768 static void
isp_gic_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)2769 isp_gic_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
2770 {
2771 u32 value = 0;
2772
2773 if (en)
2774 value |= ISP3X_MODULE_EN;
2775 isp3_param_write(params_vdev, value, ISP3X_GIC_CONTROL, id);
2776 }
2777
2778 static void
isp_dhaz_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_dhaz_cfg * arg,u32 id)2779 isp_dhaz_config(struct rkisp_isp_params_vdev *params_vdev,
2780 const struct isp3x_dhaz_cfg *arg, u32 id)
2781 {
2782 struct rkisp_device *dev = params_vdev->dev;
2783 u32 i, value, ctrl;
2784
2785 ctrl = isp3_param_read(params_vdev, ISP3X_DHAZ_CTRL, id);
2786 ctrl &= ISP3X_DHAZ_ENMUX;
2787
2788 ctrl |= (arg->enhance_en & 0x1) << 20 |
2789 (arg->air_lc_en & 0x1) << 16 |
2790 (arg->hpara_en & 0x1) << 12 |
2791 (arg->hist_en & 0x1) << 8 |
2792 (arg->dc_en & 0x1) << 4 |
2793 (arg->round_en & 0x1) << 26;
2794 if (arg->soft_wr_en)
2795 ctrl |= (arg->soft_wr_en & 0x1) << 25;
2796 /* merge dual unite isp params at frame end */
2797 if (arg->soft_wr_en) {
2798 value = ISP_PACK_2SHORT(arg->adp_wt_wr, arg->adp_air_wr);
2799 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADT_WR0, id);
2800 value = ISP_PACK_2SHORT(arg->adp_tmax_wr, arg->adp_gratio_wr);
2801 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADT_WR1, id);
2802 for (i = 0; i < ISP3X_DHAZ_HIST_WR_NUM / 3; i++) {
2803 value = (arg->hist_wr[i * 3] & 0x3ff) |
2804 (arg->hist_wr[i * 3 + 1] & 0x3ff) << 10 |
2805 (arg->hist_wr[i * 3 + 2] & 0x3ff) << 20;
2806 isp3_param_write(params_vdev, value, ISP3X_DHAZ_HIST_WR0 + i * 4, id);
2807 }
2808 value = arg->hist_wr[i * 3] & 0x3ff;
2809 isp3_param_write(params_vdev, value, ISP3X_DHAZ_HIST_WR0 + i * 4, id);
2810 }
2811
2812 value = ISP_PACK_4BYTE(arg->dc_min_th, arg->dc_max_th,
2813 arg->yhist_th, arg->yblk_th);
2814 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP0, id);
2815
2816 value = ISP_PACK_4BYTE(arg->bright_min, arg->bright_max,
2817 arg->wt_max, 0);
2818 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP1, id);
2819
2820 value = ISP_PACK_4BYTE(arg->air_min, arg->air_max,
2821 arg->dark_th, arg->tmax_base);
2822 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP2, id);
2823
2824 value = ISP_PACK_2SHORT(arg->tmax_off, arg->tmax_max);
2825 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP_TMAX, id);
2826
2827 value = (arg->hist_min & 0xFFFF) << 16 |
2828 (arg->hist_th_off & 0xFF) << 8 |
2829 (arg->hist_k & 0x1F);
2830 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP_HIST0, id);
2831
2832 value = ISP_PACK_2SHORT(arg->hist_scale, arg->hist_gratio);
2833 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP_HIST1, id);
2834
2835 value = ISP_PACK_2SHORT(arg->enhance_chroma, arg->enhance_value);
2836 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ENHANCE, id);
2837
2838 value = (arg->iir_wt_sigma & 0x07FF) << 16 |
2839 (arg->iir_sigma & 0xFF) << 8 |
2840 (arg->stab_fnum & 0x1F);
2841 isp3_param_write(params_vdev, value, ISP3X_DHAZ_IIR0, id);
2842
2843 value = (arg->iir_pre_wet & 0x0F) << 24 |
2844 (arg->iir_tmax_sigma & 0x7FF) << 8 |
2845 (arg->iir_air_sigma & 0xFF);
2846 isp3_param_write(params_vdev, value, ISP3X_DHAZ_IIR1, id);
2847
2848 value = (arg->cfg_wt & 0x01FF) << 16 |
2849 (arg->cfg_air & 0xFF) << 8 |
2850 (arg->cfg_alpha & 0xFF);
2851 isp3_param_write(params_vdev, value, ISP3X_DHAZ_SOFT_CFG0, id);
2852
2853 value = ISP_PACK_2SHORT(arg->cfg_tmax, arg->cfg_gratio);
2854 isp3_param_write(params_vdev, value, ISP3X_DHAZ_SOFT_CFG1, id);
2855
2856 value = (arg->range_sima & 0x01FF) << 16 |
2857 (arg->space_sigma_pre & 0xFF) << 8 |
2858 (arg->space_sigma_cur & 0xFF);
2859 isp3_param_write(params_vdev, value, ISP3X_DHAZ_BF_SIGMA, id);
2860
2861 value = ISP_PACK_2SHORT(arg->bf_weight, arg->dc_weitcur);
2862 isp3_param_write(params_vdev, value, ISP3X_DHAZ_BF_WET, id);
2863
2864 for (i = 0; i < ISP3X_DHAZ_ENH_CURVE_NUM / 2; i++) {
2865 value = ISP_PACK_2SHORT(arg->enh_curve[2 * i], arg->enh_curve[2 * i + 1]);
2866 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ENH_CURVE0 + 4 * i, id);
2867 }
2868 value = ISP_PACK_2SHORT(arg->enh_curve[2 * i], 0);
2869 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ENH_CURVE0 + 4 * i, id);
2870
2871 value = ISP_PACK_4BYTE(arg->gaus_h0, arg->gaus_h1, arg->gaus_h2, 0);
2872 isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAUS, id);
2873
2874 for (i = 0; i < ISP3X_DHAZ_SIGMA_IDX_NUM / 4; i++) {
2875 value = ISP_PACK_4BYTE(arg->sigma_idx[i * 4], arg->sigma_idx[i * 4 + 1],
2876 arg->sigma_idx[i * 4 + 2], arg->sigma_idx[i * 4 + 3]);
2877 isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_IDX0 + i * 4, id);
2878 }
2879 value = ISP_PACK_4BYTE(arg->sigma_idx[i * 4], arg->sigma_idx[i * 4 + 1],
2880 arg->sigma_idx[i * 4 + 2], 0);
2881 isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_IDX0 + i * 4, id);
2882
2883 for (i = 0; i < ISP3X_DHAZ_SIGMA_LUT_NUM / 2; i++) {
2884 value = ISP_PACK_2SHORT(arg->sigma_lut[i * 2], arg->sigma_lut[i * 2 + 1]);
2885 isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_LUT0 + i * 4, id);
2886 }
2887 value = ISP_PACK_2SHORT(arg->sigma_lut[i * 2], 0);
2888 isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_LUT0 + i * 4, id);
2889
2890 if (dev->hw_dev->is_unite &&
2891 dev->hw_dev->is_single &&
2892 ctrl & ISP3X_DHAZ_ENMUX)
2893 ctrl |= ISP3X_SELF_FORCE_UPD;
2894 isp3_param_write(params_vdev, ctrl, ISP3X_DHAZ_CTRL, id);
2895 }
2896
2897 static void
isp_dhaz_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)2898 isp_dhaz_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
2899 {
2900 u32 value;
2901 bool real_en;
2902
2903 value = isp3_param_read(params_vdev, ISP3X_DHAZ_CTRL, id);
2904 real_en = !!(value & ISP3X_DHAZ_ENMUX);
2905 if ((en && real_en) || (!en && !real_en))
2906 return;
2907
2908 if (en) {
2909 value |= ISP3X_SELF_FORCE_UPD | ISP3X_DHAZ_ENMUX;
2910 isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1,
2911 ISP3X_DHAZ_FST_FRAME, id);
2912 } else {
2913 value &= ~ISP3X_DHAZ_ENMUX;
2914 isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(16), id);
2915 }
2916 isp3_param_write(params_vdev, value, ISP3X_DHAZ_CTRL, id);
2917 }
2918
2919 static void
isp_3dlut_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_3dlut_cfg * arg,u32 id)2920 isp_3dlut_config(struct rkisp_isp_params_vdev *params_vdev,
2921 const struct isp2x_3dlut_cfg *arg, u32 id)
2922 {
2923 struct rkisp_device *dev = params_vdev->dev;
2924 struct rkisp_isp_params_val_v3x *priv_val;
2925 u32 value, buf_idx, i;
2926 u32 *data;
2927
2928 priv_val = (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
2929 buf_idx = (priv_val->buf_3dlut_idx[id]++) % ISP3X_3DLUT_BUF_NUM;
2930
2931 if (!priv_val->buf_3dlut[id][buf_idx].vaddr) {
2932 dev_err(dev->dev, "no find 3dlut buf\n");
2933 return;
2934 }
2935 data = (u32 *)priv_val->buf_3dlut[id][buf_idx].vaddr;
2936 for (i = 0; i < arg->actual_size; i++)
2937 data[i] = (arg->lut_b[i] & 0x3FF) |
2938 (arg->lut_g[i] & 0xFFF) << 10 |
2939 (arg->lut_r[i] & 0x3FF) << 22;
2940 rkisp_prepare_buffer(params_vdev->dev, &priv_val->buf_3dlut[id][buf_idx]);
2941 value = priv_val->buf_3dlut[id][buf_idx].dma_addr;
2942 isp3_param_write(params_vdev, value, ISP3X_MI_LUT_3D_RD_BASE, id);
2943 isp3_param_write(params_vdev, arg->actual_size, ISP3X_MI_LUT_3D_RD_WSIZE, id);
2944
2945 value = isp3_param_read(params_vdev, ISP3X_3DLUT_CTRL, id);
2946 value &= ISP3X_3DLUT_EN;
2947
2948 if (value)
2949 isp3_param_set_bits(params_vdev, ISP3X_3DLUT_UPDATE, 0x01, id);
2950
2951 isp3_param_write(params_vdev, value, ISP3X_3DLUT_CTRL, id);
2952 }
2953
2954 static void
isp_3dlut_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)2955 isp_3dlut_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
2956 {
2957 u32 value;
2958 bool en_state;
2959 struct rkisp_isp_params_val_v3x *priv_val;
2960
2961 value = isp3_param_read(params_vdev, ISP3X_3DLUT_CTRL, id);
2962 en_state = (value & ISP3X_3DLUT_EN) ? true : false;
2963
2964 if (en == en_state)
2965 return;
2966
2967 priv_val = (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
2968 if (en && priv_val->buf_3dlut[id][0].vaddr) {
2969 isp3_param_set_bits(params_vdev, ISP3X_3DLUT_CTRL, 0x01, id);
2970 isp3_param_set_bits(params_vdev, ISP3X_3DLUT_UPDATE, 0x01, id);
2971 } else {
2972 isp3_param_clear_bits(params_vdev, ISP3X_3DLUT_CTRL, 0x01, id);
2973 isp3_param_clear_bits(params_vdev, ISP3X_3DLUT_UPDATE, 0x01, id);
2974 isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(20), id);
2975 }
2976 }
2977
2978 static void
isp_ldch_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_ldch_cfg * arg,u32 id)2979 isp_ldch_config(struct rkisp_isp_params_vdev *params_vdev,
2980 const struct isp2x_ldch_cfg *arg, u32 id)
2981 {
2982 struct rkisp_device *dev = params_vdev->dev;
2983 struct rkisp_isp_params_val_v3x *priv_val;
2984 struct isp2x_mesh_head *head;
2985 int buf_idx, i;
2986 u32 value;
2987
2988 priv_val = (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
2989 for (i = 0; i < ISP3X_MESH_BUF_NUM; i++) {
2990 if (!priv_val->buf_ldch[id][i].mem_priv)
2991 continue;
2992 if (arg->buf_fd == priv_val->buf_ldch[id][i].dma_fd)
2993 break;
2994 }
2995 if (i == ISP3X_MESH_BUF_NUM) {
2996 dev_err(dev->dev, "cannot find ldch buf fd(%d)\n", arg->buf_fd);
2997 return;
2998 }
2999
3000 if (!priv_val->buf_ldch[id][i].vaddr) {
3001 dev_err(dev->dev, "no ldch buffer allocated\n");
3002 return;
3003 }
3004
3005 buf_idx = priv_val->buf_ldch_idx[id];
3006 head = (struct isp2x_mesh_head *)priv_val->buf_ldch[id][buf_idx].vaddr;
3007 head->stat = MESH_BUF_INIT;
3008
3009 buf_idx = i;
3010 head = (struct isp2x_mesh_head *)priv_val->buf_ldch[id][buf_idx].vaddr;
3011 head->stat = MESH_BUF_CHIPINUSE;
3012 priv_val->buf_ldch_idx[id] = buf_idx;
3013 rkisp_prepare_buffer(dev, &priv_val->buf_ldch[id][buf_idx]);
3014 value = priv_val->buf_ldch[id][buf_idx].dma_addr + head->data_oft;
3015 isp3_param_write(params_vdev, value, ISP3X_MI_LUT_LDCH_RD_BASE, id);
3016 isp3_param_write(params_vdev, arg->hsize, ISP3X_MI_LUT_LDCH_RD_H_WSIZE, id);
3017 isp3_param_write(params_vdev, arg->vsize, ISP3X_MI_LUT_LDCH_RD_V_SIZE, id);
3018 }
3019
3020 static void
isp_ldch_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)3021 isp_ldch_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
3022 {
3023 struct rkisp_device *dev = params_vdev->dev;
3024 struct rkisp_isp_params_val_v3x *priv_val;
3025 u32 buf_idx;
3026
3027 priv_val = (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
3028 if (en) {
3029 buf_idx = priv_val->buf_ldch_idx[id];
3030 if (!priv_val->buf_ldch[id][buf_idx].vaddr) {
3031 dev_err(dev->dev, "no ldch buffer allocated\n");
3032 return;
3033 }
3034 isp3_param_set_bits(params_vdev, ISP3X_LDCH_STS, 0x01, id);
3035 } else {
3036 isp3_param_clear_bits(params_vdev, ISP3X_LDCH_STS, 0x01, id);
3037 }
3038 }
3039
3040 static void
isp_ynr_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_ynr_cfg * arg,u32 id)3041 isp_ynr_config(struct rkisp_isp_params_vdev *params_vdev,
3042 const struct isp3x_ynr_cfg *arg, u32 id)
3043 {
3044 u32 i, value;
3045
3046 value = isp3_param_read(params_vdev, ISP3X_YNR_GLOBAL_CTRL, id);
3047 value &= ISP3X_MODULE_EN;
3048
3049 value |= (arg->rnr_en & 0x1) << 26 |
3050 (arg->thumb_mix_cur_en & 0x1) << 24 |
3051 (arg->global_gain_alpha & 0xF) << 20 |
3052 (arg->global_gain & 0x3FF) << 8 |
3053 (arg->flt1x1_bypass_sel & 0x3) << 6 |
3054 (arg->sft5x5_bypass & 0x1) << 5 |
3055 (arg->flt1x1_bypass & 0x1) << 4 |
3056 (arg->lgft3x3_bypass & 0x1) << 3 |
3057 (arg->lbft5x5_bypass & 0x1) << 2 |
3058 (arg->bft3x3_bypass & 0x1) << 1;
3059 isp3_param_write(params_vdev, value, ISP3X_YNR_GLOBAL_CTRL, id);
3060
3061 value = ISP_PACK_2SHORT(arg->rnr_max_r, arg->local_gainscale);
3062 isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_MAX_R, id);
3063
3064 value = ISP_PACK_2SHORT(arg->rnr_center_coorh, arg->rnr_center_coorv);
3065 isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_CENTER_COOR, id);
3066
3067 value = ISP_PACK_2SHORT(arg->loclagain_adj_thresh, arg->localgain_adj);
3068 isp3_param_write(params_vdev, value, ISP3X_YNR_LOCAL_GAIN_CTRL, id);
3069
3070 value = ISP_PACK_2SHORT(arg->low_bf_inv0, arg->low_bf_inv1);
3071 isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL0, id);
3072
3073 value = ISP_PACK_2SHORT(arg->low_thred_adj, arg->low_peak_supress);
3074 isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL1, id);
3075
3076 value = ISP_PACK_2SHORT(arg->low_edge_adj_thresh, arg->low_dist_adj);
3077 isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL2, id);
3078
3079 value = (arg->low_bi_weight & 0xFF) << 24 |
3080 (arg->low_weight & 0xFF) << 16 |
3081 (arg->low_center_weight & 0xFFFF);
3082 isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL3, id);
3083
3084 value = ISP_PACK_2SHORT(arg->high_thred_adj, arg->hi_min_adj);
3085 isp3_param_write(params_vdev, value, ISP3X_YNR_HIGHNR_CTRL0, id);
3086
3087 value = ISP_PACK_2SHORT(arg->hi_edge_thed, arg->high_retain_weight);
3088 isp3_param_write(params_vdev, value, ISP3X_YNR_HIGHNR_CTRL1, id);
3089
3090 value = ISP_PACK_4BYTE(arg->base_filter_weight0,
3091 arg->base_filter_weight1,
3092 arg->base_filter_weight2,
3093 0);
3094 isp3_param_write(params_vdev, value, ISP3X_YNR_HIGHNR_BASE_FILTER_WEIGHT, id);
3095
3096 value = ISP_PACK_2SHORT(arg->lbf_weight_thres, arg->frame_full_size);
3097 isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL4, id);
3098
3099 value = (arg->low_gauss1_coeff2 & 0xFFFF) << 16 |
3100 (arg->low_gauss1_coeff1 & 0xFF) << 8 |
3101 (arg->low_gauss1_coeff0 & 0xFF);
3102 isp3_param_write(params_vdev, value, ISP3X_YNR_GAUSS1_COEFF, id);
3103
3104 value = (arg->low_gauss2_coeff2 & 0xFFFF) << 16 |
3105 (arg->low_gauss2_coeff1 & 0xFF) << 8 |
3106 (arg->low_gauss2_coeff0 & 0xFF);
3107 isp3_param_write(params_vdev, value, ISP3X_YNR_GAUSS2_COEFF, id);
3108
3109 value = ISP_PACK_4BYTE(arg->direction_weight0,
3110 arg->direction_weight1,
3111 arg->direction_weight2,
3112 arg->direction_weight3);
3113 isp3_param_write(params_vdev, value, ISP3X_YNR_DIRECTION_W_0_3, id);
3114
3115 value = ISP_PACK_4BYTE(arg->direction_weight4,
3116 arg->direction_weight5,
3117 arg->direction_weight6,
3118 arg->direction_weight7);
3119 isp3_param_write(params_vdev, value, ISP3X_YNR_DIRECTION_W_4_7, id);
3120
3121 for (i = 0; i < ISP3X_YNR_XY_NUM / 2; i++) {
3122 value = ISP_PACK_2SHORT(arg->luma_points_x[2 * i],
3123 arg->luma_points_x[2 * i + 1]);
3124 isp3_param_write(params_vdev, value, ISP3X_YNR_SGM_DX_0_1 + 4 * i, id);
3125 }
3126 value = ISP_PACK_2SHORT(arg->luma_points_x[2 * i], 0);
3127 isp3_param_write(params_vdev, value, ISP3X_YNR_SGM_DX_0_1 + 4 * i, id);
3128
3129 for (i = 0; i < ISP3X_YNR_XY_NUM / 2; i++) {
3130 value = ISP_PACK_2SHORT(arg->lsgm_y[2 * i],
3131 arg->lsgm_y[2 * i + 1]);
3132 isp3_param_write(params_vdev, value, ISP3X_YNR_LSGM_Y_0_1 + 4 * i, id);
3133 }
3134 value = ISP_PACK_2SHORT(arg->lsgm_y[2 * i], 0);
3135 isp3_param_write(params_vdev, value, ISP3X_YNR_LSGM_Y_0_1 + 4 * i, id);
3136
3137 for (i = 0; i < ISP3X_YNR_XY_NUM / 2; i++) {
3138 value = ISP_PACK_2SHORT(arg->hsgm_y[2 * i],
3139 arg->hsgm_y[2 * i + 1]);
3140 isp3_param_write(params_vdev, value, ISP3X_YNR_HSGM_Y_0_1 + 4 * i, id);
3141 }
3142 value = ISP_PACK_2SHORT(arg->hsgm_y[2 * i], 0);
3143 isp3_param_write(params_vdev, value, ISP3X_YNR_HSGM_Y_0_1 + 4 * i, id);
3144
3145 for (i = 0; i < ISP3X_YNR_XY_NUM / 4; i++) {
3146 value = ISP_PACK_4BYTE(arg->rnr_strength3[4 * i],
3147 arg->rnr_strength3[4 * i + 1],
3148 arg->rnr_strength3[4 * i + 2],
3149 arg->rnr_strength3[4 * i + 3]);
3150 isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_STRENGTH03 + 4 * i, id);
3151 }
3152 value = ISP_PACK_4BYTE(arg->rnr_strength3[4 * i], 0, 0, 0);
3153 isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_STRENGTH03 + 4 * i, id);
3154 }
3155
3156 static void
isp_ynr_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)3157 isp_ynr_enable(struct rkisp_isp_params_vdev *params_vdev,
3158 bool en, u32 id)
3159 {
3160 u32 ynr_ctrl;
3161 bool real_en;
3162
3163 ynr_ctrl = isp3_param_read_cache(params_vdev, ISP3X_YNR_GLOBAL_CTRL, id);
3164 real_en = !!(ynr_ctrl & ISP3X_MODULE_EN);
3165 if ((en && real_en) || (!en && !real_en))
3166 return;
3167
3168 if (en) {
3169 ynr_ctrl |= ISP3X_MODULE_EN;
3170 isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1,
3171 ISP3X_YNR_FST_FRAME, id);
3172 } else {
3173 ynr_ctrl &= ~ISP3X_MODULE_EN;
3174 }
3175
3176 isp3_param_write(params_vdev, ynr_ctrl, ISP3X_YNR_GLOBAL_CTRL, id);
3177 }
3178
3179 static void
isp_cnr_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_cnr_cfg * arg,u32 id)3180 isp_cnr_config(struct rkisp_isp_params_vdev *params_vdev,
3181 const struct isp3x_cnr_cfg *arg, u32 id)
3182 {
3183 u32 i, value, ctrl, gain_ctrl;
3184
3185 gain_ctrl = isp3_param_read(params_vdev, ISP3X_GAIN_CTRL, id);
3186 ctrl = isp3_param_read(params_vdev, ISP3X_CNR_CTRL, id);
3187 ctrl &= ISP3X_MODULE_EN;
3188
3189 ctrl |= (arg->thumb_mix_cur_en & 0x1) << 4 |
3190 (arg->lq_bila_bypass & 0x1) << 3 |
3191 (arg->hq_bila_bypass & 0x1) << 2 |
3192 (arg->exgain_bypass & 0x1) << 1;
3193 value = (arg->global_gain & 0x3ff) |
3194 (arg->global_gain_alpha & 0xf) << 12;
3195 /* gain disable, using global gain for cnr */
3196 if (ctrl & ISP3X_MODULE_EN && !(gain_ctrl & ISP3X_MODULE_EN)) {
3197 ctrl |= BIT(1);
3198 value &= 0x3ff;
3199 value |= 0x8000;
3200 }
3201 isp3_param_write(params_vdev, ctrl, ISP3X_CNR_CTRL, id);
3202 isp3_param_write(params_vdev, value, ISP3X_CNR_EXGAIN, id);
3203
3204 value = ISP_PACK_4BYTE(arg->gain_1sigma, arg->gain_offset,
3205 arg->gain_iso, 0);
3206 isp3_param_write(params_vdev, value, ISP3X_CNR_GAIN_PARA, id);
3207
3208 value = ISP_PACK_4BYTE(arg->gain_uvgain0, arg->gain_uvgain1, 0, 0);
3209 isp3_param_write(params_vdev, value, ISP3X_CNR_GAIN_UV_PARA, id);
3210
3211 isp3_param_write(params_vdev, arg->lmed3_alpha, ISP3X_CNR_LMED3, id);
3212
3213 value = ISP_PACK_4BYTE(arg->lbf5_gain_c, arg->lbf5_gain_y, 0, 0);
3214 isp3_param_write(params_vdev, value, ISP3X_CNR_LBF5_GAIN, id);
3215
3216 value = ISP_PACK_4BYTE(arg->lbf5_weit_d0, arg->lbf5_weit_d1,
3217 arg->lbf5_weit_d2, arg->lbf5_weit_d3);
3218 isp3_param_write(params_vdev, value, ISP3X_CNR_LBF5_WEITD0_3, id);
3219
3220 isp3_param_write(params_vdev, arg->lbf5_weit_d4, ISP3X_CNR_LBF5_WEITD4, id);
3221
3222 isp3_param_write(params_vdev, arg->hmed3_alpha, ISP3X_CNR_HMED3, id);
3223
3224 value = (arg->hbf5_weit_src & 0xFF) << 24 |
3225 (arg->hbf5_min_wgt & 0xFF) << 16 |
3226 (arg->hbf5_sigma & 0xFFFF);
3227 isp3_param_write(params_vdev, value, ISP3X_CNR_HBF5, id);
3228
3229 value = ISP_PACK_2SHORT(arg->lbf3_sigma, arg->lbf5_weit_src);
3230 isp3_param_write(params_vdev, value, ISP3X_CNR_LBF3, id);
3231
3232 for (i = 0; i < ISP3X_CNR_SIGMA_Y_NUM / 4; i++) {
3233 value = ISP_PACK_4BYTE(arg->sigma_y[i * 4], arg->sigma_y[i * 4 + 1],
3234 arg->sigma_y[i * 4 + 2], arg->sigma_y[i * 4 + 3]);
3235 isp3_param_write(params_vdev, value, ISP3X_CNR_SIGMA0 + i * 4, id);
3236 }
3237 value = arg->sigma_y[i * 4];
3238 isp3_param_write(params_vdev, value, ISP3X_CNR_SIGMA0 + i * 4, id);
3239 }
3240
3241 static void
isp_cnr_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)3242 isp_cnr_enable(struct rkisp_isp_params_vdev *params_vdev,
3243 bool en, u32 id)
3244 {
3245 u32 cnr_ctrl;
3246 bool real_en;
3247
3248 cnr_ctrl = isp3_param_read_cache(params_vdev, ISP3X_CNR_CTRL, id);
3249 real_en = !!(cnr_ctrl & ISP3X_MODULE_EN);
3250 if ((en && real_en) || (!en && !real_en))
3251 return;
3252
3253 if (en) {
3254 cnr_ctrl |= ISP3X_MODULE_EN;
3255 isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1,
3256 ISP3X_CNR_FST_FRAME, id);
3257 } else {
3258 cnr_ctrl &= ~ISP3X_MODULE_EN;
3259 }
3260
3261 isp3_param_write(params_vdev, cnr_ctrl, ISP3X_CNR_CTRL, id);
3262 }
3263
3264 static void
isp_sharp_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_sharp_cfg * arg,u32 id)3265 isp_sharp_config(struct rkisp_isp_params_vdev *params_vdev,
3266 const struct isp3x_sharp_cfg *arg, u32 id)
3267 {
3268 u32 value;
3269
3270 value = isp3_param_read(params_vdev, ISP3X_SHARP_EN, id);
3271 value &= ISP3X_MODULE_EN;
3272
3273 value |= (arg->bypass & 0x1) << 1 |
3274 (arg->center_mode & 0x1) << 2 |
3275 (arg->exgain_bypass & 0x1) << 3;
3276 isp3_param_write(params_vdev, value, ISP3X_SHARP_EN, id);
3277
3278 value = ISP_PACK_4BYTE(arg->pbf_ratio, arg->gaus_ratio,
3279 arg->bf_ratio, arg->sharp_ratio);
3280 isp3_param_write(params_vdev, value, ISP3X_SHARP_RATIO, id);
3281
3282 value = (arg->luma_dx[6] & 0x0F) << 24 |
3283 (arg->luma_dx[5] & 0x0F) << 20 |
3284 (arg->luma_dx[4] & 0x0F) << 16 |
3285 (arg->luma_dx[3] & 0x0F) << 12 |
3286 (arg->luma_dx[2] & 0x0F) << 8 |
3287 (arg->luma_dx[1] & 0x0F) << 4 |
3288 (arg->luma_dx[0] & 0x0F);
3289 isp3_param_write(params_vdev, value, ISP3X_SHARP_LUMA_DX, id);
3290
3291 value = (arg->pbf_sigma_inv[2] & 0x3FF) << 20 |
3292 (arg->pbf_sigma_inv[1] & 0x3FF) << 10 |
3293 (arg->pbf_sigma_inv[0] & 0x3FF);
3294 isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_SIGMA_INV_0, id);
3295
3296 value = (arg->pbf_sigma_inv[5] & 0x3FF) << 20 |
3297 (arg->pbf_sigma_inv[4] & 0x3FF) << 10 |
3298 (arg->pbf_sigma_inv[3] & 0x3FF);
3299 isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_SIGMA_INV_1, id);
3300
3301 value = (arg->pbf_sigma_inv[7] & 0x3FF) << 10 |
3302 (arg->pbf_sigma_inv[6] & 0x3FF);
3303 isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_SIGMA_INV_2, id);
3304
3305 value = (arg->bf_sigma_inv[2] & 0x3FF) << 20 |
3306 (arg->bf_sigma_inv[1] & 0x3FF) << 10 |
3307 (arg->bf_sigma_inv[0] & 0x3FF);
3308 isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_SIGMA_INV_0, id);
3309
3310 value = (arg->bf_sigma_inv[5] & 0x3FF) << 20 |
3311 (arg->bf_sigma_inv[4] & 0x3FF) << 10 |
3312 (arg->bf_sigma_inv[3] & 0x3FF);
3313 isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_SIGMA_INV_1, id);
3314
3315 value = (arg->bf_sigma_inv[7] & 0x3FF) << 10 |
3316 (arg->bf_sigma_inv[6] & 0x3FF);
3317 isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_SIGMA_INV_2, id);
3318
3319 value = (arg->bf_sigma_shift & 0x0F) << 4 |
3320 (arg->pbf_sigma_shift & 0x0F);
3321 isp3_param_write(params_vdev, value, ISP3X_SHARP_SIGMA_SHIFT, id);
3322
3323 value = (arg->ehf_th[2] & 0x3FF) << 20 |
3324 (arg->ehf_th[1] & 0x3FF) << 10 |
3325 (arg->ehf_th[0] & 0x3FF);
3326 isp3_param_write(params_vdev, value, ISP3X_SHARP_EHF_TH_0, id);
3327
3328 value = (arg->ehf_th[5] & 0x3FF) << 20 |
3329 (arg->ehf_th[4] & 0x3FF) << 10 |
3330 (arg->ehf_th[3] & 0x3FF);
3331 isp3_param_write(params_vdev, value, ISP3X_SHARP_EHF_TH_1, id);
3332
3333 value = (arg->ehf_th[7] & 0x3FF) << 10 |
3334 (arg->ehf_th[6] & 0x3FF);
3335 isp3_param_write(params_vdev, value, ISP3X_SHARP_EHF_TH_2, id);
3336
3337 value = (arg->clip_hf[2] & 0x3FF) << 20 |
3338 (arg->clip_hf[1] & 0x3FF) << 10 |
3339 (arg->clip_hf[0] & 0x3FF);
3340 isp3_param_write(params_vdev, value, ISP3X_SHARP_CLIP_HF_0, id);
3341
3342 value = (arg->clip_hf[5] & 0x3FF) << 20 |
3343 (arg->clip_hf[4] & 0x3FF) << 10 |
3344 (arg->clip_hf[3] & 0x3FF);
3345 isp3_param_write(params_vdev, value, ISP3X_SHARP_CLIP_HF_1, id);
3346
3347 value = (arg->clip_hf[7] & 0x3FF) << 10 |
3348 (arg->clip_hf[6] & 0x3FF);
3349 isp3_param_write(params_vdev, value, ISP3X_SHARP_CLIP_HF_2, id);
3350
3351 value = ISP_PACK_4BYTE(arg->pbf_coef0, arg->pbf_coef1, arg->pbf_coef2, 0);
3352 isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_COEF, id);
3353
3354 value = ISP_PACK_4BYTE(arg->bf_coef0, arg->bf_coef1, arg->bf_coef2, 0);
3355 isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_COEF, id);
3356
3357 value = ISP_PACK_4BYTE(arg->gaus_coef[0], arg->gaus_coef[1], arg->gaus_coef[2], 0);
3358 isp3_param_write(params_vdev, value, ISP3X_SHARP_GAUS_COEF0, id);
3359
3360 value = ISP_PACK_4BYTE(arg->gaus_coef[3], arg->gaus_coef[4], arg->gaus_coef[5], 0);
3361 isp3_param_write(params_vdev, value, ISP3X_SHARP_GAUS_COEF1, id);
3362 }
3363
3364 static void
isp_sharp_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)3365 isp_sharp_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
3366 {
3367 u32 value;
3368
3369 value = isp3_param_read_cache(params_vdev, ISP3X_SHARP_EN, id);
3370 value &= ~ISP3X_MODULE_EN;
3371
3372 if (en)
3373 value |= ISP3X_MODULE_EN;
3374
3375 isp3_param_write(params_vdev, value, ISP3X_SHARP_EN, id);
3376 }
3377
3378 static void
isp_baynr_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_baynr_cfg * arg,u32 id)3379 isp_baynr_config(struct rkisp_isp_params_vdev *params_vdev,
3380 const struct isp3x_baynr_cfg *arg, u32 id)
3381 {
3382 u32 i, value;
3383
3384 value = isp3_param_read(params_vdev, ISP3X_BAYNR_CTRL, id);
3385 value &= ISP3X_MODULE_EN;
3386
3387 value |= (arg->lg2_mode & 0x3) << 12 |
3388 (arg->gauss_en & 0x1) << 8 |
3389 (arg->log_bypass & 0x1) << 4;
3390 isp3_param_write(params_vdev, value, ISP3X_BAYNR_CTRL, id);
3391
3392 value = ISP_PACK_2SHORT(arg->dgain0, arg->dgain1);
3393 isp3_param_write(params_vdev, value, ISP3X_BAYNR_DGAIN0, id);
3394
3395 isp3_param_write(params_vdev, arg->dgain2, ISP3X_BAYNR_DGAIN1, id);
3396 isp3_param_write(params_vdev, arg->pix_diff, ISP3X_BAYNR_PIXDIFF, id);
3397
3398 value = ISP_PACK_2SHORT(arg->softthld, arg->diff_thld);
3399 isp3_param_write(params_vdev, value, ISP3X_BAYNR_THLD, id);
3400
3401 value = ISP_PACK_2SHORT(arg->reg_w1, arg->bltflt_streng);
3402 isp3_param_write(params_vdev, value, ISP3X_BAYNR_W1_STRENG, id);
3403
3404 for (i = 0; i < ISP3X_BAYNR_XY_NUM / 2; i++) {
3405 value = ISP_PACK_2SHORT(arg->sigma_x[2 * i], arg->sigma_x[2 * i + 1]);
3406 isp3_param_write(params_vdev, value, ISP3X_BAYNR_SIGMAX01 + 4 * i, id);
3407 }
3408
3409 for (i = 0; i < ISP3X_BAYNR_XY_NUM / 2; i++) {
3410 value = ISP_PACK_2SHORT(arg->sigma_y[2 * i], arg->sigma_y[2 * i + 1]);
3411 isp3_param_write(params_vdev, value, ISP3X_BAYNR_SIGMAY01 + 4 * i, id);
3412 }
3413
3414 value = (arg->weit_d2 & 0x3FF) << 20 |
3415 (arg->weit_d1 & 0x3FF) << 10 |
3416 (arg->weit_d0 & 0x3FF);
3417 isp3_param_write(params_vdev, value, ISP3X_BAYNR_WRIT_D, id);
3418
3419 value = ISP_PACK_2SHORT(arg->lg2_off, arg->lg2_lgoff);
3420 isp3_param_write(params_vdev, value, ISP3X_BAYNR_LG_OFF, id);
3421
3422 value = arg->dat_max & 0xfffff;
3423 isp3_param_write(params_vdev, value, ISP3X_BAYNR_DAT_MAX, id);
3424 }
3425
3426 static void
isp_baynr_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)3427 isp_baynr_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
3428 {
3429 u32 value;
3430
3431 value = isp3_param_read_cache(params_vdev, ISP3X_BAYNR_CTRL, id);
3432 value &= ~ISP3X_MODULE_EN;
3433
3434 if (en)
3435 value |= ISP3X_MODULE_EN;
3436
3437 isp3_param_write(params_vdev, value, ISP3X_BAYNR_CTRL, id);
3438 }
3439
3440 static void
isp_bay3d_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_bay3d_cfg * arg,u32 id)3441 isp_bay3d_config(struct rkisp_isp_params_vdev *params_vdev,
3442 const struct isp3x_bay3d_cfg *arg, u32 id)
3443 {
3444 struct rkisp_device *dev = params_vdev->dev;
3445 u32 i, value;
3446
3447 value = isp3_param_read(params_vdev, ISP3X_BAY3D_CTRL, id);
3448 value &= ISP3X_MODULE_EN;
3449
3450 if (dev->rd_mode == HDR_NORMAL ||
3451 dev->rd_mode == HDR_RDBK_FRAME1)
3452 value |= BIT(13); //bandwidth save
3453 value |= (arg->loswitch_protect & 0x1) << 12 |
3454 (arg->glbpk_en & 0x1) << 11 |
3455 (arg->logaus3_bypass_en & 0x1) << 10 |
3456 (arg->logaus5_bypass_en & 0x1) << 9 |
3457 (arg->lomed_bypass_en & 0x1) << 8 |
3458 (arg->hichnsplit_en & 0x1) << 7 |
3459 (arg->hiabs_possel & 0x1) << 6 |
3460 (arg->higaus_bypass_en & 0x1) << 5 |
3461 (arg->himed_bypass_en & 0x1) << 4 |
3462 (arg->lobypass_en & 0x1) << 3 |
3463 (arg->hibypass_en & 0x1) << 2 |
3464 (arg->bypass_en & 0x1) << 1;
3465 isp3_param_write(params_vdev, value, ISP3X_BAY3D_CTRL, id);
3466
3467 value = ISP_PACK_2SHORT(arg->softwgt, arg->hidif_th);
3468 isp3_param_write(params_vdev, value, ISP3X_BAY3D_KALRATIO, id);
3469
3470 isp3_param_write(params_vdev, arg->glbpk2, ISP3X_BAY3D_GLBPK2, id);
3471
3472 value = ISP_PACK_2SHORT(arg->wgtlmt, arg->wgtratio);
3473 isp3_param_write(params_vdev, value, ISP3X_BAY3D_WGTLMT, id);
3474
3475 for (i = 0; i < ISP3X_BAY3D_XY_NUM / 2; i++) {
3476 value = ISP_PACK_2SHORT(arg->sig0_x[2 * i],
3477 arg->sig0_x[2 * i + 1]);
3478 isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG0_X0 + 4 * i, id);
3479
3480 value = ISP_PACK_2SHORT(arg->sig1_x[2 * i],
3481 arg->sig1_x[2 * i + 1]);
3482 isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG1_X0 + 4 * i, id);
3483 }
3484
3485 for (i = 0; i < ISP3X_BAY3D_XY_NUM / 2; i++) {
3486 value = ISP_PACK_2SHORT(arg->sig0_y[2 * i],
3487 arg->sig0_y[2 * i + 1]);
3488 isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG0_Y0 + 4 * i, id);
3489
3490 value = ISP_PACK_2SHORT(arg->sig1_y[2 * i],
3491 arg->sig1_y[2 * i + 1]);
3492 isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG1_Y0 + 4 * i, id);
3493
3494 value = ISP_PACK_2SHORT(arg->sig2_y[2 * i],
3495 arg->sig2_y[2 * i + 1]);
3496 isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG2_Y0 + 4 * i, id);
3497 }
3498 }
3499
3500 static void
isp_bay3d_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)3501 isp_bay3d_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
3502 {
3503 struct rkisp_device *ispdev = params_vdev->dev;
3504 struct rkisp_isp_params_val_v3x *priv_val;
3505 u32 value, bay3d_ctrl;
3506
3507 priv_val = (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
3508 bay3d_ctrl = isp3_param_read_cache(params_vdev, ISP3X_BAY3D_CTRL, id);
3509 if ((en && (bay3d_ctrl & ISP3X_MODULE_EN)) ||
3510 (!en && !(bay3d_ctrl & ISP3X_MODULE_EN)))
3511 return;
3512
3513 if (en) {
3514 if (!priv_val->buf_3dnr_iir[id].mem_priv) {
3515 dev_err(ispdev->dev, "no bay3d buffer available\n");
3516 return;
3517 }
3518
3519 value = priv_val->buf_3dnr_iir[id].size;
3520 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_WR_SIZE, id);
3521 value = priv_val->buf_3dnr_iir[id].dma_addr;
3522 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_WR_BASE, id);
3523 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_RD_BASE, id);
3524
3525 value = priv_val->buf_3dnr_cur[id].size;
3526 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_WR_SIZE, id);
3527 value = priv_val->buf_3dnr_cur[id].dma_addr;
3528 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_WR_BASE, id);
3529 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_RD_BASE, id);
3530
3531 value = priv_val->buf_3dnr_ds[id].size;
3532 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_DS_WR_SIZE, id);
3533 value = priv_val->buf_3dnr_ds[id].dma_addr;
3534 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_DS_WR_BASE, id);
3535 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_DS_RD_BASE, id);
3536
3537 bay3d_ctrl |= ISP3X_MODULE_EN;
3538 isp3_param_write(params_vdev, bay3d_ctrl, ISP3X_BAY3D_CTRL, id);
3539
3540 value = ISP3X_BAY3D_IIR_WR_AUTO_UPD | ISP3X_BAY3D_CUR_WR_AUTO_UPD |
3541 ISP3X_BAY3D_DS_WR_AUTO_UPD | ISP3X_BAY3D_IIRSELF_UPD |
3542 ISP3X_BAY3D_CURSELF_UPD | ISP3X_BAY3D_DSSELF_UPD |
3543 ISP3X_BAY3D_RDSELF_UPD;
3544 isp3_param_set_bits(params_vdev, MI_WR_CTRL2, value, id);
3545
3546 isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1, ISP3X_RAW3D_FST_FRAME, id);
3547 } else {
3548 bay3d_ctrl &= ~ISP3X_MODULE_EN;
3549 isp3_param_write(params_vdev, bay3d_ctrl, ISP3X_BAY3D_CTRL, id);
3550 isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(4), id);
3551 }
3552 }
3553
3554 static void
isp_gain_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_gain_cfg * arg,u32 id)3555 isp_gain_config(struct rkisp_isp_params_vdev *params_vdev,
3556 const struct isp3x_gain_cfg *arg, u32 id)
3557 {
3558 u32 val;
3559
3560 val = arg->g0 & 0x3ffff;
3561 isp3_param_write(params_vdev, val, ISP3X_GAIN_G0, id);
3562 val = ISP_PACK_2SHORT(arg->g1, arg->g2);
3563 isp3_param_write(params_vdev, val, ISP3X_GAIN_G1_G2, id);
3564 }
3565
3566 static void
isp_gain_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)3567 isp_gain_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
3568 {
3569 struct rkisp_isp_params_val_v3x *priv_val =
3570 (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
3571 u32 val = isp3_param_read_cache(params_vdev, ISP3X_LDCH_STS, id);
3572
3573 /* gain will affect ldch, no support for ldch and gain enable */
3574 if (val & ISP3X_MODULE_EN && en)
3575 return;
3576
3577 val = 0;
3578 if (en) {
3579 val |= priv_val->lut3d_en << 20 |
3580 priv_val->dhaz_en << 16 |
3581 priv_val->drc_en << 12 |
3582 priv_val->lsc_en << 8 |
3583 priv_val->bay3d_en << 4;
3584 if (isp3_param_read(params_vdev, ISP3X_HDRMGE_CTRL, id) & BIT(0))
3585 val |= BIT(1);
3586 if (val)
3587 val |= ISP3X_MODULE_EN;
3588 }
3589 isp3_param_write(params_vdev, val, ISP3X_GAIN_CTRL, id);
3590 }
3591
3592 static void
isp_cac_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_cac_cfg * arg,u32 id)3593 isp_cac_config(struct rkisp_isp_params_vdev *params_vdev,
3594 const struct isp3x_cac_cfg *arg, u32 id)
3595 {
3596 struct rkisp_device *dev = params_vdev->dev;
3597 struct rkisp_isp_params_val_v3x *priv_val;
3598 struct isp2x_mesh_head *head;
3599 u32 i, val, ctrl;
3600
3601 priv_val = (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
3602
3603 ctrl = isp3_param_read(params_vdev, ISP3X_CAC_CTRL, id);
3604 ctrl &= ISP3X_CAC_EN;
3605 ctrl |= (arg->bypass_en & 0x1) << 1 | (arg->center_en & 0x1) << 3;
3606
3607 val = (arg->psf_sft_bit & 0xff) |
3608 (arg->cfg_num & 0x7ff) << 8;
3609 isp3_param_write(params_vdev, val, ISP3X_CAC_PSF_PARA, id);
3610
3611 val = ISP_PACK_2SHORT(arg->center_width, arg->center_height);
3612 isp3_param_write(params_vdev, val, ISP3X_CAC_STRENGTH_CENTER, id);
3613
3614 for (i = 0; i < ISP3X_CAC_STRENGTH_NUM / 2; i++) {
3615 val = ISP_PACK_2SHORT(arg->strength[2 * i], arg->strength[2 * i + 1]);
3616 isp3_param_write(params_vdev, val, ISP3X_CAC_STRENGTH0 + i * 4, id);
3617 }
3618
3619 for (i = 0; i < ISP3X_MESH_BUF_NUM; i++) {
3620 if (!priv_val->buf_cac[id][i].mem_priv)
3621 continue;
3622 if (arg->buf_fd == priv_val->buf_cac[id][i].dma_fd)
3623 break;
3624 }
3625
3626 if (i == ISP3X_MESH_BUF_NUM) {
3627 dev_err(dev->dev, "cannot find cac buf fd(%d)\n", arg->buf_fd);
3628 return;
3629 }
3630
3631 if (!priv_val->buf_cac[id][i].vaddr) {
3632 dev_err(dev->dev, "no cac buffer allocated\n");
3633 return;
3634 }
3635
3636 val = priv_val->buf_cac_idx[id];
3637 head = (struct isp2x_mesh_head *)priv_val->buf_cac[id][val].vaddr;
3638 head->stat = MESH_BUF_INIT;
3639
3640 head = (struct isp2x_mesh_head *)priv_val->buf_cac[id][i].vaddr;
3641 head->stat = MESH_BUF_CHIPINUSE;
3642 priv_val->buf_cac_idx[id] = i;
3643 rkisp_prepare_buffer(dev, &priv_val->buf_cac[id][i]);
3644 val = priv_val->buf_cac[id][i].dma_addr + head->data_oft;
3645 isp3_param_write(params_vdev, val, ISP3X_MI_LUT_CAC_RD_BASE, id);
3646 isp3_param_write(params_vdev, arg->hsize, ISP3X_MI_LUT_CAC_RD_H_WSIZE, id);
3647 isp3_param_write(params_vdev, arg->vsize, ISP3X_MI_LUT_CAC_RD_V_SIZE, id);
3648 if (ctrl & ISP3X_CAC_EN)
3649 ctrl |= ISP3X_CAC_LUT_EN;
3650 isp3_param_write(params_vdev, ctrl, ISP3X_CAC_CTRL, id);
3651 }
3652
3653 static void
isp_cac_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)3654 isp_cac_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
3655 {
3656 u32 val;
3657
3658 val = isp3_param_read(params_vdev, ISP3X_CAC_CTRL, id);
3659 val &= ~ISP3X_CAC_EN;
3660 if (en)
3661 val |= ISP3X_CAC_EN | ISP3X_CAC_LUT_EN;
3662 isp3_param_write(params_vdev, val, ISP3X_CAC_CTRL, id);
3663 }
3664
3665 static void
isp_csm_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_csm_cfg * arg,u32 id)3666 isp_csm_config(struct rkisp_isp_params_vdev *params_vdev,
3667 const struct isp21_csm_cfg *arg, u32 id)
3668 {
3669 u32 i, val;
3670
3671 for (i = 0; i < ISP3X_CSM_COEFF_NUM; i++) {
3672 if (i == 0)
3673 val = (arg->csm_y_offset & 0x3f) << 24 |
3674 (arg->csm_c_offset & 0xff) << 16 |
3675 (arg->csm_coeff[i] & 0x1ff);
3676 else
3677 val = arg->csm_coeff[i] & 0x1ff;
3678 isp3_param_write(params_vdev, val, ISP3X_ISP_CC_COEFF_0 + i * 4, id);
3679 }
3680
3681 val = CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA | CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA;
3682 isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL0, val, id);
3683 }
3684
3685 static void
isp_cgc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_cgc_cfg * arg,u32 id)3686 isp_cgc_config(struct rkisp_isp_params_vdev *params_vdev,
3687 const struct isp21_cgc_cfg *arg, u32 id)
3688 {
3689 u32 val = isp3_param_read(params_vdev, ISP3X_ISP_CTRL0, id);
3690 u32 eff_ctrl, cproc_ctrl;
3691
3692 params_vdev->quantization = V4L2_QUANTIZATION_FULL_RANGE;
3693 val &= ~(ISP3X_SW_CGC_YUV_LIMIT | ISP3X_SW_CGC_RATIO_EN);
3694 if (arg->yuv_limit) {
3695 params_vdev->quantization = V4L2_QUANTIZATION_LIM_RANGE;
3696 }
3697 if (arg->ratio_en)
3698 val |= ISP3X_SW_CGC_RATIO_EN;
3699 isp3_param_write(params_vdev, val, ISP3X_ISP_CTRL0, id);
3700
3701 /* cproc limit replace cgc limit config */
3702 cproc_ctrl = isp3_param_read(params_vdev, ISP3X_CPROC_CTRL, id);
3703 if (arg->yuv_limit) {
3704 cproc_ctrl = CIF_C_PROC_CTR_ENABLE | CIF_C_PROC_YIN_FULL;
3705 } else {
3706 cproc_ctrl |= CIF_C_PROC_YOUT_FULL | CIF_C_PROC_YIN_FULL | CIF_C_PROC_COUT_FULL;
3707 }
3708 isp3_param_write(params_vdev, cproc_ctrl, ISP3X_CPROC_CTRL, id);
3709
3710 eff_ctrl = isp3_param_read(params_vdev, ISP3X_IMG_EFF_CTRL, id);
3711 if (eff_ctrl & CIF_IMG_EFF_CTRL_ENABLE) {
3712 if (arg->yuv_limit)
3713 eff_ctrl &= ~CIF_IMG_EFF_CTRL_YCBCR_FULL;
3714 else
3715 eff_ctrl |= CIF_IMG_EFF_CTRL_YCBCR_FULL;
3716 isp3_param_write(params_vdev, eff_ctrl, ISP3X_IMG_EFF_CTRL, id);
3717 }
3718 }
3719
3720 struct rkisp_isp_params_ops_v3x isp_params_ops_v3x = {
3721 .dpcc_config = isp_dpcc_config,
3722 .dpcc_enable = isp_dpcc_enable,
3723 .bls_config = isp_bls_config,
3724 .bls_enable = isp_bls_enable,
3725 .sdg_config = isp_sdg_config,
3726 .sdg_enable = isp_sdg_enable,
3727 .lsc_config = isp_lsc_config,
3728 .lsc_enable = isp_lsc_enable,
3729 .awbgain_config = isp_awbgain_config,
3730 .awbgain_enable = isp_awbgain_enable,
3731 .debayer_config = isp_debayer_config,
3732 .debayer_enable = isp_debayer_enable,
3733 .ccm_config = isp_ccm_config,
3734 .ccm_enable = isp_ccm_enable,
3735 .goc_config = isp_goc_config,
3736 .goc_enable = isp_goc_enable,
3737 .csm_config = isp_csm_config,
3738 .cproc_config = isp_cproc_config,
3739 .cproc_enable = isp_cproc_enable,
3740 .ie_config = isp_ie_config,
3741 .ie_enable = isp_ie_enable,
3742 .rawaf_config = isp_rawaf_config,
3743 .rawaf_enable = isp_rawaf_enable,
3744 .rawae0_config = isp_rawaelite_config,
3745 .rawae0_enable = isp_rawaelite_enable,
3746 .rawae1_config = isp_rawae1_config,
3747 .rawae1_enable = isp_rawae1_enable,
3748 .rawae2_config = isp_rawae2_config,
3749 .rawae2_enable = isp_rawae2_enable,
3750 .rawae3_config = isp_rawae3_config,
3751 .rawae3_enable = isp_rawae3_enable,
3752 .rawawb_config = isp_rawawb_config,
3753 .rawawb_enable = isp_rawawb_enable,
3754 .rawhst0_config = isp_rawhstlite_config,
3755 .rawhst0_enable = isp_rawhstlite_enable,
3756 .rawhst1_config = isp_rawhst1_config,
3757 .rawhst1_enable = isp_rawhst1_enable,
3758 .rawhst2_config = isp_rawhst2_config,
3759 .rawhst2_enable = isp_rawhst2_enable,
3760 .rawhst3_config = isp_rawhst3_config,
3761 .rawhst3_enable = isp_rawhst3_enable,
3762 .hdrmge_config = isp_hdrmge_config,
3763 .hdrmge_enable = isp_hdrmge_enable,
3764 .hdrdrc_config = isp_hdrdrc_config,
3765 .hdrdrc_enable = isp_hdrdrc_enable,
3766 .gic_config = isp_gic_config,
3767 .gic_enable = isp_gic_enable,
3768 .dhaz_config = isp_dhaz_config,
3769 .dhaz_enable = isp_dhaz_enable,
3770 .isp3dlut_config = isp_3dlut_config,
3771 .isp3dlut_enable = isp_3dlut_enable,
3772 .ldch_config = isp_ldch_config,
3773 .ldch_enable = isp_ldch_enable,
3774 .ynr_config = isp_ynr_config,
3775 .ynr_enable = isp_ynr_enable,
3776 .cnr_config = isp_cnr_config,
3777 .cnr_enable = isp_cnr_enable,
3778 .sharp_config = isp_sharp_config,
3779 .sharp_enable = isp_sharp_enable,
3780 .baynr_config = isp_baynr_config,
3781 .baynr_enable = isp_baynr_enable,
3782 .bay3d_config = isp_bay3d_config,
3783 .bay3d_enable = isp_bay3d_enable,
3784 .gain_config = isp_gain_config,
3785 .gain_enable = isp_gain_enable,
3786 .cac_config = isp_cac_config,
3787 .cac_enable = isp_cac_enable,
3788 .cgc_config = isp_cgc_config,
3789 };
3790
3791 static __maybe_unused
__isp_isr_other_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_isp_params_cfg * new_params,enum rkisp_params_type type,enum isp3x_unite_id id)3792 void __isp_isr_other_config(struct rkisp_isp_params_vdev *params_vdev,
3793 const struct isp3x_isp_params_cfg *new_params,
3794 enum rkisp_params_type type, enum isp3x_unite_id id)
3795 {
3796 struct rkisp_isp_params_ops_v3x *ops =
3797 (struct rkisp_isp_params_ops_v3x *)params_vdev->priv_ops;
3798 u64 module_cfg_update = new_params->module_cfg_update;
3799
3800 if (type == RKISP_PARAMS_SHD) {
3801 if ((module_cfg_update & ISP3X_MODULE_HDRMGE))
3802 ops->hdrmge_config(params_vdev, &new_params->others.hdrmge_cfg, type, id);
3803
3804 if ((module_cfg_update & ISP3X_MODULE_DRC))
3805 ops->hdrdrc_config(params_vdev, &new_params->others.drc_cfg, type, id);
3806 return;
3807 }
3808
3809 v4l2_dbg(4, rkisp_debug, ¶ms_vdev->dev->v4l2_dev,
3810 "%s id:%d seq:%d module_cfg_update:0x%llx\n",
3811 __func__, id, new_params->frame_id, module_cfg_update);
3812
3813 if ((module_cfg_update & ISP3X_MODULE_LSC))
3814 ops->lsc_config(params_vdev, &new_params->others.lsc_cfg, id);
3815
3816 if ((module_cfg_update & ISP3X_MODULE_DPCC))
3817 ops->dpcc_config(params_vdev, &new_params->others.dpcc_cfg, id);
3818
3819 if ((module_cfg_update & ISP3X_MODULE_BLS))
3820 ops->bls_config(params_vdev, &new_params->others.bls_cfg, id);
3821
3822 if ((module_cfg_update & ISP3X_MODULE_SDG))
3823 ops->sdg_config(params_vdev, &new_params->others.sdg_cfg, id);
3824
3825 if ((module_cfg_update & ISP3X_MODULE_AWB_GAIN))
3826 ops->awbgain_config(params_vdev, &new_params->others.awb_gain_cfg, id);
3827
3828 if ((module_cfg_update & ISP3X_MODULE_DEBAYER))
3829 ops->debayer_config(params_vdev, &new_params->others.debayer_cfg, id);
3830
3831 if ((module_cfg_update & ISP3X_MODULE_CCM))
3832 ops->ccm_config(params_vdev, &new_params->others.ccm_cfg, id);
3833
3834 if ((module_cfg_update & ISP3X_MODULE_GOC))
3835 ops->goc_config(params_vdev, &new_params->others.gammaout_cfg, id);
3836
3837 /* range csm->cgc->cproc->ie */
3838 if ((module_cfg_update & ISP3X_MODULE_CSM))
3839 ops->csm_config(params_vdev, &new_params->others.csm_cfg, id);
3840
3841 if ((module_cfg_update & ISP3X_MODULE_CGC))
3842 ops->cgc_config(params_vdev, &new_params->others.cgc_cfg, id);
3843
3844 if ((module_cfg_update & ISP3X_MODULE_CPROC))
3845 ops->cproc_config(params_vdev, &new_params->others.cproc_cfg, id);
3846
3847 if ((module_cfg_update & ISP3X_MODULE_IE))
3848 ops->ie_config(params_vdev, &new_params->others.ie_cfg, id);
3849
3850 if ((module_cfg_update & ISP3X_MODULE_HDRMGE))
3851 ops->hdrmge_config(params_vdev, &new_params->others.hdrmge_cfg, type, id);
3852
3853 if ((module_cfg_update & ISP3X_MODULE_DRC))
3854 ops->hdrdrc_config(params_vdev, &new_params->others.drc_cfg, type, id);
3855
3856 if ((module_cfg_update & ISP3X_MODULE_GIC))
3857 ops->gic_config(params_vdev, &new_params->others.gic_cfg, id);
3858
3859 if ((module_cfg_update & ISP3X_MODULE_DHAZ))
3860 ops->dhaz_config(params_vdev, &new_params->others.dhaz_cfg, id);
3861
3862 if ((module_cfg_update & ISP3X_MODULE_3DLUT))
3863 ops->isp3dlut_config(params_vdev, &new_params->others.isp3dlut_cfg, id);
3864
3865 if ((module_cfg_update & ISP3X_MODULE_LDCH))
3866 ops->ldch_config(params_vdev, &new_params->others.ldch_cfg, id);
3867
3868 if ((module_cfg_update & ISP3X_MODULE_YNR))
3869 ops->ynr_config(params_vdev, &new_params->others.ynr_cfg, id);
3870
3871 if ((module_cfg_update & ISP3X_MODULE_CNR))
3872 ops->cnr_config(params_vdev, &new_params->others.cnr_cfg, id);
3873
3874 if ((module_cfg_update & ISP3X_MODULE_SHARP))
3875 ops->sharp_config(params_vdev, &new_params->others.sharp_cfg, id);
3876
3877 if ((module_cfg_update & ISP3X_MODULE_BAYNR))
3878 ops->baynr_config(params_vdev, &new_params->others.baynr_cfg, id);
3879
3880 if ((module_cfg_update & ISP3X_MODULE_BAY3D))
3881 ops->bay3d_config(params_vdev, &new_params->others.bay3d_cfg, id);
3882
3883 if ((module_cfg_update & ISP3X_MODULE_CAC))
3884 ops->cac_config(params_vdev, &new_params->others.cac_cfg, id);
3885
3886 if ((module_cfg_update & ISP3X_MODULE_GAIN))
3887 ops->gain_config(params_vdev, &new_params->others.gain_cfg, id);
3888 }
3889
3890 static __maybe_unused
__isp_isr_other_en(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_isp_params_cfg * new_params,enum rkisp_params_type type,enum isp3x_unite_id id)3891 void __isp_isr_other_en(struct rkisp_isp_params_vdev *params_vdev,
3892 const struct isp3x_isp_params_cfg *new_params,
3893 enum rkisp_params_type type, enum isp3x_unite_id id)
3894 {
3895 struct rkisp_isp_params_ops_v3x *ops =
3896 (struct rkisp_isp_params_ops_v3x *)params_vdev->priv_ops;
3897 struct rkisp_isp_params_val_v3x *priv_val =
3898 (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
3899 u64 module_en_update = new_params->module_en_update;
3900 u64 module_ens = new_params->module_ens;
3901 u32 gain_ctrl, cnr_ctrl, val;
3902
3903 if (type == RKISP_PARAMS_SHD)
3904 return;
3905
3906 v4l2_dbg(4, rkisp_debug, ¶ms_vdev->dev->v4l2_dev,
3907 "%s id:%d seq:%d module_en_update:0x%llx module_ens:0x%llx\n",
3908 __func__, id, new_params->frame_id, module_en_update, module_ens);
3909
3910 if (module_en_update & ISP3X_MODULE_DPCC)
3911 ops->dpcc_enable(params_vdev, !!(module_ens & ISP3X_MODULE_DPCC), id);
3912
3913 if (module_en_update & ISP3X_MODULE_BLS)
3914 ops->bls_enable(params_vdev, !!(module_ens & ISP3X_MODULE_BLS), id);
3915
3916 if (module_en_update & ISP3X_MODULE_SDG)
3917 ops->sdg_enable(params_vdev, !!(module_ens & ISP3X_MODULE_SDG), id);
3918
3919 if (module_en_update & ISP3X_MODULE_LSC) {
3920 ops->lsc_enable(params_vdev, !!(module_ens & ISP3X_MODULE_LSC), id);
3921 priv_val->lsc_en = !!(module_ens & ISP3X_MODULE_LSC);
3922 }
3923
3924 if (module_en_update & ISP3X_MODULE_AWB_GAIN)
3925 ops->awbgain_enable(params_vdev, !!(module_ens & ISP3X_MODULE_AWB_GAIN), id);
3926
3927 if (module_en_update & ISP3X_MODULE_DEBAYER)
3928 ops->debayer_enable(params_vdev, !!(module_ens & ISP3X_MODULE_DEBAYER), id);
3929
3930 if (module_en_update & ISP3X_MODULE_CCM)
3931 ops->ccm_enable(params_vdev, !!(module_ens & ISP3X_MODULE_CCM), id);
3932
3933 if (module_en_update & ISP3X_MODULE_GOC)
3934 ops->goc_enable(params_vdev, !!(module_ens & ISP3X_MODULE_GOC), id);
3935
3936 if (module_en_update & ISP3X_MODULE_CPROC)
3937 ops->cproc_enable(params_vdev, !!(module_ens & ISP3X_MODULE_CPROC), id);
3938
3939 if (module_en_update & ISP3X_MODULE_IE)
3940 ops->ie_enable(params_vdev, !!(module_ens & ISP3X_MODULE_IE), id);
3941
3942 if (module_en_update & ISP3X_MODULE_HDRMGE) {
3943 ops->hdrmge_enable(params_vdev, !!(module_ens & ISP3X_MODULE_HDRMGE), id);
3944 priv_val->mge_en = !!(module_ens & ISP3X_MODULE_HDRMGE);
3945 }
3946
3947 if (module_en_update & ISP3X_MODULE_DRC) {
3948 ops->hdrdrc_enable(params_vdev, !!(module_ens & ISP3X_MODULE_DRC), id);
3949 priv_val->drc_en = !!(module_ens & ISP3X_MODULE_DRC);
3950 }
3951
3952 if (module_en_update & ISP3X_MODULE_GIC)
3953 ops->gic_enable(params_vdev, !!(module_ens & ISP3X_MODULE_GIC), id);
3954
3955 if (module_en_update & ISP3X_MODULE_DHAZ) {
3956 ops->dhaz_enable(params_vdev, !!(module_ens & ISP3X_MODULE_DHAZ), id);
3957 priv_val->dhaz_en = !!(module_ens & ISP3X_MODULE_DHAZ);
3958 }
3959
3960 if (module_en_update & ISP3X_MODULE_3DLUT) {
3961 ops->isp3dlut_enable(params_vdev, !!(module_ens & ISP3X_MODULE_3DLUT), id);
3962 priv_val->lut3d_en = !!(module_ens & ISP3X_MODULE_3DLUT);
3963 }
3964
3965 if (module_en_update & ISP3X_MODULE_LDCH)
3966 ops->ldch_enable(params_vdev, !!(module_ens & ISP3X_MODULE_LDCH), id);
3967
3968 if (module_en_update & ISP3X_MODULE_YNR)
3969 ops->ynr_enable(params_vdev, !!(module_ens & ISP3X_MODULE_YNR), id);
3970
3971 if (module_en_update & ISP3X_MODULE_CNR)
3972 ops->cnr_enable(params_vdev, !!(module_ens & ISP3X_MODULE_CNR), id);
3973
3974 if (module_en_update & ISP3X_MODULE_SHARP)
3975 ops->sharp_enable(params_vdev, !!(module_ens & ISP3X_MODULE_SHARP), id);
3976
3977 if (module_en_update & ISP3X_MODULE_BAYNR)
3978 ops->baynr_enable(params_vdev, !!(module_ens & ISP3X_MODULE_BAYNR), id);
3979
3980 if (module_en_update & ISP3X_MODULE_BAY3D) {
3981 ops->bay3d_enable(params_vdev, !!(module_ens & ISP3X_MODULE_BAY3D), id);
3982 priv_val->bay3d_en = !!(module_ens & ISP3X_MODULE_BAY3D);
3983 }
3984
3985 if (module_en_update & ISP3X_MODULE_CAC)
3986 ops->cac_enable(params_vdev, !!(module_ens & ISP3X_MODULE_CAC), id);
3987
3988 if (module_en_update & ISP3X_MODULE_GAIN)
3989 ops->gain_enable(params_vdev, !!(module_ens & ISP3X_MODULE_GAIN), id);
3990
3991 /* gain disable, using global gain for cnr */
3992 gain_ctrl = isp3_param_read_cache(params_vdev, ISP3X_GAIN_CTRL, id);
3993 cnr_ctrl = isp3_param_read_cache(params_vdev, ISP3X_CNR_CTRL, id);
3994 if (!(gain_ctrl & ISP3X_MODULE_EN) && cnr_ctrl & ISP3X_MODULE_EN) {
3995 cnr_ctrl |= BIT(1);
3996 isp3_param_write(params_vdev, cnr_ctrl, ISP3X_CNR_CTRL, id);
3997 val = isp3_param_read(params_vdev, ISP3X_CNR_EXGAIN, id) & 0x3ff;
3998 isp3_param_write(params_vdev, val | 0x8000, ISP3X_CNR_EXGAIN, id);
3999 }
4000 }
4001
4002 static __maybe_unused
__isp_isr_meas_config(struct rkisp_isp_params_vdev * params_vdev,struct isp3x_isp_params_cfg * new_params,enum rkisp_params_type type,enum isp3x_unite_id id)4003 void __isp_isr_meas_config(struct rkisp_isp_params_vdev *params_vdev,
4004 struct isp3x_isp_params_cfg *new_params,
4005 enum rkisp_params_type type, enum isp3x_unite_id id)
4006 {
4007 struct rkisp_isp_params_ops_v3x *ops =
4008 (struct rkisp_isp_params_ops_v3x *)params_vdev->priv_ops;
4009 u64 module_cfg_update = new_params->module_cfg_update;
4010
4011 params_vdev->cur_frame_id = new_params->frame_id;
4012 if (type == RKISP_PARAMS_SHD)
4013 return;
4014
4015 v4l2_dbg(4, rkisp_debug, ¶ms_vdev->dev->v4l2_dev,
4016 "%s id:%d seq:%d module_cfg_update:0x%llx\n",
4017 __func__, id, new_params->frame_id, module_cfg_update);
4018
4019 if ((module_cfg_update & ISP3X_MODULE_RAWAF))
4020 ops->rawaf_config(params_vdev, &new_params->meas.rawaf, id);
4021
4022 if ((module_cfg_update & ISP3X_MODULE_RAWAE0))
4023 ops->rawae0_config(params_vdev, &new_params->meas.rawae0, id);
4024
4025 if ((module_cfg_update & ISP3X_MODULE_RAWAE1))
4026 ops->rawae1_config(params_vdev, &new_params->meas.rawae1, id);
4027
4028 if ((module_cfg_update & ISP3X_MODULE_RAWAE2))
4029 ops->rawae2_config(params_vdev, &new_params->meas.rawae2, id);
4030
4031 if ((module_cfg_update & ISP3X_MODULE_RAWAE3) && !params_vdev->afaemode_en)
4032 ops->rawae3_config(params_vdev, &new_params->meas.rawae3, id);
4033
4034 if ((module_cfg_update & ISP3X_MODULE_RAWHIST0))
4035 ops->rawhst0_config(params_vdev, &new_params->meas.rawhist0, id);
4036
4037 if ((module_cfg_update & ISP3X_MODULE_RAWHIST1))
4038 ops->rawhst1_config(params_vdev, &new_params->meas.rawhist1, id);
4039
4040 if ((module_cfg_update & ISP3X_MODULE_RAWHIST2))
4041 ops->rawhst2_config(params_vdev, &new_params->meas.rawhist2, id);
4042
4043 if ((module_cfg_update & ISP3X_MODULE_RAWHIST3))
4044 ops->rawhst3_config(params_vdev, &new_params->meas.rawhist3, id);
4045
4046 if ((module_cfg_update & ISP3X_MODULE_RAWAWB))
4047 ops->rawawb_config(params_vdev, &new_params->meas.rawawb, id);
4048 }
4049
4050 static __maybe_unused
__isp_isr_meas_en(struct rkisp_isp_params_vdev * params_vdev,struct isp3x_isp_params_cfg * new_params,enum rkisp_params_type type,enum isp3x_unite_id id)4051 void __isp_isr_meas_en(struct rkisp_isp_params_vdev *params_vdev,
4052 struct isp3x_isp_params_cfg *new_params,
4053 enum rkisp_params_type type, enum isp3x_unite_id id)
4054 {
4055 struct rkisp_isp_params_ops_v3x *ops =
4056 (struct rkisp_isp_params_ops_v3x *)params_vdev->priv_ops;
4057 u64 module_en_update = new_params->module_en_update;
4058 u64 module_ens = new_params->module_ens;
4059
4060 if (type == RKISP_PARAMS_SHD)
4061 return;
4062
4063 v4l2_dbg(4, rkisp_debug, ¶ms_vdev->dev->v4l2_dev,
4064 "%s id:%d seq:%d module_en_update:0x%llx module_ens:0x%llx\n",
4065 __func__, id, new_params->frame_id, module_en_update, module_ens);
4066
4067 if (module_en_update & ISP3X_MODULE_RAWAF)
4068 ops->rawaf_enable(params_vdev, !!(module_ens & ISP3X_MODULE_RAWAF), id);
4069
4070 if (module_en_update & ISP3X_MODULE_RAWAE0)
4071 ops->rawae0_enable(params_vdev, !!(module_ens & ISP3X_MODULE_RAWAE0), id);
4072
4073 if (module_en_update & ISP3X_MODULE_RAWAE1)
4074 ops->rawae1_enable(params_vdev, !!(module_ens & ISP3X_MODULE_RAWAE1), id);
4075
4076 if (module_en_update & ISP3X_MODULE_RAWAE2)
4077 ops->rawae2_enable(params_vdev, !!(module_ens & ISP3X_MODULE_RAWAE2), id);
4078
4079 if ((module_en_update & ISP3X_MODULE_RAWAE3) && !params_vdev->afaemode_en)
4080 ops->rawae3_enable(params_vdev, !!(module_ens & ISP3X_MODULE_RAWAE3), id);
4081
4082 if (module_en_update & ISP3X_MODULE_RAWHIST0)
4083 ops->rawhst0_enable(params_vdev, !!(module_ens & ISP3X_MODULE_RAWHIST0), id);
4084
4085 if (module_en_update & ISP3X_MODULE_RAWHIST1)
4086 ops->rawhst1_enable(params_vdev, !!(module_ens & ISP3X_MODULE_RAWHIST1), id);
4087
4088 if (module_en_update & ISP3X_MODULE_RAWHIST2)
4089 ops->rawhst2_enable(params_vdev, !!(module_ens & ISP3X_MODULE_RAWHIST2), id);
4090
4091 if (module_en_update & ISP3X_MODULE_RAWHIST3)
4092 ops->rawhst3_enable(params_vdev, !!(module_ens & ISP3X_MODULE_RAWHIST3), id);
4093
4094 if (module_en_update & ISP3X_MODULE_RAWAWB)
4095 ops->rawawb_enable(params_vdev, !!(module_ens & ISP3X_MODULE_RAWAWB), id);
4096 }
4097
4098 static __maybe_unused
__isp_config_hdrshd(struct rkisp_isp_params_vdev * params_vdev)4099 void __isp_config_hdrshd(struct rkisp_isp_params_vdev *params_vdev)
4100 {
4101 struct rkisp_isp_params_ops_v3x *ops =
4102 (struct rkisp_isp_params_ops_v3x *)params_vdev->priv_ops;
4103 struct rkisp_isp_params_val_v3x *priv_val =
4104 (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
4105
4106 if (params_vdev->dev->hw_dev->is_unite) {
4107 ops->hdrmge_config(params_vdev, &priv_val->last_hdrmge, RKISP_PARAMS_SHD, 1);
4108 ops->hdrdrc_config(params_vdev, &priv_val->last_hdrdrc, RKISP_PARAMS_SHD, 1);
4109 }
4110 ops->hdrmge_config(params_vdev, &priv_val->last_hdrmge, RKISP_PARAMS_SHD, 0);
4111 ops->hdrdrc_config(params_vdev, &priv_val->last_hdrdrc, RKISP_PARAMS_SHD, 0);
4112 }
4113
4114 static
rkisp_params_cfgsram_v3x(struct rkisp_isp_params_vdev * params_vdev)4115 void rkisp_params_cfgsram_v3x(struct rkisp_isp_params_vdev *params_vdev)
4116 {
4117 struct isp3x_isp_params_cfg *params = params_vdev->isp3x_params;
4118
4119 isp_lsc_matrix_cfg_sram(params_vdev, ¶ms->others.lsc_cfg, true, 0);
4120 isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist1, 1, true, 0);
4121 isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist2, 2, true, 0);
4122 isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist3, 0, true, 0);
4123 isp_rawawb_cfg_sram(params_vdev, ¶ms->meas.rawawb, true, 0);
4124 if (params_vdev->dev->hw_dev->is_unite) {
4125 params++;
4126 isp_lsc_matrix_cfg_sram(params_vdev, ¶ms->others.lsc_cfg, true, 1);
4127 isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist1, 1, true, 1);
4128 isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist2, 2, true, 1);
4129 isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist3, 0, true, 1);
4130 isp_rawawb_cfg_sram(params_vdev, ¶ms->meas.rawawb, true, 1);
4131 }
4132 }
4133
4134 static int
rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_isp_params_cfg * new_params)4135 rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev,
4136 const struct isp3x_isp_params_cfg *new_params)
4137 {
4138 struct rkisp_device *ispdev = params_vdev->dev;
4139 struct rkisp_isp_subdev *isp_sdev = &ispdev->isp_sdev;
4140 struct rkisp_isp_params_val_v3x *priv_val;
4141 u64 module_en_update, module_ens;
4142 int ret, w, h, size, id, i;
4143
4144 priv_val = (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
4145 module_en_update = new_params->module_en_update;
4146 module_ens = new_params->module_ens;
4147
4148 for (id = 0; id <= ispdev->hw_dev->is_unite; id++) {
4149 priv_val->buf_3dlut_idx[id] = 0;
4150 for (i = 0; i < ISP3X_3DLUT_BUF_NUM; i++) {
4151 priv_val->buf_3dlut[id][i].is_need_vaddr = true;
4152 priv_val->buf_3dlut[id][i].size = ISP3X_3DLUT_BUF_SIZE;
4153 ret = rkisp_alloc_buffer(ispdev, &priv_val->buf_3dlut[id][i]);
4154 if (ret) {
4155 dev_err(ispdev->dev, "alloc 3dlut buf fail:%d\n", ret);
4156 goto err_3dlut;
4157 }
4158 }
4159 }
4160
4161 if ((module_en_update & ISP3X_MODULE_BAY3D) &&
4162 (module_ens & ISP3X_MODULE_BAY3D)) {
4163 w = ALIGN(isp_sdev->in_crop.width, 16);
4164 h = ALIGN(isp_sdev->in_crop.height, 16);
4165 if (ispdev->hw_dev->is_unite)
4166 w = ALIGN(isp_sdev->in_crop.width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL, 16);
4167
4168 for (id = 0; id <= ispdev->hw_dev->is_unite; id++) {
4169 size = ALIGN((w + w / 8) * h * 2, 16);
4170
4171 priv_val->buf_3dnr_iir[id].size = size;
4172 ret = rkisp_alloc_buffer(ispdev, &priv_val->buf_3dnr_iir[id]);
4173 if (ret) {
4174 dev_err(ispdev->dev, "alloc bay3d iir buf fail:%d\n", ret);
4175 goto err_3dnr;
4176 }
4177
4178 priv_val->buf_3dnr_cur[id].size = size;
4179 ret = rkisp_alloc_buffer(ispdev, &priv_val->buf_3dnr_cur[id]);
4180 if (ret) {
4181 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_iir[id]);
4182 dev_err(ispdev->dev, "alloc bay3d cur buf fail:%d\n", ret);
4183 goto err_3dnr;
4184 }
4185
4186 size = 2 * ALIGN(w * h / 64, 16);
4187 priv_val->buf_3dnr_ds[id].size = size;
4188 ret = rkisp_alloc_buffer(ispdev, &priv_val->buf_3dnr_ds[id]);
4189 if (ret) {
4190 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_iir[id]);
4191 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_cur[id]);
4192 dev_err(ispdev->dev, "alloc bay3d ds buf fail:%d\n", ret);
4193 goto err_3dnr;
4194 }
4195 }
4196 }
4197 return 0;
4198 err_3dnr:
4199 for (id -= 1; id >= 0; id--) {
4200 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_iir[id]);
4201 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_cur[id]);
4202 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_ds[id]);
4203 }
4204 id = ispdev->hw_dev->is_unite ? 1 : 0;
4205 i = ISP3X_3DLUT_BUF_NUM;
4206 err_3dlut:
4207 for (; id >= 0; id--) {
4208 for (i -= 1; i >= 0; i--)
4209 rkisp_free_buffer(ispdev, &priv_val->buf_3dlut[id][i]);
4210 i = ISP3X_3DLUT_BUF_NUM;
4211 }
4212 return ret;
4213 }
4214
4215 static bool
rkisp_params_check_bigmode_v3x(struct rkisp_isp_params_vdev * params_vdev)4216 rkisp_params_check_bigmode_v3x(struct rkisp_isp_params_vdev *params_vdev)
4217 {
4218 struct rkisp_device *ispdev = params_vdev->dev;
4219 struct device *dev = ispdev->dev;
4220 struct rkisp_hw_dev *hw = ispdev->hw_dev;
4221 struct v4l2_rect *crop = ¶ms_vdev->dev->isp_sdev.in_crop;
4222 u32 width = hw->max_in.w, height = hw->max_in.h, size = width * height;
4223 u32 bigmode_max_w, bigmode_max_size;
4224 int k = 0, idx1[DEV_MAX] = { 0 };
4225 int n = 0, idx2[DEV_MAX] = { 0 };
4226 int i = 0, j = 0;
4227 bool is_bigmode = false;
4228
4229 multi_overflow:
4230 if (hw->is_multi_overflow) {
4231 ispdev->multi_index = 0;
4232 ispdev->multi_mode = 0;
4233 bigmode_max_w = ISP3X_AUTO_BIGMODE_WIDTH;
4234 bigmode_max_size = ISP3X_NOBIG_OVERFLOW_SIZE;
4235 dev_warn(dev, "over virtual isp max resolution, force to 2 readback\n");
4236 goto end;
4237 }
4238
4239 switch (hw->dev_link_num) {
4240 case 4:
4241 bigmode_max_w = ISP3X_VIR4_AUTO_BIGMODE_WIDTH;
4242 bigmode_max_size = ISP3X_VIR4_NOBIG_OVERFLOW_SIZE;
4243 ispdev->multi_index = ispdev->dev_id;
4244 ispdev->multi_mode = 2;
4245 /* internal buf of hw divided to four parts
4246 * bigmode nobigmode
4247 * _________ max width:2560 max width:1280
4248 * |_sensor0_| max size:2560*1536 max size:1280*800
4249 * |_sensor1_| max size:2560*1536 max size:1280*800
4250 * |_sensor2_| max size:2560*1536 max size:1280*800
4251 * |_sensor3_| max size:2560*1536 max size:1280*800
4252 */
4253 for (i = 0; i < hw->dev_num; i++) {
4254 if (hw->isp_size[i].w <= ISP3X_VIR4_MAX_WIDTH &&
4255 hw->isp_size[i].size <= ISP3X_VIR4_MAX_SIZE)
4256 continue;
4257 dev_warn(dev, "isp%d %dx%d over four vir isp max:%dx1536\n",
4258 i, hw->isp_size[i].w, hw->isp_size[i].h,
4259 hw->is_unite ? (2560 - RKMOUDLE_UNITE_EXTEND_PIXEL) * 2 : 2560);
4260 hw->is_multi_overflow = true;
4261 goto multi_overflow;
4262 }
4263 break;
4264 case 3:
4265 bigmode_max_w = ISP3X_VIR4_AUTO_BIGMODE_WIDTH;
4266 bigmode_max_size = ISP3X_VIR4_NOBIG_OVERFLOW_SIZE;
4267 ispdev->multi_index = ispdev->dev_id;
4268 ispdev->multi_mode = 2;
4269 /* case0: bigmode nobigmode
4270 * _________ max width:2560 max width:1280
4271 * |_sensor0_| max size:2560*1536 max size:1280*800
4272 * |_sensor1_| max size:2560*1536 max size:1280*800
4273 * |_sensor2_| max size:2560*1536 max size:1280*800
4274 * |_________|
4275 *
4276 * case1: bigmode special reg cfg
4277 * _________ max width:3840
4278 * | sensor0 | max size:3840*2160 mode=1 index=0
4279 * |_________|
4280 * |_sensor1_| max size:2560*1536 mode=2 index=2
4281 * |_sensor2_| max size:2560*1536 mode=2 index=3
4282 * max width:2560
4283 */
4284 for (i = 0; i < hw->dev_num; i++) {
4285 if (!hw->isp_size[i].size) {
4286 if (i < hw->dev_link_num)
4287 idx2[n++] = i;
4288 continue;
4289 }
4290 if (hw->isp_size[i].w <= ISP3X_VIR4_MAX_WIDTH &&
4291 hw->isp_size[i].size <= ISP3X_VIR4_MAX_SIZE)
4292 continue;
4293 idx1[k++] = i;
4294 }
4295 if (k) {
4296 is_bigmode = true;
4297 if (k != 1 ||
4298 (hw->isp_size[idx1[0]].size > ISP3X_VIR2_MAX_SIZE)) {
4299 dev_warn(dev, "isp%d %dx%d over three vir isp max:%dx1536\n",
4300 idx1[0], hw->isp_size[idx1[0]].w, hw->isp_size[idx1[0]].h,
4301 hw->is_unite ? (2560 - RKMOUDLE_UNITE_EXTEND_PIXEL) * 2 : 2560);
4302 hw->is_multi_overflow = true;
4303 goto multi_overflow;
4304 } else {
4305 if (idx1[0] == ispdev->dev_id) {
4306 ispdev->multi_mode = 1;
4307 ispdev->multi_index = 0;
4308 } else {
4309 ispdev->multi_mode = 2;
4310 if (ispdev->multi_index == 0 ||
4311 ispdev->multi_index == 1)
4312 ispdev->multi_index = 3;
4313 }
4314 }
4315 } else if (ispdev->multi_index >= hw->dev_link_num) {
4316 ispdev->multi_index = idx2[ispdev->multi_index - hw->dev_link_num];
4317 }
4318 break;
4319 case 2:
4320 bigmode_max_w = ISP3X_VIR2_AUTO_BIGMODE_WIDTH;
4321 bigmode_max_size = ISP3X_VIR2_NOBIG_OVERFLOW_SIZE;
4322 ispdev->multi_index = ispdev->dev_id;
4323 ispdev->multi_mode = 1;
4324 /* case0: bigmode nobigmode
4325 * _________ max width:3840 max width:1920
4326 * | sensor0 | max size:3840*2160 max size:1920*1080
4327 * |_________|
4328 * | sensor1 | max size:3840*2160 max size:1920*1080
4329 * |_________|
4330 *
4331 * case1: bigmode special reg cfg
4332 * _________ max width:4672
4333 * | sensor0 | max size: mode=0 index=0
4334 * | | 3840*2160+2560*2160
4335 * |_________|
4336 * |_sensor1_| max size:2560*1536 mode=2 index=3
4337 * max width:2560
4338 */
4339 for (i = 0; i < hw->dev_num; i++) {
4340 if (!hw->isp_size[i].size) {
4341 if (i < hw->dev_link_num)
4342 idx2[n++] = i;
4343 continue;
4344 }
4345 if (hw->isp_size[i].w <= ISP3X_VIR2_MAX_WIDTH &&
4346 hw->isp_size[i].size <= ISP3X_VIR2_MAX_SIZE) {
4347 if (hw->isp_size[i].w > ISP3X_VIR4_MAX_WIDTH ||
4348 hw->isp_size[i].size > ISP3X_VIR4_MAX_SIZE)
4349 j++;
4350 continue;
4351 }
4352 idx1[k++] = i;
4353 }
4354 if (k) {
4355 is_bigmode = true;
4356 if (k == 2 || j ||
4357 hw->isp_size[idx1[k - 1]].size > (ISP3X_VIR4_MAX_SIZE + ISP3X_VIR2_MAX_SIZE)) {
4358 dev_warn(dev, "isp%d %dx%d over two vir isp max:%dx2160\n",
4359 idx1[k - 1], hw->isp_size[idx1[k - 1]].w, hw->isp_size[idx1[k - 1]].h,
4360 hw->is_unite ? (3840 - RKMOUDLE_UNITE_EXTEND_PIXEL) * 2 : 3840);
4361 hw->is_multi_overflow = true;
4362 goto multi_overflow;
4363 } else {
4364 if (idx1[0] == ispdev->dev_id) {
4365 ispdev->multi_mode = 0;
4366 ispdev->multi_index = 0;
4367 } else {
4368 ispdev->multi_mode = 2;
4369 ispdev->multi_index = 3;
4370 }
4371 }
4372 } else if (ispdev->multi_index >= hw->dev_link_num) {
4373 ispdev->multi_index = idx2[ispdev->multi_index - hw->dev_link_num];
4374 }
4375 break;
4376 default:
4377 bigmode_max_w = ISP3X_AUTO_BIGMODE_WIDTH;
4378 bigmode_max_size = ISP3X_NOBIG_OVERFLOW_SIZE;
4379 ispdev->multi_mode = 0;
4380 ispdev->multi_index = 0;
4381 width = crop->width;
4382 if (hw->is_unite)
4383 width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
4384 height = crop->height;
4385 size = width * height;
4386 break;
4387 }
4388
4389 end:
4390 if (!is_bigmode &&
4391 (width > bigmode_max_w || size > bigmode_max_size))
4392 is_bigmode = true;
4393
4394 return ispdev->is_bigmode = is_bigmode;
4395 }
4396
4397 /* Not called when the camera active, thus not isr protection. */
4398 static void
rkisp_params_first_cfg_v3x(struct rkisp_isp_params_vdev * params_vdev)4399 rkisp_params_first_cfg_v3x(struct rkisp_isp_params_vdev *params_vdev)
4400 {
4401 struct rkisp_device *dev = params_vdev->dev;
4402 struct rkisp_isp_params_val_v3x *priv_val =
4403 (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
4404 struct rkisp_hw_dev *hw = params_vdev->dev->hw_dev;
4405
4406 dev->is_bigmode = rkisp_params_check_bigmode_v3x(params_vdev);
4407 spin_lock(¶ms_vdev->config_lock);
4408 /* override the default things */
4409 if (!params_vdev->isp3x_params->module_cfg_update &&
4410 !params_vdev->isp3x_params->module_en_update)
4411 dev_warn(dev->dev, "can not get first iq setting in stream on\n");
4412
4413 priv_val->bay3d_en = 0;
4414 priv_val->dhaz_en = 0;
4415 priv_val->drc_en = 0;
4416 priv_val->lsc_en = 0;
4417 priv_val->mge_en = 0;
4418 priv_val->lut3d_en = 0;
4419 if (hw->is_unite) {
4420 if (dev->is_bigmode)
4421 rkisp_next_set_bits(params_vdev->dev, ISP3X_ISP_CTRL1, 0,
4422 ISP3X_BIGMODE_MANUAL | ISP3X_BIGMODE_FORCE_EN, false);
4423 __isp_isr_meas_config(params_vdev, params_vdev->isp3x_params + 1, RKISP_PARAMS_ALL, 1);
4424 __isp_isr_other_config(params_vdev, params_vdev->isp3x_params + 1, RKISP_PARAMS_ALL, 1);
4425 __isp_isr_other_en(params_vdev, params_vdev->isp3x_params + 1, RKISP_PARAMS_ALL, 1);
4426 __isp_isr_meas_en(params_vdev, params_vdev->isp3x_params + 1, RKISP_PARAMS_ALL, 1);
4427 }
4428 if (dev->is_bigmode)
4429 rkisp_set_bits(params_vdev->dev, ISP3X_ISP_CTRL1, 0,
4430 ISP3X_BIGMODE_MANUAL | ISP3X_BIGMODE_FORCE_EN, false);
4431 __isp_isr_meas_config(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 0);
4432 __isp_isr_other_config(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 0);
4433 __isp_isr_other_en(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 0);
4434 __isp_isr_meas_en(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 0);
4435
4436 priv_val->cur_hdrmge = params_vdev->isp3x_params->others.hdrmge_cfg;
4437 priv_val->cur_hdrdrc = params_vdev->isp3x_params->others.drc_cfg;
4438 priv_val->last_hdrmge = priv_val->cur_hdrmge;
4439 priv_val->last_hdrdrc = priv_val->cur_hdrdrc;
4440 spin_unlock(¶ms_vdev->config_lock);
4441 }
4442
rkisp_save_first_param_v3x(struct rkisp_isp_params_vdev * params_vdev,void * param)4443 static void rkisp_save_first_param_v3x(struct rkisp_isp_params_vdev *params_vdev, void *param)
4444 {
4445 struct rkisp_isp_params_val_v3x *priv_val =
4446 (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
4447
4448 memcpy(params_vdev->isp3x_params, param, params_vdev->vdev_fmt.fmt.meta.buffersize);
4449 tasklet_enable(&priv_val->lsc_tasklet);
4450 rkisp_alloc_internal_buf(params_vdev, params_vdev->isp3x_params);
4451 }
4452
rkisp_clear_first_param_v3x(struct rkisp_isp_params_vdev * params_vdev)4453 static void rkisp_clear_first_param_v3x(struct rkisp_isp_params_vdev *params_vdev)
4454 {
4455 u32 mult = params_vdev->dev->hw_dev->is_unite ? ISP3_UNITE_MAX : 1;
4456 u32 size = sizeof(struct isp3x_isp_params_cfg) * mult;
4457
4458 memset(params_vdev->isp3x_params, 0, size);
4459 }
4460
rkisp_deinit_mesh_buf(struct rkisp_isp_params_vdev * params_vdev,u64 module_id,u32 id)4461 static void rkisp_deinit_mesh_buf(struct rkisp_isp_params_vdev *params_vdev,
4462 u64 module_id, u32 id)
4463 {
4464 struct rkisp_isp_params_val_v3x *priv_val;
4465 struct rkisp_dummy_buffer *buf;
4466 int i;
4467
4468 priv_val = params_vdev->priv_val;
4469 if (!priv_val)
4470 return;
4471
4472 switch (module_id) {
4473 case ISP3X_MODULE_CAC:
4474 buf = priv_val->buf_cac[id];
4475 break;
4476 case ISP3X_MODULE_LDCH:
4477 default:
4478 buf = priv_val->buf_ldch[id];
4479 break;
4480 }
4481
4482 for (i = 0; i < ISP3X_MESH_BUF_NUM; i++)
4483 rkisp_free_buffer(params_vdev->dev, buf + i);
4484 }
4485
rkisp_init_mesh_buf(struct rkisp_isp_params_vdev * params_vdev,struct rkisp_meshbuf_size * meshsize)4486 static int rkisp_init_mesh_buf(struct rkisp_isp_params_vdev *params_vdev,
4487 struct rkisp_meshbuf_size *meshsize)
4488 {
4489 struct rkisp_device *ispdev = params_vdev->dev;
4490 struct device *dev = ispdev->dev;
4491 struct rkisp_isp_params_val_v3x *priv_val;
4492 struct isp2x_mesh_head *mesh_head;
4493 struct rkisp_dummy_buffer *buf;
4494 u32 mesh_w = meshsize->meas_width;
4495 u32 mesh_h = meshsize->meas_height;
4496 u32 mesh_size, buf_size;
4497 int i, ret, id = meshsize->unite_isp_id;
4498 int buf_cnt = meshsize->buf_cnt;
4499
4500 priv_val = params_vdev->priv_val;
4501 if (!priv_val) {
4502 dev_err(dev, "priv_val is NULL\n");
4503 return -EINVAL;
4504 }
4505
4506 switch (meshsize->module_id) {
4507 case ISP3X_MODULE_CAC:
4508 priv_val->buf_cac_idx[id] = 0;
4509 buf = priv_val->buf_cac[id];
4510 mesh_w = (mesh_w + 62) / 64 * 9;
4511 mesh_h = (mesh_h + 62) / 64 * 2;
4512 mesh_size = mesh_w * 4 * mesh_h;
4513 break;
4514 case ISP3X_MODULE_LDCH:
4515 default:
4516 priv_val->buf_ldch_idx[id] = 0;
4517 buf = priv_val->buf_ldch[id];
4518 mesh_w = ((mesh_w + 15) / 16 + 2) / 2;
4519 mesh_h = (mesh_h + 7) / 8 + 1;
4520 mesh_size = mesh_w * 4 * mesh_h;
4521 break;
4522 }
4523
4524 if (buf_cnt <= 0 || buf_cnt > ISP3X_MESH_BUF_NUM)
4525 buf_cnt = ISP3X_MESH_BUF_NUM;
4526 buf_size = PAGE_ALIGN(mesh_size + ALIGN(sizeof(struct isp2x_mesh_head), 16));
4527 for (i = 0; i < buf_cnt; i++) {
4528 buf->is_need_vaddr = true;
4529 buf->is_need_dbuf = true;
4530 buf->is_need_dmafd = true;
4531 buf->size = buf_size;
4532 ret = rkisp_alloc_buffer(params_vdev->dev, buf);
4533 if (ret) {
4534 dev_err(dev, "%s failed\n", __func__);
4535 goto err;
4536 }
4537
4538 mesh_head = (struct isp2x_mesh_head *)buf->vaddr;
4539 mesh_head->stat = MESH_BUF_INIT;
4540 mesh_head->data_oft = ALIGN(sizeof(struct isp2x_mesh_head), 16);
4541 buf++;
4542 }
4543
4544 return 0;
4545 err:
4546 rkisp_deinit_mesh_buf(params_vdev, meshsize->module_id, id);
4547 return -ENOMEM;
4548 }
4549
4550 static void
rkisp_get_param_size_v3x(struct rkisp_isp_params_vdev * params_vdev,unsigned int sizes[])4551 rkisp_get_param_size_v3x(struct rkisp_isp_params_vdev *params_vdev,
4552 unsigned int sizes[])
4553 {
4554 u32 mult = params_vdev->dev->hw_dev->is_unite ? ISP3_UNITE_MAX : 1;
4555
4556 sizes[0] = sizeof(struct isp3x_isp_params_cfg) * mult;
4557 }
4558
4559 static void
rkisp_params_get_meshbuf_inf_v3x(struct rkisp_isp_params_vdev * params_vdev,void * meshbuf_inf)4560 rkisp_params_get_meshbuf_inf_v3x(struct rkisp_isp_params_vdev *params_vdev,
4561 void *meshbuf_inf)
4562 {
4563 struct rkisp_isp_params_val_v3x *priv_val;
4564 struct rkisp_meshbuf_info *meshbuf = meshbuf_inf;
4565 struct rkisp_dummy_buffer *buf;
4566 int i, id = meshbuf->unite_isp_id;
4567
4568 priv_val = params_vdev->priv_val;
4569 switch (meshbuf->module_id) {
4570 case ISP3X_MODULE_CAC:
4571 priv_val->buf_cac_idx[id] = 0;
4572 buf = priv_val->buf_cac[id];
4573 break;
4574 case ISP3X_MODULE_LDCH:
4575 default:
4576 priv_val->buf_ldch_idx[id] = 0;
4577 buf = priv_val->buf_ldch[id];
4578 break;
4579 }
4580
4581 for (i = 0; i < ISP3X_MESH_BUF_NUM; i++) {
4582 if (!buf->mem_priv) {
4583 meshbuf->buf_fd[i] = -1;
4584 meshbuf->buf_size[i] = 0;
4585 } else {
4586 meshbuf->buf_fd[i] = buf->dma_fd;
4587 meshbuf->buf_size[i] = buf->size;
4588 }
4589 buf++;
4590 }
4591 }
4592
4593 static int
rkisp_params_set_meshbuf_size_v3x(struct rkisp_isp_params_vdev * params_vdev,void * size)4594 rkisp_params_set_meshbuf_size_v3x(struct rkisp_isp_params_vdev *params_vdev,
4595 void *size)
4596 {
4597 struct rkisp_meshbuf_size *meshsize = size;
4598
4599 if (!params_vdev->dev->hw_dev->is_unite)
4600 meshsize->unite_isp_id = 0;
4601 rkisp_deinit_mesh_buf(params_vdev, meshsize->module_id, meshsize->unite_isp_id);
4602 return rkisp_init_mesh_buf(params_vdev, meshsize);
4603 }
4604
4605 static void
rkisp_params_free_meshbuf_v3x(struct rkisp_isp_params_vdev * params_vdev,u64 module_id)4606 rkisp_params_free_meshbuf_v3x(struct rkisp_isp_params_vdev *params_vdev,
4607 u64 module_id)
4608 {
4609 int id;
4610
4611 for (id = 0; id <= params_vdev->dev->hw_dev->is_unite; id++)
4612 rkisp_deinit_mesh_buf(params_vdev, module_id, id);
4613 }
4614
4615 static void
rkisp_params_stream_stop_v3x(struct rkisp_isp_params_vdev * params_vdev)4616 rkisp_params_stream_stop_v3x(struct rkisp_isp_params_vdev *params_vdev)
4617 {
4618 struct rkisp_device *ispdev = params_vdev->dev;
4619 struct rkisp_isp_params_val_v3x *priv_val;
4620 u32 id, i;
4621
4622 priv_val = (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
4623 tasklet_disable(&priv_val->lsc_tasklet);
4624 for (id = 0; id <= ispdev->hw_dev->is_unite; id++) {
4625 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_iir[id]);
4626 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_cur[id]);
4627 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_ds[id]);
4628 for (i = 0; i < ISP3X_3DLUT_BUF_NUM; i++)
4629 rkisp_free_buffer(ispdev, &priv_val->buf_3dlut[id][i]);
4630 }
4631 for (i = 0; i < RKISP_STATS_DDR_BUF_NUM; i++)
4632 rkisp_free_buffer(ispdev, &ispdev->stats_vdev.stats_buf[i]);
4633 }
4634
4635 static void
rkisp_params_fop_release_v3x(struct rkisp_isp_params_vdev * params_vdev)4636 rkisp_params_fop_release_v3x(struct rkisp_isp_params_vdev *params_vdev)
4637 {
4638 int id;
4639
4640 for (id = 0; id <= params_vdev->dev->hw_dev->is_unite; id++) {
4641 rkisp_deinit_mesh_buf(params_vdev, ISP3X_MODULE_LDCH, id);
4642 rkisp_deinit_mesh_buf(params_vdev, ISP3X_MODULE_CAC, id);
4643 }
4644 }
4645
4646 /* Not called when the camera active, thus not isr protection. */
4647 static void
rkisp_params_disable_isp_v3x(struct rkisp_isp_params_vdev * params_vdev)4648 rkisp_params_disable_isp_v3x(struct rkisp_isp_params_vdev *params_vdev)
4649 {
4650 params_vdev->isp3x_params->module_ens = 0;
4651 params_vdev->isp3x_params->module_en_update = 0x7ffffffffff;
4652
4653 __isp_isr_other_en(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 0);
4654 __isp_isr_meas_en(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 0);
4655 if (params_vdev->dev->hw_dev->is_unite) {
4656 __isp_isr_other_en(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 1);
4657 __isp_isr_meas_en(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 1);
4658 }
4659 }
4660
4661 static void
module_data_abandon(struct rkisp_isp_params_vdev * params_vdev,struct isp3x_isp_params_cfg * params,u32 id)4662 module_data_abandon(struct rkisp_isp_params_vdev *params_vdev,
4663 struct isp3x_isp_params_cfg *params, u32 id)
4664 {
4665 struct rkisp_isp_params_val_v3x *priv_val;
4666 struct isp2x_mesh_head *mesh_head;
4667 int i;
4668
4669 priv_val = (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
4670 if (params->module_cfg_update & ISP3X_MODULE_LDCH) {
4671 const struct isp2x_ldch_cfg *arg = ¶ms->others.ldch_cfg;
4672
4673 for (i = 0; i < ISP3X_MESH_BUF_NUM; i++) {
4674 if (priv_val->buf_ldch[id][i].vaddr &&
4675 arg->buf_fd == priv_val->buf_ldch[id][i].dma_fd) {
4676 mesh_head = (struct isp2x_mesh_head *)priv_val->buf_ldch[id][i].vaddr;
4677 mesh_head->stat = MESH_BUF_CHIPINUSE;
4678 break;
4679 }
4680 }
4681 }
4682
4683 if (params->module_cfg_update & ISP3X_MODULE_CAC) {
4684 const struct isp3x_cac_cfg *arg = ¶ms->others.cac_cfg;
4685
4686 for (i = 0; i < ISP3X_MESH_BUF_NUM; i++) {
4687 if (priv_val->buf_cac[id][i].vaddr &&
4688 arg->buf_fd == priv_val->buf_cac[id][i].dma_fd) {
4689 mesh_head = (struct isp2x_mesh_head *)priv_val->buf_cac[id][i].vaddr;
4690 mesh_head->stat = MESH_BUF_CHIPINUSE;
4691 break;
4692 }
4693 }
4694 }
4695 }
4696
4697 static void
rkisp_params_cfg_v3x(struct rkisp_isp_params_vdev * params_vdev,u32 frame_id,enum rkisp_params_type type)4698 rkisp_params_cfg_v3x(struct rkisp_isp_params_vdev *params_vdev,
4699 u32 frame_id, enum rkisp_params_type type)
4700 {
4701 struct isp3x_isp_params_cfg *new_params = NULL;
4702 struct rkisp_buffer *cur_buf = params_vdev->cur_buf;
4703 struct rkisp_device *dev = params_vdev->dev;
4704 struct rkisp_hw_dev *hw_dev = dev->hw_dev;
4705
4706 spin_lock(¶ms_vdev->config_lock);
4707 if (!params_vdev->streamon)
4708 goto unlock;
4709
4710 /* get buffer by frame_id */
4711 while (!list_empty(¶ms_vdev->params) && !cur_buf) {
4712 cur_buf = list_first_entry(¶ms_vdev->params,
4713 struct rkisp_buffer, queue);
4714
4715 new_params = (struct isp3x_isp_params_cfg *)(cur_buf->vaddr[0]);
4716 if (new_params->frame_id < frame_id) {
4717 list_del(&cur_buf->queue);
4718 if (list_empty(¶ms_vdev->params))
4719 break;
4720 else if (new_params->module_en_update ||
4721 (new_params->module_cfg_update & ISP3X_MODULE_FORCE)) {
4722 /* update en immediately */
4723 __isp_isr_meas_config(params_vdev, new_params, type, 0);
4724 __isp_isr_other_config(params_vdev, new_params, type, 0);
4725 __isp_isr_other_en(params_vdev, new_params, type, 0);
4726 __isp_isr_meas_en(params_vdev, new_params, type, 0);
4727 new_params->module_cfg_update = 0;
4728 if (hw_dev->is_unite) {
4729 struct isp3x_isp_params_cfg *params = new_params + 1;
4730
4731 __isp_isr_meas_config(params_vdev, params, type, 1);
4732 __isp_isr_other_config(params_vdev, params, type, 1);
4733 __isp_isr_other_en(params_vdev, params, type, 1);
4734 __isp_isr_meas_en(params_vdev, params, type, 1);
4735 params->module_cfg_update = 0;
4736 }
4737 }
4738 if (new_params->module_cfg_update &
4739 (ISP3X_MODULE_LDCH | ISP3X_MODULE_CAC)) {
4740 module_data_abandon(params_vdev, new_params, 0);
4741 if (hw_dev->is_unite)
4742 module_data_abandon(params_vdev, new_params, 1);
4743 }
4744 vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
4745 cur_buf = NULL;
4746 continue;
4747 } else if (new_params->frame_id == frame_id) {
4748 list_del(&cur_buf->queue);
4749 } else {
4750 cur_buf = NULL;
4751 }
4752 break;
4753 }
4754
4755 if (!cur_buf)
4756 goto unlock;
4757
4758 new_params = (struct isp3x_isp_params_cfg *)(cur_buf->vaddr[0]);
4759 if (hw_dev->is_unite) {
4760 __isp_isr_meas_config(params_vdev, new_params + 1, type, 1);
4761 __isp_isr_other_config(params_vdev, new_params + 1, type, 1);
4762 __isp_isr_other_en(params_vdev, new_params + 1, type, 1);
4763 __isp_isr_meas_en(params_vdev, new_params + 1, type, 1);
4764 }
4765 __isp_isr_meas_config(params_vdev, new_params, type, 0);
4766 __isp_isr_other_config(params_vdev, new_params, type, 0);
4767 __isp_isr_other_en(params_vdev, new_params, type, 0);
4768 __isp_isr_meas_en(params_vdev, new_params, type, 0);
4769 if (!hw_dev->is_single && type != RKISP_PARAMS_SHD)
4770 __isp_config_hdrshd(params_vdev);
4771
4772 if (type != RKISP_PARAMS_IMD) {
4773 struct rkisp_isp_params_val_v3x *priv_val =
4774 (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
4775
4776 priv_val->last_hdrmge = priv_val->cur_hdrmge;
4777 priv_val->last_hdrdrc = priv_val->cur_hdrdrc;
4778 priv_val->cur_hdrmge = new_params->others.hdrmge_cfg;
4779 priv_val->cur_hdrdrc = new_params->others.drc_cfg;
4780 new_params->module_cfg_update = 0;
4781 if (hw_dev->is_unite)
4782 (new_params++)->module_cfg_update = 0;
4783 vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
4784 cur_buf = NULL;
4785 }
4786
4787 unlock:
4788 params_vdev->cur_buf = cur_buf;
4789 spin_unlock(¶ms_vdev->config_lock);
4790 }
4791
4792 static void
rkisp_params_clear_fstflg(struct rkisp_isp_params_vdev * params_vdev)4793 rkisp_params_clear_fstflg(struct rkisp_isp_params_vdev *params_vdev)
4794 {
4795 struct rkisp_device *dev = params_vdev->dev;
4796 struct rkisp_hw_dev *hw_dev = dev->hw_dev;
4797 u32 value;
4798
4799 value = rkisp_read(dev, ISP3X_ISP_CTRL1, false);
4800 if (value & ISP3X_YNR_FST_FRAME)
4801 rkisp_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
4802 ISP3X_YNR_FST_FRAME, false);
4803 if (value & ISP3X_ADRC_FST_FRAME)
4804 rkisp_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
4805 ISP3X_ADRC_FST_FRAME, false);
4806 if (value & ISP3X_DHAZ_FST_FRAME)
4807 rkisp_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
4808 ISP3X_DHAZ_FST_FRAME, false);
4809 if (value & ISP3X_CNR_FST_FRAME)
4810 rkisp_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
4811 ISP3X_CNR_FST_FRAME, false);
4812 if (value & ISP3X_RAW3D_FST_FRAME)
4813 rkisp_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
4814 ISP3X_RAW3D_FST_FRAME, false);
4815 if (hw_dev->is_unite) {
4816 value = rkisp_next_read(dev, ISP3X_ISP_CTRL1, false);
4817 if (value & ISP3X_YNR_FST_FRAME)
4818 rkisp_next_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
4819 ISP3X_YNR_FST_FRAME, false);
4820 if (value & ISP3X_ADRC_FST_FRAME)
4821 rkisp_next_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
4822 ISP3X_ADRC_FST_FRAME, false);
4823 if (value & ISP3X_DHAZ_FST_FRAME)
4824 rkisp_next_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
4825 ISP3X_DHAZ_FST_FRAME, false);
4826 if (value & ISP3X_CNR_FST_FRAME)
4827 rkisp_next_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
4828 ISP3X_CNR_FST_FRAME, false);
4829 if (value & ISP3X_RAW3D_FST_FRAME)
4830 rkisp_next_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
4831 ISP3X_RAW3D_FST_FRAME, false);
4832 }
4833 }
4834
4835 static void
rkisp_params_isr_v3x(struct rkisp_isp_params_vdev * params_vdev,u32 isp_mis)4836 rkisp_params_isr_v3x(struct rkisp_isp_params_vdev *params_vdev,
4837 u32 isp_mis)
4838 {
4839 struct rkisp_device *dev = params_vdev->dev;
4840 u32 cur_frame_id;
4841
4842 rkisp_dmarx_get_frame(dev, &cur_frame_id, NULL, NULL, true);
4843 if (isp_mis & CIF_ISP_V_START) {
4844 if (params_vdev->rdbk_times)
4845 params_vdev->rdbk_times--;
4846 if (!params_vdev->cur_buf)
4847 return;
4848
4849 if (IS_HDR_RDBK(dev->rd_mode) && !params_vdev->rdbk_times) {
4850 rkisp_params_cfg_v3x(params_vdev, cur_frame_id, RKISP_PARAMS_SHD);
4851 return;
4852 }
4853 }
4854
4855 if (isp_mis & CIF_ISP_FRAME)
4856 rkisp_params_clear_fstflg(params_vdev);
4857
4858 if ((isp_mis & CIF_ISP_FRAME) && !IS_HDR_RDBK(dev->rd_mode))
4859 rkisp_params_cfg_v3x(params_vdev, cur_frame_id + 1, RKISP_PARAMS_ALL);
4860 }
4861
4862 static struct rkisp_isp_params_ops rkisp_isp_params_ops_tbl = {
4863 .save_first_param = rkisp_save_first_param_v3x,
4864 .clear_first_param = rkisp_clear_first_param_v3x,
4865 .get_param_size = rkisp_get_param_size_v3x,
4866 .first_cfg = rkisp_params_first_cfg_v3x,
4867 .disable_isp = rkisp_params_disable_isp_v3x,
4868 .isr_hdl = rkisp_params_isr_v3x,
4869 .param_cfg = rkisp_params_cfg_v3x,
4870 .param_cfgsram = rkisp_params_cfgsram_v3x,
4871 .get_meshbuf_inf = rkisp_params_get_meshbuf_inf_v3x,
4872 .set_meshbuf_size = rkisp_params_set_meshbuf_size_v3x,
4873 .free_meshbuf = rkisp_params_free_meshbuf_v3x,
4874 .stream_stop = rkisp_params_stream_stop_v3x,
4875 .fop_release = rkisp_params_fop_release_v3x,
4876 .check_bigmode = rkisp_params_check_bigmode_v3x,
4877 };
4878
rkisp_init_params_vdev_v3x(struct rkisp_isp_params_vdev * params_vdev)4879 int rkisp_init_params_vdev_v3x(struct rkisp_isp_params_vdev *params_vdev)
4880 {
4881 struct rkisp_device *ispdev = params_vdev->dev;
4882 struct rkisp_isp_params_val_v3x *priv_val;
4883 int size;
4884
4885 priv_val = kzalloc(sizeof(*priv_val), GFP_KERNEL);
4886 if (!priv_val)
4887 return -ENOMEM;
4888
4889 size = sizeof(struct isp3x_isp_params_cfg);
4890 if (ispdev->hw_dev->is_unite)
4891 size *= 2;
4892 params_vdev->isp3x_params = vmalloc(size);
4893 if (!params_vdev->isp3x_params) {
4894 kfree(priv_val);
4895 return -ENOMEM;
4896 }
4897
4898 params_vdev->priv_val = (void *)priv_val;
4899 params_vdev->ops = &rkisp_isp_params_ops_tbl;
4900 params_vdev->priv_ops = &isp_params_ops_v3x;
4901 rkisp_clear_first_param_v3x(params_vdev);
4902 tasklet_init(&priv_val->lsc_tasklet,
4903 isp_lsc_cfg_sram_task,
4904 (unsigned long)params_vdev);
4905 tasklet_disable(&priv_val->lsc_tasklet);
4906 return 0;
4907 }
4908
rkisp_uninit_params_vdev_v3x(struct rkisp_isp_params_vdev * params_vdev)4909 void rkisp_uninit_params_vdev_v3x(struct rkisp_isp_params_vdev *params_vdev)
4910 {
4911 struct rkisp_isp_params_val_v3x *priv_val = params_vdev->priv_val;
4912
4913 if (params_vdev->isp3x_params)
4914 vfree(params_vdev->isp3x_params);
4915 if (priv_val) {
4916 tasklet_kill(&priv_val->lsc_tasklet);
4917 kfree(priv_val);
4918 params_vdev->priv_val = NULL;
4919 }
4920 }
4921