1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /* Copyright (C) 2019 Rockchip Electronics Co., Ltd */
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include <media/videobuf2-dma-contig.h>
5*4882a593Smuzhiyun #include <media/videobuf2-dma-sg.h>
6*4882a593Smuzhiyun #include <linux/of_platform.h>
7*4882a593Smuzhiyun #include <linux/slab.h>
8*4882a593Smuzhiyun #include "dev.h"
9*4882a593Smuzhiyun #include "isp_ispp.h"
10*4882a593Smuzhiyun #include "regs.h"
11*4882a593Smuzhiyun
rkisp_write(struct rkisp_device * dev,u32 reg,u32 val,bool is_direct)12*4882a593Smuzhiyun void rkisp_write(struct rkisp_device *dev, u32 reg, u32 val, bool is_direct)
13*4882a593Smuzhiyun {
14*4882a593Smuzhiyun u32 *mem = dev->sw_base_addr + reg;
15*4882a593Smuzhiyun u32 *flag = dev->sw_base_addr + reg + RKISP_ISP_SW_REG_SIZE;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun *mem = val;
18*4882a593Smuzhiyun *flag = SW_REG_CACHE;
19*4882a593Smuzhiyun if (dev->hw_dev->is_single || is_direct) {
20*4882a593Smuzhiyun *flag = SW_REG_CACHE_SYNC;
21*4882a593Smuzhiyun if (dev->isp_ver == ISP_V32 && reg <= 0x200)
22*4882a593Smuzhiyun rv1106_sdmmc_get_lock();
23*4882a593Smuzhiyun writel(val, dev->hw_dev->base_addr + reg);
24*4882a593Smuzhiyun if (dev->isp_ver == ISP_V32 && reg <= 0x200)
25*4882a593Smuzhiyun rv1106_sdmmc_put_lock();
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
rkisp_next_write(struct rkisp_device * dev,u32 reg,u32 val,bool is_direct)29*4882a593Smuzhiyun void rkisp_next_write(struct rkisp_device *dev, u32 reg, u32 val, bool is_direct)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun u32 offset = RKISP_ISP_SW_MAX_SIZE + reg;
32*4882a593Smuzhiyun u32 *mem = dev->sw_base_addr + offset;
33*4882a593Smuzhiyun u32 *flag = dev->sw_base_addr + offset + RKISP_ISP_SW_REG_SIZE;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun *mem = val;
36*4882a593Smuzhiyun *flag = SW_REG_CACHE;
37*4882a593Smuzhiyun if (dev->hw_dev->is_single || is_direct) {
38*4882a593Smuzhiyun *flag = SW_REG_CACHE_SYNC;
39*4882a593Smuzhiyun writel(val, dev->hw_dev->base_next_addr + reg);
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
rkisp_read(struct rkisp_device * dev,u32 reg,bool is_direct)43*4882a593Smuzhiyun u32 rkisp_read(struct rkisp_device *dev, u32 reg, bool is_direct)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun u32 val;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun if (dev->hw_dev->is_single || is_direct)
48*4882a593Smuzhiyun val = readl(dev->hw_dev->base_addr + reg);
49*4882a593Smuzhiyun else
50*4882a593Smuzhiyun val = *(u32 *)(dev->sw_base_addr + reg);
51*4882a593Smuzhiyun return val;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
rkisp_next_read(struct rkisp_device * dev,u32 reg,bool is_direct)54*4882a593Smuzhiyun u32 rkisp_next_read(struct rkisp_device *dev, u32 reg, bool is_direct)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun u32 val;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun if (dev->hw_dev->is_single || is_direct)
59*4882a593Smuzhiyun val = readl(dev->hw_dev->base_next_addr + reg);
60*4882a593Smuzhiyun else
61*4882a593Smuzhiyun val = *(u32 *)(dev->sw_base_addr + RKISP_ISP_SW_MAX_SIZE + reg);
62*4882a593Smuzhiyun return val;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
rkisp_set_bits(struct rkisp_device * dev,u32 reg,u32 mask,u32 val,bool is_direct)65*4882a593Smuzhiyun void rkisp_set_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val, bool is_direct)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun u32 tmp = rkisp_read(dev, reg, is_direct) & ~mask;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun rkisp_write(dev, reg, val | tmp, is_direct);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
rkisp_next_set_bits(struct rkisp_device * dev,u32 reg,u32 mask,u32 val,bool is_direct)72*4882a593Smuzhiyun void rkisp_next_set_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val, bool is_direct)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun u32 tmp = rkisp_next_read(dev, reg, is_direct) & ~mask;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun rkisp_next_write(dev, reg, val | tmp, is_direct);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
rkisp_clear_bits(struct rkisp_device * dev,u32 reg,u32 mask,bool is_direct)79*4882a593Smuzhiyun void rkisp_clear_bits(struct rkisp_device *dev, u32 reg, u32 mask, bool is_direct)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun u32 tmp = rkisp_read(dev, reg, is_direct);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun rkisp_write(dev, reg, tmp & ~mask, is_direct);
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
rkisp_next_clear_bits(struct rkisp_device * dev,u32 reg,u32 mask,bool is_direct)86*4882a593Smuzhiyun void rkisp_next_clear_bits(struct rkisp_device *dev, u32 reg, u32 mask, bool is_direct)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun u32 tmp = rkisp_next_read(dev, reg, is_direct);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun rkisp_next_write(dev, reg, tmp & ~mask, is_direct);
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
rkisp_write_reg_cache(struct rkisp_device * dev,u32 reg,u32 val)93*4882a593Smuzhiyun void rkisp_write_reg_cache(struct rkisp_device *dev, u32 reg, u32 val)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun u32 *mem = dev->sw_base_addr + reg;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun *mem = val;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
rkisp_next_write_reg_cache(struct rkisp_device * dev,u32 reg,u32 val)100*4882a593Smuzhiyun void rkisp_next_write_reg_cache(struct rkisp_device *dev, u32 reg, u32 val)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun u32 offset = RKISP_ISP_SW_MAX_SIZE + reg;
103*4882a593Smuzhiyun u32 *mem = dev->sw_base_addr + offset;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun *mem = val;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
rkisp_read_reg_cache(struct rkisp_device * dev,u32 reg)108*4882a593Smuzhiyun u32 rkisp_read_reg_cache(struct rkisp_device *dev, u32 reg)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun return *(u32 *)(dev->sw_base_addr + reg);
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
rkisp_next_read_reg_cache(struct rkisp_device * dev,u32 reg)113*4882a593Smuzhiyun u32 rkisp_next_read_reg_cache(struct rkisp_device *dev, u32 reg)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun return *(u32 *)(dev->sw_base_addr + RKISP_ISP_SW_MAX_SIZE + reg);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
rkisp_set_reg_cache_bits(struct rkisp_device * dev,u32 reg,u32 mask,u32 val)118*4882a593Smuzhiyun void rkisp_set_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun u32 tmp = rkisp_read_reg_cache(dev, reg) & ~mask;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun rkisp_write_reg_cache(dev, reg, val | tmp);
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
rkisp_next_set_reg_cache_bits(struct rkisp_device * dev,u32 reg,u32 mask,u32 val)125*4882a593Smuzhiyun void rkisp_next_set_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun u32 tmp = rkisp_next_read_reg_cache(dev, reg) & ~mask;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun rkisp_next_write_reg_cache(dev, reg, val | tmp);
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
rkisp_clear_reg_cache_bits(struct rkisp_device * dev,u32 reg,u32 mask)132*4882a593Smuzhiyun void rkisp_clear_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun u32 tmp = rkisp_read_reg_cache(dev, reg);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun rkisp_write_reg_cache(dev, reg, tmp & ~mask);
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
rkisp_next_clear_reg_cache_bits(struct rkisp_device * dev,u32 reg,u32 mask)139*4882a593Smuzhiyun void rkisp_next_clear_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun u32 tmp = rkisp_next_read_reg_cache(dev, reg);
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun rkisp_next_write_reg_cache(dev, reg, tmp & ~mask);
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun
rkisp_update_regs(struct rkisp_device * dev,u32 start,u32 end)146*4882a593Smuzhiyun void rkisp_update_regs(struct rkisp_device *dev, u32 start, u32 end)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun struct rkisp_hw_dev *hw = dev->hw_dev;
149*4882a593Smuzhiyun void __iomem *base = hw->base_addr;
150*4882a593Smuzhiyun u32 i;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun if (end > RKISP_ISP_SW_REG_SIZE - 4) {
153*4882a593Smuzhiyun dev_err(dev->dev, "%s out of range\n", __func__);
154*4882a593Smuzhiyun return;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun for (i = start; i <= end; i += 4) {
157*4882a593Smuzhiyun u32 *val = dev->sw_base_addr + i;
158*4882a593Smuzhiyun u32 *flag = dev->sw_base_addr + i + RKISP_ISP_SW_REG_SIZE;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun if (dev->procfs.mode & RKISP_PROCFS_FIL_SW) {
161*4882a593Smuzhiyun if (!((i >= ISP3X_ISP_ACQ_H_OFFS && i <= ISP3X_ISP_ACQ_V_SIZE) ||
162*4882a593Smuzhiyun (i >= ISP3X_ISP_OUT_H_OFFS && i <= ISP3X_ISP_OUT_V_SIZE) ||
163*4882a593Smuzhiyun (i >= ISP3X_DUAL_CROP_BASE && i < ISP3X_DUAL_CROP_FBC_V_SIZE_SHD) ||
164*4882a593Smuzhiyun (i >= ISP3X_MAIN_RESIZE_BASE && i < ISP3X_CSI2RX_VERSION) ||
165*4882a593Smuzhiyun (i >= CIF_ISP_IS_BASE && i < CIF_ISP_IS_V_SIZE_SHD)))
166*4882a593Smuzhiyun continue;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun if (*flag == SW_REG_CACHE) {
170*4882a593Smuzhiyun if ((i == ISP3X_MAIN_RESIZE_CTRL ||
171*4882a593Smuzhiyun i == ISP32_BP_RESIZE_CTRL ||
172*4882a593Smuzhiyun i == ISP3X_SELF_RESIZE_CTRL) && *val == 0)
173*4882a593Smuzhiyun *val = CIF_RSZ_CTRL_CFG_UPD;
174*4882a593Smuzhiyun writel(*val, base + i);
175*4882a593Smuzhiyun if (hw->is_unite) {
176*4882a593Smuzhiyun val = dev->sw_base_addr + i + RKISP_ISP_SW_MAX_SIZE;
177*4882a593Smuzhiyun if ((i == ISP3X_MAIN_RESIZE_CTRL ||
178*4882a593Smuzhiyun i == ISP32_BP_RESIZE_CTRL ||
179*4882a593Smuzhiyun i == ISP3X_SELF_RESIZE_CTRL) && *val == 0)
180*4882a593Smuzhiyun *val = CIF_RSZ_CTRL_CFG_UPD;
181*4882a593Smuzhiyun writel(*val, hw->base_next_addr + i);
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
rkisp_alloc_buffer(struct rkisp_device * dev,struct rkisp_dummy_buffer * buf)187*4882a593Smuzhiyun int rkisp_alloc_buffer(struct rkisp_device *dev,
188*4882a593Smuzhiyun struct rkisp_dummy_buffer *buf)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun unsigned long attrs = buf->is_need_vaddr ? 0 : DMA_ATTR_NO_KERNEL_MAPPING;
191*4882a593Smuzhiyun const struct vb2_mem_ops *g_ops = dev->hw_dev->mem_ops;
192*4882a593Smuzhiyun struct sg_table *sg_tbl;
193*4882a593Smuzhiyun void *mem_priv;
194*4882a593Smuzhiyun int ret = 0;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun mutex_lock(&dev->buf_lock);
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun if (!buf->size) {
199*4882a593Smuzhiyun ret = -EINVAL;
200*4882a593Smuzhiyun goto err;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun if (dev->hw_dev->is_dma_contig)
204*4882a593Smuzhiyun attrs |= DMA_ATTR_FORCE_CONTIGUOUS;
205*4882a593Smuzhiyun buf->size = PAGE_ALIGN(buf->size);
206*4882a593Smuzhiyun mem_priv = g_ops->alloc(dev->hw_dev->dev, attrs, buf->size,
207*4882a593Smuzhiyun DMA_BIDIRECTIONAL, GFP_KERNEL | GFP_DMA32);
208*4882a593Smuzhiyun if (IS_ERR_OR_NULL(mem_priv)) {
209*4882a593Smuzhiyun ret = -ENOMEM;
210*4882a593Smuzhiyun goto err;
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun buf->mem_priv = mem_priv;
214*4882a593Smuzhiyun if (dev->hw_dev->is_dma_sg_ops) {
215*4882a593Smuzhiyun sg_tbl = (struct sg_table *)g_ops->cookie(mem_priv);
216*4882a593Smuzhiyun buf->dma_addr = sg_dma_address(sg_tbl->sgl);
217*4882a593Smuzhiyun g_ops->prepare(mem_priv);
218*4882a593Smuzhiyun } else {
219*4882a593Smuzhiyun buf->dma_addr = *((dma_addr_t *)g_ops->cookie(mem_priv));
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun if (buf->is_need_vaddr)
222*4882a593Smuzhiyun buf->vaddr = g_ops->vaddr(mem_priv);
223*4882a593Smuzhiyun if (buf->is_need_dbuf) {
224*4882a593Smuzhiyun buf->dbuf = g_ops->get_dmabuf(mem_priv, O_RDWR);
225*4882a593Smuzhiyun if (buf->is_need_dmafd) {
226*4882a593Smuzhiyun buf->dma_fd = dma_buf_fd(buf->dbuf, O_CLOEXEC);
227*4882a593Smuzhiyun if (buf->dma_fd < 0) {
228*4882a593Smuzhiyun dma_buf_put(buf->dbuf);
229*4882a593Smuzhiyun ret = buf->dma_fd;
230*4882a593Smuzhiyun goto err;
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun get_dma_buf(buf->dbuf);
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
236*4882a593Smuzhiyun "%s buf:0x%x~0x%x size:%d\n", __func__,
237*4882a593Smuzhiyun (u32)buf->dma_addr, (u32)buf->dma_addr + buf->size, buf->size);
238*4882a593Smuzhiyun mutex_unlock(&dev->buf_lock);
239*4882a593Smuzhiyun return ret;
240*4882a593Smuzhiyun err:
241*4882a593Smuzhiyun mutex_unlock(&dev->buf_lock);
242*4882a593Smuzhiyun dev_err(dev->dev, "%s failed ret:%d\n", __func__, ret);
243*4882a593Smuzhiyun return ret;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun
rkisp_free_buffer(struct rkisp_device * dev,struct rkisp_dummy_buffer * buf)246*4882a593Smuzhiyun void rkisp_free_buffer(struct rkisp_device *dev,
247*4882a593Smuzhiyun struct rkisp_dummy_buffer *buf)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun const struct vb2_mem_ops *g_ops = dev->hw_dev->mem_ops;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun mutex_lock(&dev->buf_lock);
252*4882a593Smuzhiyun if (buf && buf->mem_priv) {
253*4882a593Smuzhiyun v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
254*4882a593Smuzhiyun "%s buf:0x%x~0x%x\n", __func__,
255*4882a593Smuzhiyun (u32)buf->dma_addr, (u32)buf->dma_addr + buf->size);
256*4882a593Smuzhiyun if (buf->dbuf)
257*4882a593Smuzhiyun dma_buf_put(buf->dbuf);
258*4882a593Smuzhiyun g_ops->put(buf->mem_priv);
259*4882a593Smuzhiyun buf->size = 0;
260*4882a593Smuzhiyun buf->dbuf = NULL;
261*4882a593Smuzhiyun buf->vaddr = NULL;
262*4882a593Smuzhiyun buf->mem_priv = NULL;
263*4882a593Smuzhiyun buf->is_need_dbuf = false;
264*4882a593Smuzhiyun buf->is_need_vaddr = false;
265*4882a593Smuzhiyun buf->is_need_dmafd = false;
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun mutex_unlock(&dev->buf_lock);
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun
rkisp_prepare_buffer(struct rkisp_device * dev,struct rkisp_dummy_buffer * buf)270*4882a593Smuzhiyun void rkisp_prepare_buffer(struct rkisp_device *dev,
271*4882a593Smuzhiyun struct rkisp_dummy_buffer *buf)
272*4882a593Smuzhiyun {
273*4882a593Smuzhiyun const struct vb2_mem_ops *g_ops = dev->hw_dev->mem_ops;
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun if (buf && buf->mem_priv)
276*4882a593Smuzhiyun g_ops->prepare(buf->mem_priv);
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun
rkisp_finish_buffer(struct rkisp_device * dev,struct rkisp_dummy_buffer * buf)279*4882a593Smuzhiyun void rkisp_finish_buffer(struct rkisp_device *dev,
280*4882a593Smuzhiyun struct rkisp_dummy_buffer *buf)
281*4882a593Smuzhiyun {
282*4882a593Smuzhiyun const struct vb2_mem_ops *g_ops = dev->hw_dev->mem_ops;
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun if (buf && buf->mem_priv)
285*4882a593Smuzhiyun g_ops->finish(buf->mem_priv);
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
rkisp_attach_hw(struct rkisp_device * isp)288*4882a593Smuzhiyun int rkisp_attach_hw(struct rkisp_device *isp)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun struct device_node *np;
291*4882a593Smuzhiyun struct platform_device *pdev;
292*4882a593Smuzhiyun struct rkisp_hw_dev *hw;
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun np = of_parse_phandle(isp->dev->of_node, "rockchip,hw", 0);
295*4882a593Smuzhiyun if (!np || !of_device_is_available(np)) {
296*4882a593Smuzhiyun dev_err(isp->dev, "failed to get isp hw node\n");
297*4882a593Smuzhiyun return -ENODEV;
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun pdev = of_find_device_by_node(np);
301*4882a593Smuzhiyun of_node_put(np);
302*4882a593Smuzhiyun if (!pdev) {
303*4882a593Smuzhiyun dev_err(isp->dev, "failed to get isp hw from node\n");
304*4882a593Smuzhiyun return -ENODEV;
305*4882a593Smuzhiyun }
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun hw = platform_get_drvdata(pdev);
308*4882a593Smuzhiyun if (!hw) {
309*4882a593Smuzhiyun dev_err(isp->dev, "failed attach isp hw\n");
310*4882a593Smuzhiyun return -EINVAL;
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun isp->dev_id = hw->dev_num;
314*4882a593Smuzhiyun hw->isp[hw->dev_num] = isp;
315*4882a593Smuzhiyun hw->dev_num++;
316*4882a593Smuzhiyun isp->hw_dev = hw;
317*4882a593Smuzhiyun isp->isp_ver = hw->isp_ver;
318*4882a593Smuzhiyun isp->base_addr = hw->base_addr;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun return 0;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun
rkisp_alloc_page_dummy_buf(struct rkisp_device * dev,u32 size)323*4882a593Smuzhiyun static int rkisp_alloc_page_dummy_buf(struct rkisp_device *dev, u32 size)
324*4882a593Smuzhiyun {
325*4882a593Smuzhiyun struct rkisp_hw_dev *hw = dev->hw_dev;
326*4882a593Smuzhiyun struct rkisp_dummy_buffer *dummy_buf = &hw->dummy_buf;
327*4882a593Smuzhiyun u32 i, n_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
328*4882a593Smuzhiyun struct page *page = NULL, **pages = NULL;
329*4882a593Smuzhiyun struct sg_table *sg = NULL;
330*4882a593Smuzhiyun int ret = -ENOMEM;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun page = alloc_pages(GFP_KERNEL | GFP_DMA32, 0);
333*4882a593Smuzhiyun if (!page)
334*4882a593Smuzhiyun goto err;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun pages = kvmalloc_array(n_pages, sizeof(struct page *), GFP_KERNEL);
337*4882a593Smuzhiyun if (!pages)
338*4882a593Smuzhiyun goto free_page;
339*4882a593Smuzhiyun for (i = 0; i < n_pages; i++)
340*4882a593Smuzhiyun pages[i] = page;
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun sg = kmalloc(sizeof(struct sg_table), GFP_KERNEL);
343*4882a593Smuzhiyun if (!sg)
344*4882a593Smuzhiyun goto free_pages;
345*4882a593Smuzhiyun ret = sg_alloc_table_from_pages(sg, pages, n_pages, 0,
346*4882a593Smuzhiyun n_pages << PAGE_SHIFT, GFP_KERNEL);
347*4882a593Smuzhiyun if (ret)
348*4882a593Smuzhiyun goto free_sg;
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun ret = dma_map_sg(hw->dev, sg->sgl, sg->nents, DMA_BIDIRECTIONAL);
351*4882a593Smuzhiyun dummy_buf->dma_addr = sg_dma_address(sg->sgl);
352*4882a593Smuzhiyun dummy_buf->mem_priv = sg;
353*4882a593Smuzhiyun dummy_buf->pages = pages;
354*4882a593Smuzhiyun v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
355*4882a593Smuzhiyun "%s buf:0x%x map cnt:%d size:%d\n", __func__,
356*4882a593Smuzhiyun (u32)dummy_buf->dma_addr, ret, size);
357*4882a593Smuzhiyun return 0;
358*4882a593Smuzhiyun free_sg:
359*4882a593Smuzhiyun kfree(sg);
360*4882a593Smuzhiyun free_pages:
361*4882a593Smuzhiyun kvfree(pages);
362*4882a593Smuzhiyun free_page:
363*4882a593Smuzhiyun __free_pages(page, 0);
364*4882a593Smuzhiyun err:
365*4882a593Smuzhiyun return ret;
366*4882a593Smuzhiyun }
367*4882a593Smuzhiyun
rkisp_free_page_dummy_buf(struct rkisp_device * dev)368*4882a593Smuzhiyun static void rkisp_free_page_dummy_buf(struct rkisp_device *dev)
369*4882a593Smuzhiyun {
370*4882a593Smuzhiyun struct rkisp_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
371*4882a593Smuzhiyun struct sg_table *sg = dummy_buf->mem_priv;
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun if (!sg)
374*4882a593Smuzhiyun return;
375*4882a593Smuzhiyun dma_unmap_sg(dev->hw_dev->dev, sg->sgl, sg->nents, DMA_BIDIRECTIONAL);
376*4882a593Smuzhiyun sg_free_table(sg);
377*4882a593Smuzhiyun kfree(sg);
378*4882a593Smuzhiyun __free_pages(dummy_buf->pages[0], 0);
379*4882a593Smuzhiyun kvfree(dummy_buf->pages);
380*4882a593Smuzhiyun dummy_buf->mem_priv = NULL;
381*4882a593Smuzhiyun dummy_buf->pages = NULL;
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun
rkisp_alloc_common_dummy_buf(struct rkisp_device * dev)384*4882a593Smuzhiyun int rkisp_alloc_common_dummy_buf(struct rkisp_device *dev)
385*4882a593Smuzhiyun {
386*4882a593Smuzhiyun struct rkisp_hw_dev *hw = dev->hw_dev;
387*4882a593Smuzhiyun struct rkisp_dummy_buffer *dummy_buf = &hw->dummy_buf;
388*4882a593Smuzhiyun struct rkisp_stream *stream;
389*4882a593Smuzhiyun struct rkisp_device *isp;
390*4882a593Smuzhiyun u32 i, j, val, size = 0;
391*4882a593Smuzhiyun int ret = 0;
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun if (dummy_buf->mem_priv)
394*4882a593Smuzhiyun goto end;
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun if (hw->max_in.w && hw->max_in.h)
397*4882a593Smuzhiyun size = hw->max_in.w * hw->max_in.h * 2;
398*4882a593Smuzhiyun for (i = 0; i < hw->dev_num; i++) {
399*4882a593Smuzhiyun isp = hw->isp[i];
400*4882a593Smuzhiyun if (!isp || (isp && !isp->is_hw_link))
401*4882a593Smuzhiyun continue;
402*4882a593Smuzhiyun for (j = 0; j < RKISP_MAX_STREAM; j++) {
403*4882a593Smuzhiyun stream = &isp->cap_dev.stream[j];
404*4882a593Smuzhiyun if (!stream->linked)
405*4882a593Smuzhiyun continue;
406*4882a593Smuzhiyun val = stream->out_isp_fmt.fmt_type == FMT_FBC ?
407*4882a593Smuzhiyun stream->out_fmt.plane_fmt[1].sizeimage :
408*4882a593Smuzhiyun stream->out_fmt.plane_fmt[0].bytesperline *
409*4882a593Smuzhiyun stream->out_fmt.height;
410*4882a593Smuzhiyun size = max(size, val);
411*4882a593Smuzhiyun }
412*4882a593Smuzhiyun }
413*4882a593Smuzhiyun if (size == 0)
414*4882a593Smuzhiyun goto end;
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun if (hw->is_mmu) {
417*4882a593Smuzhiyun ret = rkisp_alloc_page_dummy_buf(dev, size);
418*4882a593Smuzhiyun goto end;
419*4882a593Smuzhiyun }
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun dummy_buf->size = size;
422*4882a593Smuzhiyun ret = rkisp_alloc_buffer(dev, dummy_buf);
423*4882a593Smuzhiyun if (!ret)
424*4882a593Smuzhiyun v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
425*4882a593Smuzhiyun "%s buf:0x%x size:%d\n", __func__,
426*4882a593Smuzhiyun (u32)dummy_buf->dma_addr, dummy_buf->size);
427*4882a593Smuzhiyun end:
428*4882a593Smuzhiyun if (ret < 0)
429*4882a593Smuzhiyun v4l2_err(&dev->v4l2_dev, "%s failed:%d\n", __func__, ret);
430*4882a593Smuzhiyun return ret;
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun
rkisp_free_common_dummy_buf(struct rkisp_device * dev)433*4882a593Smuzhiyun void rkisp_free_common_dummy_buf(struct rkisp_device *dev)
434*4882a593Smuzhiyun {
435*4882a593Smuzhiyun struct rkisp_hw_dev *hw = dev->hw_dev;
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun if (atomic_read(&hw->refcnt) ||
438*4882a593Smuzhiyun atomic_read(&dev->cap_dev.refcnt) > 1)
439*4882a593Smuzhiyun return;
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun if (hw->is_mmu)
442*4882a593Smuzhiyun rkisp_free_page_dummy_buf(dev);
443*4882a593Smuzhiyun else
444*4882a593Smuzhiyun rkisp_free_buffer(dev, &hw->dummy_buf);
445*4882a593Smuzhiyun }
446