1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020 Rockchip Electronics Co., Ltd. */
3
4 #include <media/v4l2-common.h>
5 #include <media/v4l2-ioctl.h>
6 #include <media/videobuf2-core.h>
7 #include <media/videobuf2-vmalloc.h> /* for ISP params */
8 #include <linux/rk-preisp.h>
9 #include <linux/slab.h>
10 #include "dev.h"
11 #include "regs.h"
12 #include "regs_v2x.h"
13 #include "isp_params_v21.h"
14
15 #define ISP2X_PACK_4BYTE(a, b, c, d) \
16 (((a) & 0xFF) << 0 | ((b) & 0xFF) << 8 | \
17 ((c) & 0xFF) << 16 | ((d) & 0xFF) << 24)
18
19 #define ISP2X_PACK_2SHORT(a, b) \
20 (((a) & 0xFFFF) << 0 | ((b) & 0xFFFF) << 16)
21
22 #define ISP2X_REG_WR_MASK BIT(31) //disable write protect
23 #define ISP21_NOBIG_OVERFLOW_SIZE (2688 * 1536)
24 #define ISP21_AUTO_BIGMODE_WIDTH 2688
25 #define ISP21_VIR2_NOBIG_OVERFLOW_SIZE (1920 * 1080)
26 #define ISP21_VIR2_AUTO_BIGMODE_WIDTH 1920
27 #define ISP21_VIR4_NOBIG_OVERFLOW_SIZE (960 * 540)
28 #define ISP21_VIR4_AUTO_BIGMODE_WIDTH 960
29
30 #define ISP21_VIR2_MAX_WIDTH 3840
31 #define ISP21_VIR2_MAX_SIZE (3840 * 2160)
32 #define ISP21_VIR4_MAX_WIDTH 1920
33 #define ISP21_VIR4_MAX_SIZE (1920 * 1080)
34
35 static void
isp_dpcc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_dpcc_cfg * arg)36 isp_dpcc_config(struct rkisp_isp_params_vdev *params_vdev,
37 const struct isp2x_dpcc_cfg *arg)
38 {
39 u32 value;
40 int i;
41
42 value = rkisp_ioread32(params_vdev, ISP_DPCC0_MODE);
43 value &= ISP_DPCC_EN;
44
45 value |= (arg->stage1_enable & 0x01) << 2 |
46 (arg->grayscale_mode & 0x01) << 1;
47 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_MODE);
48 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_MODE);
49
50 value = (arg->sw_rk_out_sel & 0x03) << 5 |
51 (arg->sw_dpcc_output_sel & 0x01) << 4 |
52 (arg->stage1_rb_3x3 & 0x01) << 3 |
53 (arg->stage1_g_3x3 & 0x01) << 2 |
54 (arg->stage1_incl_rb_center & 0x01) << 1 |
55 (arg->stage1_incl_green_center & 0x01);
56 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_OUTPUT_MODE);
57 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_OUTPUT_MODE);
58
59 value = (arg->stage1_use_fix_set & 0x01) << 3 |
60 (arg->stage1_use_set_3 & 0x01) << 2 |
61 (arg->stage1_use_set_2 & 0x01) << 1 |
62 (arg->stage1_use_set_1 & 0x01);
63 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_SET_USE);
64 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_SET_USE);
65
66 value = (arg->sw_rk_red_blue1_en & 0x01) << 13 |
67 (arg->rg_red_blue1_enable & 0x01) << 12 |
68 (arg->rnd_red_blue1_enable & 0x01) << 11 |
69 (arg->ro_red_blue1_enable & 0x01) << 10 |
70 (arg->lc_red_blue1_enable & 0x01) << 9 |
71 (arg->pg_red_blue1_enable & 0x01) << 8 |
72 (arg->sw_rk_green1_en & 0x01) << 5 |
73 (arg->rg_green1_enable & 0x01) << 4 |
74 (arg->rnd_green1_enable & 0x01) << 3 |
75 (arg->ro_green1_enable & 0x01) << 2 |
76 (arg->lc_green1_enable & 0x01) << 1 |
77 (arg->pg_green1_enable & 0x01);
78 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_METHODS_SET_1);
79 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_METHODS_SET_1);
80
81 value = (arg->sw_rk_red_blue2_en & 0x01) << 13 |
82 (arg->rg_red_blue2_enable & 0x01) << 12 |
83 (arg->rnd_red_blue2_enable & 0x01) << 11 |
84 (arg->ro_red_blue2_enable & 0x01) << 10 |
85 (arg->lc_red_blue2_enable & 0x01) << 9 |
86 (arg->pg_red_blue2_enable & 0x01) << 8 |
87 (arg->sw_rk_green2_en & 0x01) << 5 |
88 (arg->rg_green2_enable & 0x01) << 4 |
89 (arg->rnd_green2_enable & 0x01) << 3 |
90 (arg->ro_green2_enable & 0x01) << 2 |
91 (arg->lc_green2_enable & 0x01) << 1 |
92 (arg->pg_green2_enable & 0x01);
93 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_METHODS_SET_2);
94 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_METHODS_SET_2);
95
96 value = (arg->sw_rk_red_blue3_en & 0x01) << 13 |
97 (arg->rg_red_blue3_enable & 0x01) << 12 |
98 (arg->rnd_red_blue3_enable & 0x01) << 11 |
99 (arg->ro_red_blue3_enable & 0x01) << 10 |
100 (arg->lc_red_blue3_enable & 0x01) << 9 |
101 (arg->pg_red_blue3_enable & 0x01) << 8 |
102 (arg->sw_rk_green3_en & 0x01) << 5 |
103 (arg->rg_green3_enable & 0x01) << 4 |
104 (arg->rnd_green3_enable & 0x01) << 3 |
105 (arg->ro_green3_enable & 0x01) << 2 |
106 (arg->lc_green3_enable & 0x01) << 1 |
107 (arg->pg_green3_enable & 0x01);
108 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_METHODS_SET_3);
109 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_METHODS_SET_3);
110
111 value = ISP2X_PACK_4BYTE(arg->line_thr_1_g, arg->line_thr_1_rb,
112 arg->sw_mindis1_g, arg->sw_mindis1_rb);
113 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_LINE_THRESH_1);
114 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_LINE_THRESH_1);
115
116 value = ISP2X_PACK_4BYTE(arg->line_mad_fac_1_g, arg->line_mad_fac_1_rb,
117 arg->sw_dis_scale_max1, arg->sw_dis_scale_min1);
118 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_LINE_MAD_FAC_1);
119 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_LINE_MAD_FAC_1);
120
121 value = ISP2X_PACK_4BYTE(arg->pg_fac_1_g, arg->pg_fac_1_rb, 0, 0);
122 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_PG_FAC_1);
123 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_PG_FAC_1);
124
125 value = ISP2X_PACK_4BYTE(arg->rnd_thr_1_g, arg->rnd_thr_1_rb, 0, 0);
126 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_RND_THRESH_1);
127 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_RND_THRESH_1);
128
129 value = ISP2X_PACK_4BYTE(arg->rg_fac_1_g, arg->rg_fac_1_rb, 0, 0);
130 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_RG_FAC_1);
131 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_RG_FAC_1);
132
133 value = ISP2X_PACK_4BYTE(arg->line_thr_2_g, arg->line_thr_2_rb,
134 arg->sw_mindis2_g, arg->sw_mindis2_rb);
135 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_LINE_THRESH_2);
136 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_LINE_THRESH_2);
137
138 value = ISP2X_PACK_4BYTE(arg->line_mad_fac_2_g, arg->line_mad_fac_2_rb,
139 arg->sw_dis_scale_max2, arg->sw_dis_scale_min2);
140 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_LINE_MAD_FAC_2);
141 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_LINE_MAD_FAC_2);
142
143 value = ISP2X_PACK_4BYTE(arg->pg_fac_2_g, arg->pg_fac_2_rb, 0, 0);
144 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_PG_FAC_2);
145 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_PG_FAC_2);
146
147 value = ISP2X_PACK_4BYTE(arg->rnd_thr_2_g, arg->rnd_thr_2_rb, 0, 0);
148 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_RND_THRESH_2);
149 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_RND_THRESH_2);
150
151 value = ISP2X_PACK_4BYTE(arg->rg_fac_2_g, arg->rg_fac_2_rb, 0, 0);
152 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_RG_FAC_2);
153 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_RG_FAC_2);
154
155 value = ISP2X_PACK_4BYTE(arg->line_thr_3_g, arg->line_thr_3_rb,
156 arg->sw_mindis3_g, arg->sw_mindis3_rb);
157 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_LINE_THRESH_3);
158 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_LINE_THRESH_3);
159
160 value = ISP2X_PACK_4BYTE(arg->line_mad_fac_3_g, arg->line_mad_fac_3_rb,
161 arg->sw_dis_scale_max3, arg->sw_dis_scale_min3);
162 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_LINE_MAD_FAC_3);
163 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_LINE_MAD_FAC_3);
164
165 value = ISP2X_PACK_4BYTE(arg->pg_fac_3_g, arg->pg_fac_3_rb, 0, 0);
166 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_PG_FAC_3);
167 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_PG_FAC_3);
168
169 value = ISP2X_PACK_4BYTE(arg->rnd_thr_3_g, arg->rnd_thr_3_rb, 0, 0);
170 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_RND_THRESH_3);
171 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_RND_THRESH_3);
172
173 value = ISP2X_PACK_4BYTE(arg->rg_fac_3_g, arg->rg_fac_3_rb, 0, 0);
174 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_RG_FAC_3);
175 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_RG_FAC_3);
176
177 value = (arg->ro_lim_3_rb & 0x03) << 10 |
178 (arg->ro_lim_3_g & 0x03) << 8 |
179 (arg->ro_lim_2_rb & 0x03) << 6 |
180 (arg->ro_lim_2_g & 0x03) << 4 |
181 (arg->ro_lim_1_rb & 0x03) << 2 |
182 (arg->ro_lim_1_g & 0x03);
183 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_RO_LIMITS);
184 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_RO_LIMITS);
185
186 value = (arg->rnd_offs_3_rb & 0x03) << 10 |
187 (arg->rnd_offs_3_g & 0x03) << 8 |
188 (arg->rnd_offs_2_rb & 0x03) << 6 |
189 (arg->rnd_offs_2_g & 0x03) << 4 |
190 (arg->rnd_offs_1_rb & 0x03) << 2 |
191 (arg->rnd_offs_1_g & 0x03);
192 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_RND_OFFS);
193 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_RND_OFFS);
194
195 value = (arg->bpt_rb_3x3 & 0x01) << 11 |
196 (arg->bpt_g_3x3 & 0x01) << 10 |
197 (arg->bpt_incl_rb_center & 0x01) << 9 |
198 (arg->bpt_incl_green_center & 0x01) << 8 |
199 (arg->bpt_use_fix_set & 0x01) << 7 |
200 (arg->bpt_use_set_3 & 0x01) << 6 |
201 (arg->bpt_use_set_2 & 0x01) << 5 |
202 (arg->bpt_use_set_1 & 0x01) << 4 |
203 (arg->bpt_cor_en & 0x01) << 1 |
204 (arg->bpt_det_en & 0x01);
205 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_BPT_CTRL);
206 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_BPT_CTRL);
207
208 rkisp_iowrite32(params_vdev, arg->bp_number, ISP_DPCC0_BPT_NUMBER);
209 rkisp_iowrite32(params_vdev, arg->bp_number, ISP_DPCC1_BPT_NUMBER);
210 rkisp_iowrite32(params_vdev, arg->bp_table_addr, ISP_DPCC0_BPT_ADDR);
211 rkisp_iowrite32(params_vdev, arg->bp_table_addr, ISP_DPCC1_BPT_ADDR);
212
213 value = ISP2X_PACK_2SHORT(arg->bpt_h_addr, arg->bpt_v_addr);
214 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_BPT_DATA);
215 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_BPT_DATA);
216
217 rkisp_iowrite32(params_vdev, arg->bp_cnt, ISP_DPCC0_BP_CNT);
218 rkisp_iowrite32(params_vdev, arg->bp_cnt, ISP_DPCC1_BP_CNT);
219
220 rkisp_iowrite32(params_vdev, arg->sw_pdaf_en, ISP_DPCC0_PDAF_EN);
221 rkisp_iowrite32(params_vdev, arg->sw_pdaf_en, ISP_DPCC1_PDAF_EN);
222
223 value = 0;
224 for (i = 0; i < ISP2X_DPCC_PDAF_POINT_NUM; i++)
225 value |= (arg->pdaf_point_en[i] & 0x01) << i;
226 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_PDAF_POINT_EN);
227 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_PDAF_POINT_EN);
228
229 value = ISP2X_PACK_2SHORT(arg->pdaf_offsetx, arg->pdaf_offsety);
230 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_PDAF_OFFSET);
231 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_PDAF_OFFSET);
232
233 value = ISP2X_PACK_2SHORT(arg->pdaf_wrapx, arg->pdaf_wrapy);
234 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_PDAF_WRAP);
235 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_PDAF_WRAP);
236
237 value = ISP2X_PACK_2SHORT(arg->pdaf_wrapx_num, arg->pdaf_wrapy_num);
238 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_PDAF_SCOPE);
239 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_PDAF_SCOPE);
240
241 for (i = 0; i < ISP2X_DPCC_PDAF_POINT_NUM / 2; i++) {
242 value = ISP2X_PACK_4BYTE(arg->point[2 * i].x, arg->point[2 * i].y,
243 arg->point[2 * i + 1].x, arg->point[2 * i + 1].y);
244 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_PDAF_POINT_0 + 4 * i);
245 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_PDAF_POINT_0 + 4 * i);
246 }
247
248 rkisp_iowrite32(params_vdev, arg->pdaf_forward_med, ISP_DPCC0_PDAF_FORWARD_MED);
249 rkisp_iowrite32(params_vdev, arg->pdaf_forward_med, ISP_DPCC1_PDAF_FORWARD_MED);
250 }
251
252 static void
isp_dpcc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)253 isp_dpcc_enable(struct rkisp_isp_params_vdev *params_vdev,
254 bool en)
255 {
256 u32 value;
257
258 value = rkisp_ioread32(params_vdev, ISP_DPCC0_MODE);
259 value &= ~ISP_DPCC_EN;
260
261 if (en)
262 value |= ISP_DPCC_EN;
263 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_MODE);
264 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_MODE);
265 }
266
267 static void
isp_bls_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_bls_cfg * arg)268 isp_bls_config(struct rkisp_isp_params_vdev *params_vdev,
269 const struct isp21_bls_cfg *arg)
270 {
271 const struct isp2x_bls_fixed_val *pval;
272 u32 new_control, value;
273
274 new_control = rkisp_ioread32(params_vdev, ISP_BLS_CTRL);
275 new_control &= ISP_BLS_ENA;
276
277 pval = &arg->bls1_val;
278 if (arg->bls1_en) {
279 new_control |= ISP_BLS_BLS1_EN;
280
281 switch (params_vdev->raw_type) {
282 case RAW_BGGR:
283 rkisp_iowrite32(params_vdev,
284 pval->r, ISP_BLS1_D_FIXED);
285 rkisp_iowrite32(params_vdev,
286 pval->gr, ISP_BLS1_C_FIXED);
287 rkisp_iowrite32(params_vdev,
288 pval->gb, ISP_BLS1_B_FIXED);
289 rkisp_iowrite32(params_vdev,
290 pval->b, ISP_BLS1_A_FIXED);
291 break;
292 case RAW_GBRG:
293 rkisp_iowrite32(params_vdev,
294 pval->r, ISP_BLS1_C_FIXED);
295 rkisp_iowrite32(params_vdev,
296 pval->gr, ISP_BLS1_D_FIXED);
297 rkisp_iowrite32(params_vdev,
298 pval->gb, ISP_BLS1_A_FIXED);
299 rkisp_iowrite32(params_vdev,
300 pval->b, ISP_BLS1_B_FIXED);
301 break;
302 case RAW_GRBG:
303 rkisp_iowrite32(params_vdev,
304 pval->r, ISP_BLS1_B_FIXED);
305 rkisp_iowrite32(params_vdev,
306 pval->gr, ISP_BLS1_A_FIXED);
307 rkisp_iowrite32(params_vdev,
308 pval->gb, ISP_BLS1_D_FIXED);
309 rkisp_iowrite32(params_vdev,
310 pval->b, ISP_BLS1_C_FIXED);
311 break;
312 case RAW_RGGB:
313 rkisp_iowrite32(params_vdev,
314 pval->r, ISP_BLS1_A_FIXED);
315 rkisp_iowrite32(params_vdev,
316 pval->gr, ISP_BLS1_B_FIXED);
317 rkisp_iowrite32(params_vdev,
318 pval->gb, ISP_BLS1_C_FIXED);
319 rkisp_iowrite32(params_vdev,
320 pval->b, ISP_BLS1_D_FIXED);
321 break;
322 default:
323 break;
324 }
325 }
326
327 /* fixed subtraction values */
328 pval = &arg->fixed_val;
329 if (!arg->enable_auto) {
330 switch (params_vdev->raw_type) {
331 case RAW_BGGR:
332 rkisp_iowrite32(params_vdev,
333 pval->r, ISP_BLS_D_FIXED);
334 rkisp_iowrite32(params_vdev,
335 pval->gr, ISP_BLS_C_FIXED);
336 rkisp_iowrite32(params_vdev,
337 pval->gb, ISP_BLS_B_FIXED);
338 rkisp_iowrite32(params_vdev,
339 pval->b, ISP_BLS_A_FIXED);
340 break;
341 case RAW_GBRG:
342 rkisp_iowrite32(params_vdev,
343 pval->r, ISP_BLS_C_FIXED);
344 rkisp_iowrite32(params_vdev,
345 pval->gr, ISP_BLS_D_FIXED);
346 rkisp_iowrite32(params_vdev,
347 pval->gb, ISP_BLS_A_FIXED);
348 rkisp_iowrite32(params_vdev,
349 pval->b, ISP_BLS_B_FIXED);
350 break;
351 case RAW_GRBG:
352 rkisp_iowrite32(params_vdev,
353 pval->r, ISP_BLS_B_FIXED);
354 rkisp_iowrite32(params_vdev,
355 pval->gr, ISP_BLS_A_FIXED);
356 rkisp_iowrite32(params_vdev,
357 pval->gb, ISP_BLS_D_FIXED);
358 rkisp_iowrite32(params_vdev,
359 pval->b, ISP_BLS_C_FIXED);
360 break;
361 case RAW_RGGB:
362 rkisp_iowrite32(params_vdev,
363 pval->r, ISP_BLS_A_FIXED);
364 rkisp_iowrite32(params_vdev,
365 pval->gr, ISP_BLS_B_FIXED);
366 rkisp_iowrite32(params_vdev,
367 pval->gb, ISP_BLS_C_FIXED);
368 rkisp_iowrite32(params_vdev,
369 pval->b, ISP_BLS_D_FIXED);
370 break;
371 default:
372 break;
373 }
374 } else {
375 if (arg->en_windows & BIT(1)) {
376 rkisp_iowrite32(params_vdev, arg->bls_window2.h_offs,
377 ISP_BLS_H2_START);
378 value = arg->bls_window2.h_offs + arg->bls_window2.h_size;
379 rkisp_iowrite32(params_vdev, value, ISP_BLS_H2_STOP);
380 rkisp_iowrite32(params_vdev, arg->bls_window2.v_offs,
381 ISP_BLS_V2_START);
382 value = arg->bls_window2.v_offs + arg->bls_window2.v_size;
383 rkisp_iowrite32(params_vdev, value, ISP_BLS_V2_STOP);
384 new_control |= ISP_BLS_WINDOW_2;
385 }
386
387 if (arg->en_windows & BIT(0)) {
388 rkisp_iowrite32(params_vdev, arg->bls_window1.h_offs,
389 ISP_BLS_H1_START);
390 value = arg->bls_window1.h_offs + arg->bls_window1.h_size;
391 rkisp_iowrite32(params_vdev, value, ISP_BLS_H1_STOP);
392 rkisp_iowrite32(params_vdev, arg->bls_window1.v_offs,
393 ISP_BLS_V1_START);
394 value = arg->bls_window1.v_offs + arg->bls_window1.v_size;
395 rkisp_iowrite32(params_vdev, value, ISP_BLS_V1_STOP);
396 new_control |= ISP_BLS_WINDOW_1;
397 }
398
399 rkisp_iowrite32(params_vdev, arg->bls_samples,
400 ISP_BLS_SAMPLES);
401
402 new_control |= ISP_BLS_MODE_MEASURED;
403 }
404 rkisp_iowrite32(params_vdev, new_control, ISP_BLS_CTRL);
405 }
406
407 static void
isp_bls_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)408 isp_bls_enable(struct rkisp_isp_params_vdev *params_vdev,
409 bool en)
410 {
411 u32 new_control;
412
413 new_control = rkisp_ioread32(params_vdev, ISP_BLS_CTRL);
414 if (en)
415 new_control |= ISP_BLS_ENA;
416 else
417 new_control &= ~ISP_BLS_ENA;
418 rkisp_iowrite32(params_vdev, new_control, ISP_BLS_CTRL);
419 }
420
421 static void
isp_sdg_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_sdg_cfg * arg)422 isp_sdg_config(struct rkisp_isp_params_vdev *params_vdev,
423 const struct isp2x_sdg_cfg *arg)
424 {
425 int i;
426
427 rkisp_iowrite32(params_vdev,
428 arg->xa_pnts.gamma_dx0, ISP_GAMMA_DX_LO);
429 rkisp_iowrite32(params_vdev,
430 arg->xa_pnts.gamma_dx1, ISP_GAMMA_DX_HI);
431
432 for (i = 0; i < ISP2X_DEGAMMA_CURVE_SIZE; i++) {
433 rkisp_iowrite32(params_vdev, arg->curve_r.gamma_y[i],
434 ISP_GAMMA_R_Y_0 + i * 4);
435 rkisp_iowrite32(params_vdev, arg->curve_g.gamma_y[i],
436 ISP_GAMMA_G_Y_0 + i * 4);
437 rkisp_iowrite32(params_vdev, arg->curve_b.gamma_y[i],
438 ISP_GAMMA_B_Y_0 + i * 4);
439 }
440 }
441
442 static void
isp_sdg_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)443 isp_sdg_enable(struct rkisp_isp_params_vdev *params_vdev,
444 bool en)
445 {
446 if (en) {
447 isp_param_set_bits(params_vdev,
448 CIF_ISP_CTRL,
449 CIF_ISP_CTRL_ISP_GAMMA_IN_ENA);
450 } else {
451 isp_param_clear_bits(params_vdev,
452 CIF_ISP_CTRL,
453 CIF_ISP_CTRL_ISP_GAMMA_IN_ENA);
454 }
455 }
456
457 static void __maybe_unused
isp_lsc_matrix_cfg_sram(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_lsc_cfg * pconfig,bool is_check)458 isp_lsc_matrix_cfg_sram(struct rkisp_isp_params_vdev *params_vdev,
459 const struct isp2x_lsc_cfg *pconfig, bool is_check)
460 {
461 int i, j;
462 unsigned int sram_addr;
463 unsigned int data;
464
465 if (is_check &&
466 !(rkisp_ioread32(params_vdev, ISP_LSC_CTRL) & ISP_LSC_EN))
467 return;
468
469 /* CIF_ISP_LSC_TABLE_ADDRESS_153 = ( 17 * 18 ) >> 1 */
470 sram_addr = CIF_ISP_LSC_TABLE_ADDRESS_0;
471 rkisp_write(params_vdev->dev, ISP_LSC_R_TABLE_ADDR, sram_addr, true);
472 rkisp_write(params_vdev->dev, ISP_LSC_GR_TABLE_ADDR, sram_addr, true);
473 rkisp_write(params_vdev->dev, ISP_LSC_GB_TABLE_ADDR, sram_addr, true);
474 rkisp_write(params_vdev->dev, ISP_LSC_B_TABLE_ADDR, sram_addr, true);
475
476 /* program data tables (table size is 9 * 17 = 153) */
477 for (i = 0; i < CIF_ISP_LSC_SECTORS_MAX * CIF_ISP_LSC_SECTORS_MAX;
478 i += CIF_ISP_LSC_SECTORS_MAX) {
479 /*
480 * 17 sectors with 2 values in one DWORD = 9
481 * DWORDs (2nd value of last DWORD unused)
482 */
483 for (j = 0; j < CIF_ISP_LSC_SECTORS_MAX - 1; j += 2) {
484 data = ISP_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i + j],
485 pconfig->r_data_tbl[i + j + 1]);
486 rkisp_write(params_vdev->dev, ISP_LSC_R_TABLE_DATA, data, true);
487
488 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i + j],
489 pconfig->gr_data_tbl[i + j + 1]);
490 rkisp_write(params_vdev->dev, ISP_LSC_GR_TABLE_DATA, data, true);
491
492 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i + j],
493 pconfig->gb_data_tbl[i + j + 1]);
494 rkisp_write(params_vdev->dev, ISP_LSC_GB_TABLE_DATA, data, true);
495
496 data = ISP_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i + j],
497 pconfig->b_data_tbl[i + j + 1]);
498 rkisp_write(params_vdev->dev, ISP_LSC_B_TABLE_DATA, data, true);
499 }
500
501 data = ISP_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i + j], 0);
502 rkisp_write(params_vdev->dev, ISP_LSC_R_TABLE_DATA, data, true);
503
504 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i + j], 0);
505 rkisp_write(params_vdev->dev, ISP_LSC_GR_TABLE_DATA, data, true);
506
507 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i + j], 0);
508 rkisp_write(params_vdev->dev, ISP_LSC_GB_TABLE_DATA, data, true);
509
510 data = ISP_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i + j], 0);
511 rkisp_write(params_vdev->dev, ISP_LSC_B_TABLE_DATA, data, true);
512 }
513 }
514
515 static void __maybe_unused
isp_lsc_matrix_cfg_ddr(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_lsc_cfg * pconfig)516 isp_lsc_matrix_cfg_ddr(struct rkisp_isp_params_vdev *params_vdev,
517 const struct isp2x_lsc_cfg *pconfig)
518 {
519 struct rkisp_isp_params_val_v21 *priv_val;
520 u32 data, buf_idx, *vaddr[4], index[4];
521 void *buf_vaddr;
522 int i, j;
523
524 memset(&index[0], 0, sizeof(index));
525 priv_val = (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
526 buf_idx = (priv_val->buf_lsclut_idx++) % RKISP_PARAM_LSC_LUT_BUF_NUM;
527 buf_vaddr = priv_val->buf_lsclut[buf_idx].vaddr;
528
529 vaddr[0] = buf_vaddr;
530 vaddr[1] = buf_vaddr + RKISP_PARAM_LSC_LUT_TBL_SIZE;
531 vaddr[2] = buf_vaddr + RKISP_PARAM_LSC_LUT_TBL_SIZE * 2;
532 vaddr[3] = buf_vaddr + RKISP_PARAM_LSC_LUT_TBL_SIZE * 3;
533
534 /* program data tables (table size is 9 * 17 = 153) */
535 for (i = 0; i < CIF_ISP_LSC_SECTORS_MAX * CIF_ISP_LSC_SECTORS_MAX;
536 i += CIF_ISP_LSC_SECTORS_MAX) {
537 /*
538 * 17 sectors with 2 values in one DWORD = 9
539 * DWORDs (2nd value of last DWORD unused)
540 */
541 for (j = 0; j < CIF_ISP_LSC_SECTORS_MAX - 1; j += 2) {
542 data = ISP_ISP_LSC_TABLE_DATA(
543 pconfig->r_data_tbl[i + j],
544 pconfig->r_data_tbl[i + j + 1]);
545 vaddr[0][index[0]++] = data;
546
547 data = ISP_ISP_LSC_TABLE_DATA(
548 pconfig->gr_data_tbl[i + j],
549 pconfig->gr_data_tbl[i + j + 1]);
550 vaddr[1][index[1]++] = data;
551
552 data = ISP_ISP_LSC_TABLE_DATA(
553 pconfig->b_data_tbl[i + j],
554 pconfig->b_data_tbl[i + j + 1]);
555 vaddr[2][index[2]++] = data;
556
557 data = ISP_ISP_LSC_TABLE_DATA(
558 pconfig->gb_data_tbl[i + j],
559 pconfig->gb_data_tbl[i + j + 1]);
560 vaddr[3][index[3]++] = data;
561 }
562
563 data = ISP_ISP_LSC_TABLE_DATA(
564 pconfig->r_data_tbl[i + j],
565 0);
566 vaddr[0][index[0]++] = data;
567
568 data = ISP_ISP_LSC_TABLE_DATA(
569 pconfig->gr_data_tbl[i + j],
570 0);
571 vaddr[1][index[1]++] = data;
572
573 data = ISP_ISP_LSC_TABLE_DATA(
574 pconfig->b_data_tbl[i + j],
575 0);
576 vaddr[2][index[2]++] = data;
577
578 data = ISP_ISP_LSC_TABLE_DATA(
579 pconfig->gb_data_tbl[i + j],
580 0);
581 vaddr[3][index[3]++] = data;
582 }
583 rkisp_prepare_buffer(params_vdev->dev, &priv_val->buf_lsclut[buf_idx]);
584 data = priv_val->buf_lsclut[buf_idx].dma_addr;
585 rkisp_iowrite32(params_vdev, data, MI_LUT_LSC_RD_BASE);
586 rkisp_iowrite32(params_vdev, RKISP_PARAM_LSC_LUT_BUF_SIZE, MI_LUT_LSC_RD_WSIZE);
587 }
588
589 static void
isp_lsc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_lsc_cfg * arg)590 isp_lsc_config(struct rkisp_isp_params_vdev *params_vdev,
591 const struct isp2x_lsc_cfg *arg)
592 {
593 struct isp21_isp_params_cfg *params_rec = params_vdev->isp21_params;
594 struct rkisp_device *dev = params_vdev->dev;
595 unsigned int data;
596 u32 lsc_ctrl;
597 int i;
598
599 /* To config must be off , store the current status firstly */
600 lsc_ctrl = rkisp_ioread32(params_vdev, ISP_LSC_CTRL);
601 isp_param_clear_bits(params_vdev, ISP_LSC_CTRL, ISP_LSC_EN);
602 /* online mode lsc lut load from ddr quick for some sensor VB short
603 * readback mode lsc lut AHB config to sram, once for single device,
604 * need record to switch for multi-device.
605 */
606 if (!IS_HDR_RDBK(dev->rd_mode))
607 isp_lsc_matrix_cfg_ddr(params_vdev, arg);
608 else if (dev->hw_dev->is_single)
609 isp_lsc_matrix_cfg_sram(params_vdev, arg, false);
610 else
611 params_rec->others.lsc_cfg = *arg;
612
613 for (i = 0; i < 4; i++) {
614 /* program x size tables */
615 data = CIF_ISP_LSC_SECT_SIZE(arg->x_size_tbl[i * 2],
616 arg->x_size_tbl[i * 2 + 1]);
617 rkisp_iowrite32(params_vdev, data,
618 ISP_LSC_XSIZE_01 + i * 4);
619
620 /* program x grad tables */
621 data = CIF_ISP_LSC_SECT_SIZE(arg->x_grad_tbl[i * 2],
622 arg->x_grad_tbl[i * 2 + 1]);
623 rkisp_iowrite32(params_vdev, data,
624 ISP_LSC_XGRAD_01 + i * 4);
625
626 /* program y size tables */
627 data = CIF_ISP_LSC_SECT_SIZE(arg->y_size_tbl[i * 2],
628 arg->y_size_tbl[i * 2 + 1]);
629 rkisp_iowrite32(params_vdev, data,
630 ISP_LSC_YSIZE_01 + i * 4);
631
632 /* program y grad tables */
633 data = CIF_ISP_LSC_SECT_SIZE(arg->y_grad_tbl[i * 2],
634 arg->y_grad_tbl[i * 2 + 1]);
635 rkisp_iowrite32(params_vdev, data,
636 ISP_LSC_YGRAD_01 + i * 4);
637 }
638
639 /* restore the lsc ctrl status */
640 if (lsc_ctrl & ISP_LSC_EN) {
641 if (!IS_HDR_RDBK(dev->rd_mode))
642 lsc_ctrl |= ISP_LSC_LUT_EN;
643 isp_param_set_bits(params_vdev, ISP_LSC_CTRL, lsc_ctrl);
644 } else {
645 isp_param_clear_bits(params_vdev, ISP_LSC_CTRL, ISP_LSC_EN);
646 }
647 }
648
649 static void
isp_lsc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)650 isp_lsc_enable(struct rkisp_isp_params_vdev *params_vdev,
651 bool en)
652 {
653 struct rkisp_device *dev = params_vdev->dev;
654 u32 val = ISP_LSC_EN;
655
656 if (!IS_HDR_RDBK(dev->rd_mode))
657 val |= ISP_LSC_LUT_EN;
658
659 if (en)
660 isp_param_set_bits(params_vdev, ISP_LSC_CTRL, val);
661 else
662 isp_param_clear_bits(params_vdev, ISP_LSC_CTRL, ISP_LSC_EN);
663 }
664
665 static void
isp_debayer_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_debayer_cfg * arg)666 isp_debayer_config(struct rkisp_isp_params_vdev *params_vdev,
667 const struct isp2x_debayer_cfg *arg)
668 {
669 u32 value;
670
671 value = rkisp_ioread32(params_vdev, ISP_DEBAYER_CONTROL);
672 value &= ISP_DEBAYER_EN;
673
674 value |= (arg->filter_c_en & 0x01) << 8 |
675 (arg->filter_g_en & 0x01) << 4;
676 rkisp_iowrite32(params_vdev, value, ISP_DEBAYER_CONTROL);
677
678 value = (arg->thed1 & 0x0F) << 12 |
679 (arg->thed0 & 0x0F) << 8 |
680 (arg->dist_scale & 0x0F) << 4 |
681 (arg->max_ratio & 0x07) << 1 |
682 (arg->clip_en & 0x01);
683 rkisp_iowrite32(params_vdev, value, ISP_DEBAYER_G_INTERP);
684
685 value = (arg->filter1_coe5 & 0x0F) << 16 |
686 (arg->filter1_coe4 & 0x0F) << 12 |
687 (arg->filter1_coe3 & 0x0F) << 8 |
688 (arg->filter1_coe2 & 0x0F) << 4 |
689 (arg->filter1_coe1 & 0x0F);
690 rkisp_iowrite32(params_vdev, value, ISP_DEBAYER_G_INTERP_FILTER1);
691
692 value = (arg->filter2_coe5 & 0x0F) << 16 |
693 (arg->filter2_coe4 & 0x0F) << 12 |
694 (arg->filter2_coe3 & 0x0F) << 8 |
695 (arg->filter2_coe2 & 0x0F) << 4 |
696 (arg->filter2_coe1 & 0x0F);
697 rkisp_iowrite32(params_vdev, value, ISP_DEBAYER_G_INTERP_FILTER2);
698
699 value = (arg->hf_offset & 0xFFFF) << 16 |
700 (arg->gain_offset & 0x0F) << 8 |
701 (arg->offset & 0x1F);
702 rkisp_iowrite32(params_vdev, value, ISP_DEBAYER_G_FILTER);
703
704 value = (arg->shift_num & 0x03) << 16 |
705 (arg->order_max & 0x1F) << 8 |
706 (arg->order_min & 0x1F);
707 rkisp_iowrite32(params_vdev, value, ISP_DEBAYER_C_FILTER);
708 }
709
710 static void
isp_debayer_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)711 isp_debayer_enable(struct rkisp_isp_params_vdev *params_vdev,
712 bool en)
713 {
714 if (en)
715 isp_param_set_bits(params_vdev,
716 ISP_DEBAYER_CONTROL,
717 ISP_DEBAYER_EN);
718 else
719 isp_param_clear_bits(params_vdev,
720 ISP_DEBAYER_CONTROL,
721 ISP_DEBAYER_EN);
722 }
723
724 static void
isp_awbgain_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_awb_gain_cfg * arg)725 isp_awbgain_config(struct rkisp_isp_params_vdev *params_vdev,
726 const struct isp21_awb_gain_cfg *arg)
727 {
728 struct rkisp_device *dev = params_vdev->dev;
729
730 if (!arg->gain0_red || !arg->gain0_blue ||
731 !arg->gain1_red || !arg->gain1_blue ||
732 !arg->gain2_red || !arg->gain2_blue ||
733 !arg->gain0_green_r || !arg->gain0_green_b ||
734 !arg->gain1_green_r || !arg->gain1_green_b ||
735 !arg->gain2_green_r || !arg->gain2_green_b) {
736 dev_err(dev->dev, "awb gain is zero!\n");
737 return;
738 }
739
740 rkisp_iowrite32(params_vdev,
741 ISP2X_PACK_2SHORT(arg->gain0_green_b, arg->gain0_green_r),
742 ISP21_AWB_GAIN0_G);
743
744 rkisp_iowrite32(params_vdev,
745 ISP2X_PACK_2SHORT(arg->gain0_blue, arg->gain0_red),
746 ISP21_AWB_GAIN0_RB);
747
748 rkisp_iowrite32(params_vdev,
749 ISP2X_PACK_2SHORT(arg->gain1_green_b, arg->gain1_green_r),
750 ISP21_AWB_GAIN1_G);
751
752 rkisp_iowrite32(params_vdev,
753 ISP2X_PACK_2SHORT(arg->gain1_blue, arg->gain1_red),
754 ISP21_AWB_GAIN1_RB);
755
756 rkisp_iowrite32(params_vdev,
757 ISP2X_PACK_2SHORT(arg->gain2_green_b, arg->gain2_green_r),
758 ISP21_AWB_GAIN2_G);
759
760 rkisp_iowrite32(params_vdev,
761 ISP2X_PACK_2SHORT(arg->gain2_blue, arg->gain2_red),
762 ISP21_AWB_GAIN2_RB);
763 }
764
765 static void
isp_awbgain_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)766 isp_awbgain_enable(struct rkisp_isp_params_vdev *params_vdev,
767 bool en)
768 {
769 if (en)
770 isp_param_set_bits(params_vdev, CIF_ISP_CTRL,
771 CIF_ISP_CTRL_ISP_AWB_ENA);
772 else
773 isp_param_clear_bits(params_vdev, CIF_ISP_CTRL,
774 CIF_ISP_CTRL_ISP_AWB_ENA);
775 }
776
777 static void
isp_ccm_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_ccm_cfg * arg)778 isp_ccm_config(struct rkisp_isp_params_vdev *params_vdev,
779 const struct isp21_ccm_cfg *arg)
780 {
781 u32 value;
782 u32 i;
783
784 value = rkisp_ioread32(params_vdev, ISP_CCM_CTRL);
785 value &= ISP_CCM_EN;
786
787 value |= (arg->highy_adjust_dis & 0x01) << 1;
788 rkisp_iowrite32(params_vdev, value, ISP_CCM_CTRL);
789
790 value = ISP2X_PACK_2SHORT(arg->coeff0_r, arg->coeff1_r);
791 rkisp_iowrite32(params_vdev, value, ISP_CCM_COEFF0_R);
792
793 value = ISP2X_PACK_2SHORT(arg->coeff2_r, arg->offset_r);
794 rkisp_iowrite32(params_vdev, value, ISP_CCM_COEFF1_R);
795
796 value = ISP2X_PACK_2SHORT(arg->coeff0_g, arg->coeff1_g);
797 rkisp_iowrite32(params_vdev, value, ISP_CCM_COEFF0_G);
798
799 value = ISP2X_PACK_2SHORT(arg->coeff2_g, arg->offset_g);
800 rkisp_iowrite32(params_vdev, value, ISP_CCM_COEFF1_G);
801
802 value = ISP2X_PACK_2SHORT(arg->coeff0_b, arg->coeff1_b);
803 rkisp_iowrite32(params_vdev, value, ISP_CCM_COEFF0_B);
804
805 value = ISP2X_PACK_2SHORT(arg->coeff2_b, arg->offset_b);
806 rkisp_iowrite32(params_vdev, value, ISP_CCM_COEFF1_B);
807
808 value = ISP2X_PACK_2SHORT(arg->coeff0_y, arg->coeff1_y);
809 rkisp_iowrite32(params_vdev, value, ISP_CCM_COEFF0_Y);
810
811 value = ISP2X_PACK_2SHORT(arg->coeff2_y, 0);
812 rkisp_iowrite32(params_vdev, value, ISP_CCM_COEFF1_Y);
813
814 for (i = 0; i < ISP2X_CCM_CURVE_NUM / 2; i++) {
815 value = ISP2X_PACK_2SHORT(arg->alp_y[2 * i], arg->alp_y[2 * i + 1]);
816 rkisp_iowrite32(params_vdev, value, ISP_CCM_ALP_Y0 + 4 * i);
817 }
818 value = ISP2X_PACK_2SHORT(arg->alp_y[2 * i], 0);
819 rkisp_iowrite32(params_vdev, value, ISP_CCM_ALP_Y0 + 4 * i);
820
821 value = arg->bound_bit & 0x0F;
822 rkisp_iowrite32(params_vdev, value, ISP_CCM_BOUND_BIT);
823 }
824
825 static void
isp_ccm_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)826 isp_ccm_enable(struct rkisp_isp_params_vdev *params_vdev,
827 bool en)
828 {
829 if (en)
830 isp_param_set_bits(params_vdev, ISP_CCM_CTRL, ISP_CCM_EN);
831 else
832 isp_param_clear_bits(params_vdev, ISP_CCM_CTRL, ISP_CCM_EN);
833 }
834
835 static void
isp_goc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_gammaout_cfg * arg)836 isp_goc_config(struct rkisp_isp_params_vdev *params_vdev,
837 const struct isp2x_gammaout_cfg *arg)
838 {
839 int i;
840 u32 value;
841
842 if (arg->equ_segm)
843 isp_param_set_bits(params_vdev, ISP_GAMMA_OUT_CTRL, 0x02);
844 else
845 isp_param_clear_bits(params_vdev, ISP_GAMMA_OUT_CTRL, 0x02);
846
847 rkisp_iowrite32(params_vdev, arg->offset, ISP_GAMMA_OUT_OFFSET);
848 for (i = 0; i < ISP2X_GAMMA_OUT_MAX_SAMPLES / 2; i++) {
849 value = ISP2X_PACK_2SHORT(
850 arg->gamma_y[2 * i],
851 arg->gamma_y[2 * i + 1]);
852 rkisp_iowrite32(params_vdev, value, ISP_GAMMA_OUT_Y0 + i * 4);
853 }
854
855 rkisp_iowrite32(params_vdev, arg->gamma_y[2 * i], ISP_GAMMA_OUT_Y0 + i * 4);
856 }
857
858 static void
isp_goc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)859 isp_goc_enable(struct rkisp_isp_params_vdev *params_vdev,
860 bool en)
861 {
862 if (en)
863 isp_param_set_bits(params_vdev, ISP_GAMMA_OUT_CTRL, 0x01);
864 else
865 isp_param_clear_bits(params_vdev, ISP_GAMMA_OUT_CTRL, 0x01);
866 }
867
868 static void
isp_cproc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_cproc_cfg * arg)869 isp_cproc_config(struct rkisp_isp_params_vdev *params_vdev,
870 const struct isp2x_cproc_cfg *arg)
871 {
872 u32 quantization = params_vdev->quantization;
873
874 rkisp_iowrite32(params_vdev, arg->contrast, CPROC_CONTRAST);
875 rkisp_iowrite32(params_vdev, arg->hue, CPROC_HUE);
876 rkisp_iowrite32(params_vdev, arg->sat, CPROC_SATURATION);
877 rkisp_iowrite32(params_vdev, arg->brightness, CPROC_BRIGHTNESS);
878
879 if (quantization != V4L2_QUANTIZATION_FULL_RANGE) {
880 isp_param_clear_bits(params_vdev, CPROC_CTRL,
881 CIF_C_PROC_YOUT_FULL |
882 CIF_C_PROC_YIN_FULL |
883 CIF_C_PROC_COUT_FULL);
884 } else {
885 isp_param_set_bits(params_vdev, CPROC_CTRL,
886 CIF_C_PROC_YOUT_FULL |
887 CIF_C_PROC_YIN_FULL |
888 CIF_C_PROC_COUT_FULL);
889 }
890 }
891
892 static void
isp_cproc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)893 isp_cproc_enable(struct rkisp_isp_params_vdev *params_vdev,
894 bool en)
895 {
896 if (en)
897 isp_param_set_bits(params_vdev,
898 CPROC_CTRL,
899 CIF_C_PROC_CTR_ENABLE);
900 else
901 isp_param_clear_bits(params_vdev,
902 CPROC_CTRL,
903 CIF_C_PROC_CTR_ENABLE);
904 }
905
906 static void
isp_ie_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_ie_cfg * arg)907 isp_ie_config(struct rkisp_isp_params_vdev *params_vdev,
908 const struct isp2x_ie_cfg *arg)
909 {
910 u32 eff_ctrl;
911
912 eff_ctrl = rkisp_ioread32(params_vdev, CIF_IMG_EFF_CTRL);
913 eff_ctrl &= ~CIF_IMG_EFF_CTRL_MODE_MASK;
914
915 if (params_vdev->quantization == V4L2_QUANTIZATION_FULL_RANGE)
916 eff_ctrl |= CIF_IMG_EFF_CTRL_YCBCR_FULL;
917
918 switch (arg->effect) {
919 case V4L2_COLORFX_SEPIA:
920 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SEPIA;
921 break;
922 case V4L2_COLORFX_SET_CBCR:
923 rkisp_iowrite32(params_vdev, arg->eff_tint, CIF_IMG_EFF_TINT);
924 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SEPIA;
925 break;
926 /*
927 * Color selection is similar to water color(AQUA):
928 * grayscale + selected color w threshold
929 */
930 case V4L2_COLORFX_AQUA:
931 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_COLOR_SEL;
932 rkisp_iowrite32(params_vdev, arg->color_sel,
933 CIF_IMG_EFF_COLOR_SEL);
934 break;
935 case V4L2_COLORFX_EMBOSS:
936 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_EMBOSS;
937 rkisp_iowrite32(params_vdev, arg->eff_mat_1,
938 CIF_IMG_EFF_MAT_1);
939 rkisp_iowrite32(params_vdev, arg->eff_mat_2,
940 CIF_IMG_EFF_MAT_2);
941 rkisp_iowrite32(params_vdev, arg->eff_mat_3,
942 CIF_IMG_EFF_MAT_3);
943 break;
944 case V4L2_COLORFX_SKETCH:
945 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SKETCH;
946 rkisp_iowrite32(params_vdev, arg->eff_mat_3,
947 CIF_IMG_EFF_MAT_3);
948 rkisp_iowrite32(params_vdev, arg->eff_mat_4,
949 CIF_IMG_EFF_MAT_4);
950 rkisp_iowrite32(params_vdev, arg->eff_mat_5,
951 CIF_IMG_EFF_MAT_5);
952 break;
953 case V4L2_COLORFX_BW:
954 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_BLACKWHITE;
955 break;
956 case V4L2_COLORFX_NEGATIVE:
957 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_NEGATIVE;
958 break;
959 default:
960 break;
961 }
962
963 rkisp_iowrite32(params_vdev, eff_ctrl, CIF_IMG_EFF_CTRL);
964 }
965
966 static void
isp_ie_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)967 isp_ie_enable(struct rkisp_isp_params_vdev *params_vdev,
968 bool en)
969 {
970 if (en) {
971 isp_param_set_bits(params_vdev, CIF_IMG_EFF_CTRL,
972 CIF_IMG_EFF_CTRL_ENABLE);
973 isp_param_set_bits(params_vdev, CIF_IMG_EFF_CTRL,
974 CIF_IMG_EFF_CTRL_CFG_UPD);
975 } else {
976 isp_param_clear_bits(params_vdev, CIF_IMG_EFF_CTRL,
977 CIF_IMG_EFF_CTRL_ENABLE);
978 }
979 }
980
981 static void
isp_rawaf_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaf_meas_cfg * arg)982 isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev,
983 const struct isp2x_rawaf_meas_cfg *arg)
984 {
985 u32 i, var;
986 u16 h_size, v_size;
987 u16 h_offs, v_offs;
988 size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->win),
989 arg->num_afm_win);
990 u32 value = rkisp_ioread32(params_vdev, ISP_RAWAF_CTRL);
991
992 for (i = 0; i < num_of_win; i++) {
993 h_size = arg->win[i].h_size;
994 v_size = arg->win[i].v_size;
995 h_offs = arg->win[i].h_offs < 2 ? 2 : arg->win[i].h_offs;
996 v_offs = arg->win[i].v_offs < 1 ? 1 : arg->win[i].v_offs;
997
998 if (i == 0) {
999 h_size = h_size / 15 * 15;
1000 v_size = v_size / 15 * 15;
1001 }
1002
1003 // (horizontal left row), value must be greater or equal 2
1004 // (vertical top line), value must be greater or equal 1
1005 rkisp_iowrite32(params_vdev,
1006 ISP2X_PACK_2SHORT(v_offs, h_offs),
1007 ISP_RAWAF_LT_A + i * 8);
1008
1009 // value must be smaller than [width of picture -2]
1010 // value must be lower than (number of lines -2)
1011 rkisp_iowrite32(params_vdev,
1012 ISP2X_PACK_2SHORT(v_size, h_size),
1013 ISP_RAWAF_RB_A + i * 8);
1014 }
1015
1016 var = 0;
1017 for (i = 0; i < ISP2X_RAWAF_LINE_NUM; i++) {
1018 if (arg->line_en[i])
1019 var |= ISP2X_RAWAF_INT_LINE0_EN << i;
1020 var |= ISP2X_RAWAF_INT_LINE0_NUM(arg->line_num[i]) << 4 * i;
1021 }
1022 rkisp_iowrite32(params_vdev, var, ISP_RAWAF_INT_LINE);
1023
1024 rkisp_iowrite32(params_vdev,
1025 ISP2X_PACK_4BYTE(arg->gaus_coe_h0, arg->gaus_coe_h1, arg->gaus_coe_h2, 0),
1026 ISP_RAWAF_GAUS_COE);
1027
1028 var = rkisp_ioread32(params_vdev, ISP_RAWAF_THRES);
1029 var &= ~(ISP2X_RAWAF_THRES(0xFFFF));
1030 var |= arg->afm_thres;
1031 rkisp_iowrite32(params_vdev, var, ISP_RAWAF_THRES);
1032
1033 rkisp_iowrite32(params_vdev,
1034 ISP2X_RAWAF_SET_SHIFT_A(arg->lum_var_shift[0], arg->afm_var_shift[0]) |
1035 ISP2X_RAWAF_SET_SHIFT_B(arg->lum_var_shift[1], arg->afm_var_shift[1]),
1036 ISP_RAWAF_VAR_SHIFT);
1037
1038 for (i = 0; i < ISP2X_RAWAF_GAMMA_NUM / 2; i++)
1039 rkisp_iowrite32(params_vdev,
1040 ISP2X_PACK_2SHORT(arg->gamma_y[2 * i], arg->gamma_y[2 * i + 1]),
1041 ISP_RAWAF_GAMMA_Y0 + i * 4);
1042
1043 rkisp_iowrite32(params_vdev,
1044 ISP2X_PACK_2SHORT(arg->gamma_y[16], 0),
1045 ISP_RAWAF_GAMMA_Y8);
1046
1047 value &= ISP2X_RAWAF_ENA;
1048 if (arg->gamma_en)
1049 value |= ISP2X_RAWAF_GAMMA_ENA;
1050 else
1051 value &= ~ISP2X_RAWAF_GAMMA_ENA;
1052 if (arg->gaus_en)
1053 value |= ISP2X_RAWAF_GAUS_ENA;
1054 else
1055 value &= ~ISP2X_RAWAF_GAUS_ENA;
1056 value &= ~ISP2X_REG_WR_MASK;
1057 rkisp_iowrite32(params_vdev, value, ISP_RAWAF_CTRL);
1058
1059 value = rkisp_ioread32(params_vdev, CTRL_VI_ISP_PATH);
1060 value &= ~(ISP2X_ISPPATH_RAWAF_SEL_SET(3));
1061 value |= ISP2X_ISPPATH_RAWAF_SEL_SET(arg->rawaf_sel);
1062 rkisp_iowrite32(params_vdev, value, CTRL_VI_ISP_PATH);
1063 }
1064
1065 static void
isp_rawaf_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)1066 isp_rawaf_enable(struct rkisp_isp_params_vdev *params_vdev,
1067 bool en)
1068 {
1069 u32 afm_ctrl = rkisp_ioread32(params_vdev, ISP_RAWAF_CTRL);
1070
1071 afm_ctrl &= ~ISP2X_REG_WR_MASK;
1072 if (en)
1073 afm_ctrl |= ISP2X_RAWAF_ENA;
1074 else
1075 afm_ctrl &= ~ISP2X_RAWAF_ENA;
1076
1077 rkisp_iowrite32(params_vdev, afm_ctrl, ISP_RAWAF_CTRL);
1078 }
1079
1080 static void
isp_rawaelite_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaelite_meas_cfg * arg)1081 isp_rawaelite_config(struct rkisp_isp_params_vdev *params_vdev,
1082 const struct isp2x_rawaelite_meas_cfg *arg)
1083 {
1084 struct rkisp_device *ispdev = params_vdev->dev;
1085 struct v4l2_rect *out_crop = &ispdev->isp_sdev.out_crop;
1086 u32 block_hsize, block_vsize, value;
1087 u32 wnd_num_idx = 0;
1088 const u32 ae_wnd_num[] = {
1089 1, 5
1090 };
1091
1092 value = rkisp_ioread32(params_vdev, ISP_RAWAE_LITE_CTRL);
1093 value &= ~(ISP2X_RAWAE_LITE_WNDNUM_SET(0x1));
1094 if (arg->wnd_num) {
1095 value |= ISP2X_RAWAE_LITE_WNDNUM_SET(0x1);
1096 wnd_num_idx = 1;
1097 }
1098 value &= ~ISP2X_REG_WR_MASK;
1099 rkisp_iowrite32(params_vdev, value, ISP_RAWAE_LITE_CTRL);
1100
1101 rkisp_iowrite32(params_vdev,
1102 ISP2X_RAWAE_LITE_V_OFFSET_SET(arg->win.v_offs) |
1103 ISP2X_RAWAE_LITE_H_OFFSET_SET(arg->win.h_offs),
1104 ISP_RAWAE_LITE_OFFSET);
1105
1106 block_hsize = arg->win.h_size / ae_wnd_num[wnd_num_idx];
1107 value = block_hsize * ae_wnd_num[wnd_num_idx] + arg->win.h_offs;
1108 if (value + 1 > out_crop->width)
1109 block_hsize -= 1;
1110 block_vsize = arg->win.v_size / ae_wnd_num[wnd_num_idx];
1111 value = block_vsize * ae_wnd_num[wnd_num_idx] + arg->win.v_offs;
1112 if (value + 2 > out_crop->height)
1113 block_vsize -= 1;
1114 if (block_vsize % 2)
1115 block_vsize -= 1;
1116 rkisp_iowrite32(params_vdev,
1117 ISP2X_RAWAE_LITE_V_SIZE_SET(block_vsize) |
1118 ISP2X_RAWAE_LITE_H_SIZE_SET(block_hsize),
1119 ISP_RAWAE_LITE_BLK_SIZ);
1120
1121 value = rkisp_ioread32(params_vdev, CTRL_VI_ISP_PATH);
1122 value &= ~(ISP2X_ISPPATH_RAWAE_SWAP_SET(3));
1123 value |= ISP2X_ISPPATH_RAWAE_SWAP_SET(arg->rawae_sel);
1124 rkisp_iowrite32(params_vdev, value, CTRL_VI_ISP_PATH);
1125 }
1126
1127 static void
isp_rawaelite_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)1128 isp_rawaelite_enable(struct rkisp_isp_params_vdev *params_vdev,
1129 bool en)
1130 {
1131 u32 exp_ctrl;
1132
1133 exp_ctrl = rkisp_ioread32(params_vdev, ISP_RAWAE_LITE_CTRL);
1134 exp_ctrl &= ~ISP2X_REG_WR_MASK;
1135 if (en)
1136 exp_ctrl |= ISP2X_RAWAE_LITE_ENA;
1137 else
1138 exp_ctrl &= ~ISP2X_RAWAE_LITE_ENA;
1139
1140 rkisp_iowrite32(params_vdev, exp_ctrl, ISP_RAWAE_LITE_CTRL);
1141 }
1142
1143 static void
isp_rawaebig_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaebig_meas_cfg * arg,u32 blk_no)1144 isp_rawaebig_config(struct rkisp_isp_params_vdev *params_vdev,
1145 const struct isp2x_rawaebig_meas_cfg *arg, u32 blk_no)
1146 {
1147 struct rkisp_device *ispdev = params_vdev->dev;
1148 struct v4l2_rect *out_crop = &ispdev->isp_sdev.out_crop;
1149 u32 block_hsize, block_vsize;
1150 u32 addr, i, value, h_size, v_size;
1151 u32 wnd_num_idx = 0;
1152 const u32 ae_wnd_num[] = {
1153 1, 5, 15, 15
1154 };
1155
1156 switch (blk_no) {
1157 case 0:
1158 addr = RAWAE_BIG1_BASE;
1159 break;
1160 case 1:
1161 addr = RAWAE_BIG2_BASE;
1162 break;
1163 case 2:
1164 addr = RAWAE_BIG3_BASE;
1165 break;
1166 default:
1167 addr = RAWAE_BIG1_BASE;
1168 break;
1169 }
1170
1171 /* avoid to override the old enable value */
1172 value = rkisp_ioread32(params_vdev, addr + RAWAE_BIG_CTRL);
1173 value &= ~(ISP2X_RAWAEBIG_WNDNUM_SET(0x3) |
1174 ISP2X_RAWAEBIG_SUBWIN1_EN |
1175 ISP2X_RAWAEBIG_SUBWIN2_EN |
1176 ISP2X_RAWAEBIG_SUBWIN3_EN |
1177 ISP2X_RAWAEBIG_SUBWIN4_EN |
1178 ISP2X_REG_WR_MASK);
1179
1180 wnd_num_idx = arg->wnd_num;
1181 value |= ISP2X_RAWAEBIG_WNDNUM_SET(wnd_num_idx);
1182
1183 if (arg->subwin_en[0])
1184 value |= ISP2X_RAWAEBIG_SUBWIN1_EN;
1185 if (arg->subwin_en[1])
1186 value |= ISP2X_RAWAEBIG_SUBWIN2_EN;
1187 if (arg->subwin_en[2])
1188 value |= ISP2X_RAWAEBIG_SUBWIN3_EN;
1189 if (arg->subwin_en[3])
1190 value |= ISP2X_RAWAEBIG_SUBWIN4_EN;
1191
1192 rkisp_iowrite32(params_vdev, value, addr + RAWAE_BIG_CTRL);
1193
1194 rkisp_iowrite32(params_vdev,
1195 ISP2X_RAWAEBIG_V_OFFSET_SET(arg->win.v_offs) |
1196 ISP2X_RAWAEBIG_H_OFFSET_SET(arg->win.h_offs),
1197 addr + RAWAE_BIG_OFFSET);
1198
1199 block_hsize = arg->win.h_size / ae_wnd_num[wnd_num_idx];
1200 value = block_hsize * ae_wnd_num[wnd_num_idx] + arg->win.h_offs;
1201 if (value + 1 > out_crop->width)
1202 block_hsize -= 1;
1203 block_vsize = arg->win.v_size / ae_wnd_num[wnd_num_idx];
1204 value = block_vsize * ae_wnd_num[wnd_num_idx] + arg->win.v_offs;
1205 if (value + 2 > out_crop->height)
1206 block_vsize -= 1;
1207 if (block_vsize % 2)
1208 block_vsize -= 1;
1209 rkisp_iowrite32(params_vdev,
1210 ISP2X_RAWAEBIG_V_SIZE_SET(block_vsize) |
1211 ISP2X_RAWAEBIG_H_SIZE_SET(block_hsize),
1212 addr + RAWAE_BIG_BLK_SIZE);
1213
1214 for (i = 0; i < ISP2X_RAWAEBIG_SUBWIN_NUM; i++) {
1215 rkisp_iowrite32(params_vdev,
1216 ISP2X_RAWAEBIG_SUBWIN_V_OFFSET_SET(arg->subwin[i].v_offs) |
1217 ISP2X_RAWAEBIG_SUBWIN_H_OFFSET_SET(arg->subwin[i].h_offs),
1218 addr + RAWAE_BIG_WND1_OFFSET + 8 * i);
1219
1220 v_size = arg->subwin[i].v_size + arg->subwin[i].v_offs;
1221 h_size = arg->subwin[i].h_size + arg->subwin[i].h_offs;
1222 rkisp_iowrite32(params_vdev,
1223 ISP2X_RAWAEBIG_SUBWIN_V_SIZE_SET(v_size) |
1224 ISP2X_RAWAEBIG_SUBWIN_H_SIZE_SET(h_size),
1225 addr + RAWAE_BIG_WND1_SIZE + 8 * i);
1226 }
1227
1228 if (blk_no == 0) {
1229 value = rkisp_ioread32(params_vdev, CTRL_VI_ISP_PATH);
1230 value &= ~(ISP2X_ISPPATH_RAWAE_SEL_SET(3));
1231 value |= ISP2X_ISPPATH_RAWAE_SEL_SET(arg->rawae_sel);
1232 rkisp_iowrite32(params_vdev, value, CTRL_VI_ISP_PATH);
1233 } else {
1234 value = rkisp_ioread32(params_vdev, CTRL_VI_ISP_PATH);
1235 value &= ~(ISP2X_ISPPATH_RAWAE_SWAP_SET(3));
1236 value |= ISP2X_ISPPATH_RAWAE_SWAP_SET(arg->rawae_sel);
1237 rkisp_iowrite32(params_vdev, value, CTRL_VI_ISP_PATH);
1238 }
1239 }
1240
1241 static void
isp_rawaebig_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 blk_no)1242 isp_rawaebig_enable(struct rkisp_isp_params_vdev *params_vdev,
1243 bool en, u32 blk_no)
1244 {
1245 u32 exp_ctrl;
1246 u32 addr;
1247
1248 switch (blk_no) {
1249 case 0:
1250 addr = RAWAE_BIG1_BASE;
1251 break;
1252 case 1:
1253 addr = RAWAE_BIG2_BASE;
1254 break;
1255 case 2:
1256 addr = RAWAE_BIG3_BASE;
1257 break;
1258 default:
1259 addr = RAWAE_BIG1_BASE;
1260 break;
1261 }
1262
1263 exp_ctrl = rkisp_ioread32(params_vdev, addr + RAWAE_BIG_CTRL);
1264 exp_ctrl &= ~ISP2X_REG_WR_MASK;
1265 if (en)
1266 exp_ctrl |= ISP2X_RAWAEBIG_ENA;
1267 else
1268 exp_ctrl &= ~ISP2X_RAWAEBIG_ENA;
1269
1270 rkisp_iowrite32(params_vdev, exp_ctrl, addr + RAWAE_BIG_CTRL);
1271 }
1272
1273 static void
isp_rawae1_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaebig_meas_cfg * arg)1274 isp_rawae1_config(struct rkisp_isp_params_vdev *params_vdev,
1275 const struct isp2x_rawaebig_meas_cfg *arg)
1276 {
1277 isp_rawaebig_config(params_vdev, arg, 1);
1278 }
1279
1280 static void
isp_rawae1_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)1281 isp_rawae1_enable(struct rkisp_isp_params_vdev *params_vdev,
1282 bool en)
1283 {
1284 isp_rawaebig_enable(params_vdev, en, 1);
1285 }
1286
1287 static void
isp_rawae2_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaebig_meas_cfg * arg)1288 isp_rawae2_config(struct rkisp_isp_params_vdev *params_vdev,
1289 const struct isp2x_rawaebig_meas_cfg *arg)
1290 {
1291 isp_rawaebig_config(params_vdev, arg, 2);
1292 }
1293
1294 static void
isp_rawae2_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)1295 isp_rawae2_enable(struct rkisp_isp_params_vdev *params_vdev,
1296 bool en)
1297 {
1298 isp_rawaebig_enable(params_vdev, en, 2);
1299 }
1300
1301 static void
isp_rawae3_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaebig_meas_cfg * arg)1302 isp_rawae3_config(struct rkisp_isp_params_vdev *params_vdev,
1303 const struct isp2x_rawaebig_meas_cfg *arg)
1304 {
1305 isp_rawaebig_config(params_vdev, arg, 0);
1306 }
1307
1308 static void
isp_rawae3_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)1309 isp_rawae3_enable(struct rkisp_isp_params_vdev *params_vdev,
1310 bool en)
1311 {
1312 isp_rawaebig_enable(params_vdev, en, 0);
1313 }
1314
1315 static void
isp_rawawb_cfg_sram(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_rawawb_meas_cfg * arg,bool is_check)1316 isp_rawawb_cfg_sram(struct rkisp_isp_params_vdev *params_vdev,
1317 const struct isp21_rawawb_meas_cfg *arg, bool is_check)
1318 {
1319 u32 i, val = ISP2X_RAWAWB_ENA;
1320
1321 if (is_check &&
1322 !(rkisp_ioread32(params_vdev, ISP21_RAWAWB_CTRL) & val))
1323 return;
1324
1325 for (i = 0; i < ISP21_RAWAWB_WEIGHT_NUM / 5; i++) {
1326 val = (arg->sw_rawawb_wp_blk_wei_w[5 * i] & 0x3f) << 0 |
1327 (arg->sw_rawawb_wp_blk_wei_w[5 * i + 1] & 0x3f) << 6 |
1328 (arg->sw_rawawb_wp_blk_wei_w[5 * i + 2] & 0x3f) << 12 |
1329 (arg->sw_rawawb_wp_blk_wei_w[5 * i + 3] & 0x3f) << 18 |
1330 (arg->sw_rawawb_wp_blk_wei_w[5 * i + 4] & 0x3f) << 24,
1331 rkisp_iowrite32(params_vdev, val, ISP21_RAWAWB_WRAM_DATA_BASE);
1332 }
1333 }
1334
1335 static void
isp_rawawb_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_rawawb_meas_cfg * arg)1336 isp_rawawb_config(struct rkisp_isp_params_vdev *params_vdev,
1337 const struct isp21_rawawb_meas_cfg *arg)
1338 {
1339 struct isp21_isp_params_cfg *params_rec = params_vdev->isp21_params;
1340 struct isp21_rawawb_meas_cfg *arg_rec = ¶ms_rec->meas.rawawb;
1341 u32 value;
1342
1343 rkisp_iowrite32(params_vdev,
1344 (arg->sw_rawawb_blk_measure_enable & 0x1) |
1345 (arg->sw_rawawb_blk_measure_mode & 0x1) << 1 |
1346 (arg->sw_rawawb_blk_measure_xytype & 0x1) << 2 |
1347 (arg->sw_rawawb_blk_rtdw_measure_en & 0x1) << 3 |
1348 (arg->sw_rawawb_blk_measure_illu_idx & 0x7) << 4 |
1349 (arg->sw_rawawb_blk_with_luma_wei_en & 0x1) << 8,
1350 ISP21_RAWAWB_BLK_CTRL);
1351
1352 rkisp_iowrite32(params_vdev,
1353 ISP2X_PACK_2SHORT(arg->sw_rawawb_h_offs, arg->sw_rawawb_v_offs),
1354 ISP21_RAWAWB_WIN_OFFS);
1355
1356 rkisp_iowrite32(params_vdev,
1357 ISP2X_PACK_2SHORT(arg->sw_rawawb_h_size, arg->sw_rawawb_v_size),
1358 ISP21_RAWAWB_WIN_SIZE);
1359
1360 rkisp_iowrite32(params_vdev,
1361 ISP2X_PACK_2SHORT(arg->sw_rawawb_r_max, arg->sw_rawawb_g_max),
1362 ISP21_RAWAWB_LIMIT_RG_MAX);
1363
1364 rkisp_iowrite32(params_vdev,
1365 ISP2X_PACK_2SHORT(arg->sw_rawawb_b_max, arg->sw_rawawb_y_max),
1366 ISP21_RAWAWB_LIMIT_BY_MAX);
1367
1368 rkisp_iowrite32(params_vdev,
1369 ISP2X_PACK_2SHORT(arg->sw_rawawb_r_min, arg->sw_rawawb_g_min),
1370 ISP21_RAWAWB_LIMIT_RG_MIN);
1371
1372 rkisp_iowrite32(params_vdev,
1373 ISP2X_PACK_2SHORT(arg->sw_rawawb_b_min, arg->sw_rawawb_y_min),
1374 ISP21_RAWAWB_LIMIT_BY_MIN);
1375
1376 rkisp_iowrite32(params_vdev,
1377 (arg->sw_rawawb_wp_luma_wei_en0 & 0x1) |
1378 (arg->sw_rawawb_wp_luma_wei_en1 & 0x1) << 1 |
1379 (arg->sw_rawawb_wp_blk_wei_en0 & 0x1) << 2 |
1380 (arg->sw_rawawb_wp_blk_wei_en1 & 0x1) << 3 |
1381 (arg->sw_rawawb_wp_hist_xytype & 0x1) << 4,
1382 ISP21_RAWAWB_WEIGHT_CURVE_CTRL);
1383
1384 rkisp_iowrite32(params_vdev,
1385 ISP2X_PACK_4BYTE(arg->sw_rawawb_wp_luma_weicurve_y0,
1386 arg->sw_rawawb_wp_luma_weicurve_y1,
1387 arg->sw_rawawb_wp_luma_weicurve_y2,
1388 arg->sw_rawawb_wp_luma_weicurve_y3),
1389 ISP21_RAWAWB_YWEIGHT_CURVE_XCOOR03);
1390
1391 rkisp_iowrite32(params_vdev,
1392 ISP2X_PACK_4BYTE(arg->sw_rawawb_wp_luma_weicurve_y4,
1393 arg->sw_rawawb_wp_luma_weicurve_y5,
1394 arg->sw_rawawb_wp_luma_weicurve_y6,
1395 arg->sw_rawawb_wp_luma_weicurve_y7),
1396 ISP21_RAWAWB_YWEIGHT_CURVE_XCOOR47);
1397
1398 rkisp_iowrite32(params_vdev,
1399 arg->sw_rawawb_wp_luma_weicurve_y8,
1400 ISP21_RAWAWB_YWEIGHT_CURVE_XCOOR8);
1401
1402 rkisp_iowrite32(params_vdev,
1403 ISP2X_PACK_4BYTE(arg->sw_rawawb_wp_luma_weicurve_w0,
1404 arg->sw_rawawb_wp_luma_weicurve_w1,
1405 arg->sw_rawawb_wp_luma_weicurve_w2,
1406 arg->sw_rawawb_wp_luma_weicurve_w3),
1407 ISP21_RAWAWB_YWEIGHT_CURVE_YCOOR03);
1408
1409 rkisp_iowrite32(params_vdev,
1410 ISP2X_PACK_4BYTE(arg->sw_rawawb_wp_luma_weicurve_w4,
1411 arg->sw_rawawb_wp_luma_weicurve_w5,
1412 arg->sw_rawawb_wp_luma_weicurve_w6,
1413 arg->sw_rawawb_wp_luma_weicurve_w7),
1414 ISP21_RAWAWB_YWEIGHT_CURVE_YCOOR47);
1415
1416 rkisp_iowrite32(params_vdev,
1417 ISP2X_PACK_2SHORT(arg->sw_rawawb_wp_luma_weicurve_w8,
1418 arg->sw_rawawb_pre_wbgain_inv_r),
1419 ISP21_RAWAWB_YWEIGHT_CURVE_YCOOR8);
1420
1421 rkisp_iowrite32(params_vdev,
1422 ISP2X_PACK_2SHORT(arg->sw_rawawb_pre_wbgain_inv_g,
1423 arg->sw_rawawb_pre_wbgain_inv_b),
1424 ISP21_RAWAWB_PRE_WBGAIN_INV);
1425
1426 rkisp_iowrite32(params_vdev,
1427 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex0_u_0,
1428 arg->sw_rawawb_vertex0_v_0),
1429 ISP21_RAWAWB_UV_DETC_VERTEX0_0);
1430
1431 rkisp_iowrite32(params_vdev,
1432 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex1_u_0,
1433 arg->sw_rawawb_vertex1_v_0),
1434 ISP21_RAWAWB_UV_DETC_VERTEX1_0);
1435
1436 rkisp_iowrite32(params_vdev,
1437 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex2_u_0,
1438 arg->sw_rawawb_vertex2_v_0),
1439 ISP21_RAWAWB_UV_DETC_VERTEX2_0);
1440
1441 rkisp_iowrite32(params_vdev,
1442 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex3_u_0,
1443 arg->sw_rawawb_vertex3_v_0),
1444 ISP21_RAWAWB_UV_DETC_VERTEX3_0);
1445
1446 rkisp_iowrite32(params_vdev,
1447 arg->sw_rawawb_islope01_0,
1448 ISP21_RAWAWB_UV_DETC_ISLOPE01_0);
1449
1450 rkisp_iowrite32(params_vdev,
1451 arg->sw_rawawb_islope12_0,
1452 ISP21_RAWAWB_UV_DETC_ISLOPE12_0);
1453
1454 rkisp_iowrite32(params_vdev,
1455 arg->sw_rawawb_islope23_0,
1456 ISP21_RAWAWB_UV_DETC_ISLOPE23_0);
1457
1458 rkisp_iowrite32(params_vdev,
1459 arg->sw_rawawb_islope30_0,
1460 ISP21_RAWAWB_UV_DETC_ISLOPE30_0);
1461
1462 rkisp_iowrite32(params_vdev,
1463 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex0_u_1,
1464 arg->sw_rawawb_vertex0_v_1),
1465 ISP21_RAWAWB_UV_DETC_VERTEX0_1);
1466
1467 rkisp_iowrite32(params_vdev,
1468 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex1_u_1,
1469 arg->sw_rawawb_vertex1_v_1),
1470 ISP21_RAWAWB_UV_DETC_VERTEX1_1);
1471
1472 rkisp_iowrite32(params_vdev,
1473 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex2_u_1,
1474 arg->sw_rawawb_vertex2_v_1),
1475 ISP21_RAWAWB_UV_DETC_VERTEX2_1);
1476
1477 rkisp_iowrite32(params_vdev,
1478 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex3_u_1,
1479 arg->sw_rawawb_vertex3_v_1),
1480 ISP21_RAWAWB_UV_DETC_VERTEX3_1);
1481
1482 rkisp_iowrite32(params_vdev,
1483 arg->sw_rawawb_islope01_1,
1484 ISP21_RAWAWB_UV_DETC_ISLOPE01_1);
1485
1486 rkisp_iowrite32(params_vdev,
1487 arg->sw_rawawb_islope12_1,
1488 ISP21_RAWAWB_UV_DETC_ISLOPE12_1);
1489
1490 rkisp_iowrite32(params_vdev,
1491 arg->sw_rawawb_islope23_1,
1492 ISP21_RAWAWB_UV_DETC_ISLOPE23_1);
1493
1494 rkisp_iowrite32(params_vdev,
1495 arg->sw_rawawb_islope30_1,
1496 ISP21_RAWAWB_UV_DETC_ISLOPE30_1);
1497
1498 rkisp_iowrite32(params_vdev,
1499 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex0_u_2,
1500 arg->sw_rawawb_vertex0_v_2),
1501 ISP21_RAWAWB_UV_DETC_VERTEX0_2);
1502
1503 rkisp_iowrite32(params_vdev,
1504 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex1_u_2,
1505 arg->sw_rawawb_vertex1_v_2),
1506 ISP21_RAWAWB_UV_DETC_VERTEX1_2);
1507
1508 rkisp_iowrite32(params_vdev,
1509 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex2_u_2,
1510 arg->sw_rawawb_vertex2_v_2),
1511 ISP21_RAWAWB_UV_DETC_VERTEX2_2);
1512
1513 rkisp_iowrite32(params_vdev,
1514 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex3_u_2,
1515 arg->sw_rawawb_vertex3_v_2),
1516 ISP21_RAWAWB_UV_DETC_VERTEX3_2);
1517
1518 rkisp_iowrite32(params_vdev,
1519 arg->sw_rawawb_islope01_2,
1520 ISP21_RAWAWB_UV_DETC_ISLOPE01_2);
1521
1522 rkisp_iowrite32(params_vdev,
1523 arg->sw_rawawb_islope12_2,
1524 ISP21_RAWAWB_UV_DETC_ISLOPE12_2);
1525
1526 rkisp_iowrite32(params_vdev,
1527 arg->sw_rawawb_islope23_2,
1528 ISP21_RAWAWB_UV_DETC_ISLOPE23_2);
1529
1530 rkisp_iowrite32(params_vdev,
1531 arg->sw_rawawb_islope30_2,
1532 ISP21_RAWAWB_UV_DETC_ISLOPE30_2);
1533
1534 rkisp_iowrite32(params_vdev,
1535 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex0_u_3,
1536 arg->sw_rawawb_vertex0_v_3),
1537 ISP21_RAWAWB_UV_DETC_VERTEX0_3);
1538
1539 rkisp_iowrite32(params_vdev,
1540 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex1_u_3,
1541 arg->sw_rawawb_vertex1_v_3),
1542 ISP21_RAWAWB_UV_DETC_VERTEX1_3);
1543
1544 rkisp_iowrite32(params_vdev,
1545 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex2_u_3,
1546 arg->sw_rawawb_vertex2_v_3),
1547 ISP21_RAWAWB_UV_DETC_VERTEX2_3);
1548
1549 rkisp_iowrite32(params_vdev,
1550 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex3_u_3,
1551 arg->sw_rawawb_vertex3_v_3),
1552 ISP21_RAWAWB_UV_DETC_VERTEX3_3);
1553
1554 rkisp_iowrite32(params_vdev,
1555 arg->sw_rawawb_islope01_3,
1556 ISP21_RAWAWB_UV_DETC_ISLOPE01_3);
1557
1558 rkisp_iowrite32(params_vdev,
1559 arg->sw_rawawb_islope12_3,
1560 ISP21_RAWAWB_UV_DETC_ISLOPE12_3);
1561
1562 rkisp_iowrite32(params_vdev,
1563 arg->sw_rawawb_islope23_3,
1564 ISP21_RAWAWB_UV_DETC_ISLOPE23_3);
1565
1566 rkisp_iowrite32(params_vdev,
1567 arg->sw_rawawb_islope30_3,
1568 ISP21_RAWAWB_UV_DETC_ISLOPE30_3);
1569
1570 rkisp_iowrite32(params_vdev,
1571 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex0_u_4,
1572 arg->sw_rawawb_vertex0_v_4),
1573 ISP21_RAWAWB_UV_DETC_VERTEX0_4);
1574
1575 rkisp_iowrite32(params_vdev,
1576 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex1_u_4,
1577 arg->sw_rawawb_vertex1_v_4),
1578 ISP21_RAWAWB_UV_DETC_VERTEX1_4);
1579
1580 rkisp_iowrite32(params_vdev,
1581 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex2_u_4,
1582 arg->sw_rawawb_vertex2_v_4),
1583 ISP21_RAWAWB_UV_DETC_VERTEX2_4);
1584
1585 rkisp_iowrite32(params_vdev,
1586 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex3_u_4,
1587 arg->sw_rawawb_vertex3_v_4),
1588 ISP21_RAWAWB_UV_DETC_VERTEX3_4);
1589
1590 rkisp_iowrite32(params_vdev,
1591 arg->sw_rawawb_islope01_4,
1592 ISP21_RAWAWB_UV_DETC_ISLOPE01_4);
1593
1594 rkisp_iowrite32(params_vdev,
1595 arg->sw_rawawb_islope12_4,
1596 ISP21_RAWAWB_UV_DETC_ISLOPE12_4);
1597
1598 rkisp_iowrite32(params_vdev,
1599 arg->sw_rawawb_islope23_4,
1600 ISP21_RAWAWB_UV_DETC_ISLOPE23_4);
1601
1602 rkisp_iowrite32(params_vdev,
1603 arg->sw_rawawb_islope30_4,
1604 ISP21_RAWAWB_UV_DETC_ISLOPE30_4);
1605
1606 rkisp_iowrite32(params_vdev,
1607 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex0_u_5,
1608 arg->sw_rawawb_vertex0_v_5),
1609 ISP21_RAWAWB_UV_DETC_VERTEX0_5);
1610
1611 rkisp_iowrite32(params_vdev,
1612 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex1_u_5,
1613 arg->sw_rawawb_vertex1_v_5),
1614 ISP21_RAWAWB_UV_DETC_VERTEX1_5);
1615
1616 rkisp_iowrite32(params_vdev,
1617 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex2_u_5,
1618 arg->sw_rawawb_vertex2_v_5),
1619 ISP21_RAWAWB_UV_DETC_VERTEX2_5);
1620
1621 rkisp_iowrite32(params_vdev,
1622 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex3_u_5,
1623 arg->sw_rawawb_vertex3_v_5),
1624 ISP21_RAWAWB_UV_DETC_VERTEX3_5);
1625
1626 rkisp_iowrite32(params_vdev,
1627 arg->sw_rawawb_islope01_5,
1628 ISP21_RAWAWB_UV_DETC_ISLOPE01_5);
1629
1630 rkisp_iowrite32(params_vdev,
1631 arg->sw_rawawb_islope12_5,
1632 ISP21_RAWAWB_UV_DETC_ISLOPE10_5);
1633
1634 rkisp_iowrite32(params_vdev,
1635 arg->sw_rawawb_islope23_5,
1636 ISP21_RAWAWB_UV_DETC_ISLOPE23_5);
1637
1638 rkisp_iowrite32(params_vdev,
1639 arg->sw_rawawb_islope30_5,
1640 ISP21_RAWAWB_UV_DETC_ISLOPE30_5);
1641
1642 rkisp_iowrite32(params_vdev,
1643 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex0_u_6,
1644 arg->sw_rawawb_vertex0_v_6),
1645 ISP21_RAWAWB_UV_DETC_VERTEX0_6);
1646
1647 rkisp_iowrite32(params_vdev,
1648 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex1_u_6,
1649 arg->sw_rawawb_vertex1_v_6),
1650 ISP21_RAWAWB_UV_DETC_VERTEX1_6);
1651
1652 rkisp_iowrite32(params_vdev,
1653 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex2_u_6,
1654 arg->sw_rawawb_vertex2_v_6),
1655 ISP21_RAWAWB_UV_DETC_VERTEX2_6);
1656
1657 rkisp_iowrite32(params_vdev,
1658 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex3_u_6,
1659 arg->sw_rawawb_vertex3_v_6),
1660 ISP21_RAWAWB_UV_DETC_VERTEX3_6);
1661
1662 rkisp_iowrite32(params_vdev,
1663 arg->sw_rawawb_islope01_6,
1664 ISP21_RAWAWB_UV_DETC_ISLOPE01_6);
1665
1666 rkisp_iowrite32(params_vdev,
1667 arg->sw_rawawb_islope12_6,
1668 ISP21_RAWAWB_UV_DETC_ISLOPE10_6);
1669
1670 rkisp_iowrite32(params_vdev,
1671 arg->sw_rawawb_islope23_6,
1672 ISP21_RAWAWB_UV_DETC_ISLOPE23_6);
1673
1674 rkisp_iowrite32(params_vdev,
1675 arg->sw_rawawb_islope30_6,
1676 ISP21_RAWAWB_UV_DETC_ISLOPE30_6);
1677
1678
1679 rkisp_iowrite32(params_vdev,
1680 ISP2X_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat0_y,
1681 arg->sw_rawawb_rgb2ryuvmat1_y),
1682 ISP21_RAWAWB_YUV_RGB2ROTY_0);
1683
1684 rkisp_iowrite32(params_vdev,
1685 ISP2X_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat2_y,
1686 arg->sw_rawawb_rgb2ryuvofs_y),
1687 ISP21_RAWAWB_YUV_RGB2ROTY_1);
1688
1689
1690 rkisp_iowrite32(params_vdev,
1691 ISP2X_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat0_u,
1692 arg->sw_rawawb_rgb2ryuvmat1_u),
1693 ISP21_RAWAWB_YUV_RGB2ROTU_0);
1694
1695 rkisp_iowrite32(params_vdev,
1696 ISP2X_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat2_u,
1697 arg->sw_rawawb_rgb2ryuvofs_u),
1698 ISP21_RAWAWB_YUV_RGB2ROTU_1);
1699
1700 rkisp_iowrite32(params_vdev,
1701 ISP2X_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat0_v,
1702 arg->sw_rawawb_rgb2ryuvmat1_v),
1703 ISP21_RAWAWB_YUV_RGB2ROTV_0);
1704
1705 rkisp_iowrite32(params_vdev,
1706 ISP2X_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat2_v,
1707 arg->sw_rawawb_rgb2ryuvofs_v),
1708 ISP21_RAWAWB_YUV_RGB2ROTV_1);
1709
1710 rkisp_iowrite32(params_vdev,
1711 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls0_y,
1712 arg->sw_rawawb_vec_x21_ls0_y),
1713 ISP21_RAWAWB_YUV_X_COOR_Y_0);
1714
1715 rkisp_iowrite32(params_vdev,
1716 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls0_u,
1717 arg->sw_rawawb_vec_x21_ls0_u),
1718 ISP21_RAWAWB_YUV_X_COOR_U_0);
1719
1720 rkisp_iowrite32(params_vdev,
1721 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls0_v,
1722 arg->sw_rawawb_vec_x21_ls0_v),
1723 ISP21_RAWAWB_YUV_X_COOR_V_0);
1724
1725 rkisp_iowrite32(params_vdev,
1726 ISP2X_PACK_4BYTE(arg->sw_rawawb_dis_x1x2_ls0,
1727 0,
1728 arg->sw_rawawb_rotu0_ls0,
1729 arg->sw_rawawb_rotu1_ls0),
1730 ISP21_RAWAWB_YUV_X1X2_DIS_0);
1731
1732 rkisp_iowrite32(params_vdev,
1733 ISP2X_PACK_4BYTE(arg->sw_rawawb_rotu2_ls0,
1734 arg->sw_rawawb_rotu3_ls0,
1735 arg->sw_rawawb_rotu4_ls0,
1736 arg->sw_rawawb_rotu5_ls0),
1737 ISP21_RAWAWB_YUV_INTERP_CURVE_UCOOR_0);
1738
1739 rkisp_iowrite32(params_vdev,
1740 ISP2X_PACK_2SHORT(arg->sw_rawawb_th0_ls0,
1741 arg->sw_rawawb_th1_ls0),
1742 ISP21_RAWAWB_YUV_INTERP_CURVE_TH0_0);
1743
1744 rkisp_iowrite32(params_vdev,
1745 ISP2X_PACK_2SHORT(arg->sw_rawawb_th2_ls0,
1746 arg->sw_rawawb_th3_ls0),
1747 ISP21_RAWAWB_YUV_INTERP_CURVE_TH1_0);
1748
1749 rkisp_iowrite32(params_vdev,
1750 ISP2X_PACK_2SHORT(arg->sw_rawawb_th4_ls0,
1751 arg->sw_rawawb_th5_ls0),
1752 ISP21_RAWAWB_YUV_INTERP_CURVE_TH2_0);
1753
1754 rkisp_iowrite32(params_vdev,
1755 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls1_y,
1756 arg->sw_rawawb_vec_x21_ls1_y),
1757 ISP21_RAWAWB_YUV_X_COOR_Y_1);
1758
1759 rkisp_iowrite32(params_vdev,
1760 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls1_u,
1761 arg->sw_rawawb_vec_x21_ls1_u),
1762 ISP21_RAWAWB_YUV_X_COOR_U_1);
1763
1764 rkisp_iowrite32(params_vdev,
1765 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls1_v,
1766 arg->sw_rawawb_vec_x21_ls1_v),
1767 ISP21_RAWAWB_YUV_X_COOR_V_1);
1768
1769 rkisp_iowrite32(params_vdev,
1770 ISP2X_PACK_4BYTE(arg->sw_rawawb_dis_x1x2_ls1,
1771 0,
1772 arg->sw_rawawb_rotu0_ls1,
1773 arg->sw_rawawb_rotu1_ls1),
1774 ISP21_RAWAWB_YUV_X1X2_DIS_1);
1775
1776 rkisp_iowrite32(params_vdev,
1777 ISP2X_PACK_4BYTE(arg->sw_rawawb_rotu2_ls1,
1778 arg->sw_rawawb_rotu3_ls1,
1779 arg->sw_rawawb_rotu4_ls1,
1780 arg->sw_rawawb_rotu5_ls1),
1781 ISP21_RAWAWB_YUV_INTERP_CURVE_UCOOR_1);
1782
1783 rkisp_iowrite32(params_vdev,
1784 ISP2X_PACK_2SHORT(arg->sw_rawawb_th0_ls1,
1785 arg->sw_rawawb_th1_ls1),
1786 ISP21_RAWAWB_YUV_INTERP_CURVE_TH0_1);
1787
1788 rkisp_iowrite32(params_vdev,
1789 ISP2X_PACK_2SHORT(arg->sw_rawawb_th2_ls1,
1790 arg->sw_rawawb_th3_ls1),
1791 ISP21_RAWAWB_YUV_INTERP_CURVE_TH1_1);
1792
1793 rkisp_iowrite32(params_vdev,
1794 ISP2X_PACK_2SHORT(arg->sw_rawawb_th4_ls1,
1795 arg->sw_rawawb_th5_ls1),
1796 ISP21_RAWAWB_YUV_INTERP_CURVE_TH2_1);
1797
1798 rkisp_iowrite32(params_vdev,
1799 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls2_y,
1800 arg->sw_rawawb_vec_x21_ls2_y),
1801 ISP21_RAWAWB_YUV_X_COOR_Y_2);
1802
1803 rkisp_iowrite32(params_vdev,
1804 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls2_u,
1805 arg->sw_rawawb_vec_x21_ls2_u),
1806 ISP21_RAWAWB_YUV_X_COOR_U_2);
1807
1808 rkisp_iowrite32(params_vdev,
1809 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls2_v,
1810 arg->sw_rawawb_vec_x21_ls2_v),
1811 ISP21_RAWAWB_YUV_X_COOR_V_2);
1812
1813 rkisp_iowrite32(params_vdev,
1814 ISP2X_PACK_4BYTE(arg->sw_rawawb_dis_x1x2_ls2,
1815 0,
1816 arg->sw_rawawb_rotu0_ls2,
1817 arg->sw_rawawb_rotu1_ls2),
1818 ISP21_RAWAWB_YUV_X1X2_DIS_2);
1819
1820 rkisp_iowrite32(params_vdev,
1821 ISP2X_PACK_4BYTE(arg->sw_rawawb_rotu2_ls2,
1822 arg->sw_rawawb_rotu3_ls2,
1823 arg->sw_rawawb_rotu4_ls2,
1824 arg->sw_rawawb_rotu5_ls2),
1825 ISP21_RAWAWB_YUV_INTERP_CURVE_UCOOR_2);
1826
1827 rkisp_iowrite32(params_vdev,
1828 ISP2X_PACK_2SHORT(arg->sw_rawawb_th0_ls2,
1829 arg->sw_rawawb_th1_ls2),
1830 ISP21_RAWAWB_YUV_INTERP_CURVE_TH0_2);
1831
1832 rkisp_iowrite32(params_vdev,
1833 ISP2X_PACK_2SHORT(arg->sw_rawawb_th2_ls2,
1834 arg->sw_rawawb_th3_ls2),
1835 ISP21_RAWAWB_YUV_INTERP_CURVE_TH1_2);
1836
1837 rkisp_iowrite32(params_vdev,
1838 ISP2X_PACK_2SHORT(arg->sw_rawawb_th4_ls2,
1839 arg->sw_rawawb_th5_ls2),
1840 ISP21_RAWAWB_YUV_INTERP_CURVE_TH2_2);
1841
1842 rkisp_iowrite32(params_vdev,
1843 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls3_y,
1844 arg->sw_rawawb_vec_x21_ls3_y),
1845 ISP21_RAWAWB_YUV_X_COOR_Y_3);
1846
1847 rkisp_iowrite32(params_vdev,
1848 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls3_u,
1849 arg->sw_rawawb_vec_x21_ls3_u),
1850 ISP21_RAWAWB_YUV_X_COOR_U_3);
1851
1852 rkisp_iowrite32(params_vdev,
1853 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls3_v,
1854 arg->sw_rawawb_vec_x21_ls3_v),
1855 ISP21_RAWAWB_YUV_X_COOR_V_3);
1856
1857 rkisp_iowrite32(params_vdev,
1858 ISP2X_PACK_4BYTE(arg->sw_rawawb_dis_x1x2_ls3,
1859 0,
1860 arg->sw_rawawb_rotu0_ls3,
1861 arg->sw_rawawb_rotu1_ls3),
1862 ISP21_RAWAWB_YUV_X1X2_DIS_3);
1863
1864 rkisp_iowrite32(params_vdev,
1865 ISP2X_PACK_4BYTE(arg->sw_rawawb_rotu2_ls3,
1866 arg->sw_rawawb_rotu3_ls3,
1867 arg->sw_rawawb_rotu4_ls3,
1868 arg->sw_rawawb_rotu5_ls3),
1869 ISP21_RAWAWB_YUV_INTERP_CURVE_UCOOR_3);
1870
1871 rkisp_iowrite32(params_vdev,
1872 ISP2X_PACK_2SHORT(arg->sw_rawawb_th0_ls3,
1873 arg->sw_rawawb_th1_ls3),
1874 ISP21_RAWAWB_YUV_INTERP_CURVE_TH0_3);
1875
1876 rkisp_iowrite32(params_vdev,
1877 ISP2X_PACK_2SHORT(arg->sw_rawawb_th2_ls3,
1878 arg->sw_rawawb_th3_ls3),
1879 ISP21_RAWAWB_YUV_INTERP_CURVE_TH1_3);
1880
1881 rkisp_iowrite32(params_vdev,
1882 ISP2X_PACK_2SHORT(arg->sw_rawawb_th4_ls3,
1883 arg->sw_rawawb_th5_ls3),
1884 ISP21_RAWAWB_YUV_INTERP_CURVE_TH2_3);
1885
1886 rkisp_iowrite32(params_vdev,
1887 ISP2X_PACK_2SHORT(arg->sw_rawawb_wt0,
1888 arg->sw_rawawb_wt1),
1889 ISP21_RAWAWB_RGB2XY_WT01);
1890
1891 rkisp_iowrite32(params_vdev,
1892 arg->sw_rawawb_wt2,
1893 ISP21_RAWAWB_RGB2XY_WT2);
1894
1895 rkisp_iowrite32(params_vdev,
1896 ISP2X_PACK_2SHORT(arg->sw_rawawb_mat0_x,
1897 arg->sw_rawawb_mat0_y),
1898 ISP21_RAWAWB_RGB2XY_MAT0_XY);
1899
1900 rkisp_iowrite32(params_vdev,
1901 ISP2X_PACK_2SHORT(arg->sw_rawawb_mat1_x,
1902 arg->sw_rawawb_mat1_y),
1903 ISP21_RAWAWB_RGB2XY_MAT1_XY);
1904
1905 rkisp_iowrite32(params_vdev,
1906 ISP2X_PACK_2SHORT(arg->sw_rawawb_mat2_x,
1907 arg->sw_rawawb_mat2_y),
1908 ISP21_RAWAWB_RGB2XY_MAT2_XY);
1909
1910 rkisp_iowrite32(params_vdev,
1911 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_x0_0,
1912 arg->sw_rawawb_nor_x1_0),
1913 ISP21_RAWAWB_XY_DETC_NOR_X_0);
1914
1915 rkisp_iowrite32(params_vdev,
1916 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_y0_0,
1917 arg->sw_rawawb_nor_y1_0),
1918 ISP21_RAWAWB_XY_DETC_NOR_Y_0);
1919
1920 rkisp_iowrite32(params_vdev,
1921 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_x0_0,
1922 arg->sw_rawawb_big_x1_0),
1923 ISP21_RAWAWB_XY_DETC_BIG_X_0);
1924
1925 rkisp_iowrite32(params_vdev,
1926 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_y0_0,
1927 arg->sw_rawawb_big_y1_0),
1928 ISP21_RAWAWB_XY_DETC_BIG_Y_0);
1929
1930 rkisp_iowrite32(params_vdev,
1931 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_x0_1,
1932 arg->sw_rawawb_nor_x1_1),
1933 ISP21_RAWAWB_XY_DETC_NOR_X_1);
1934
1935 rkisp_iowrite32(params_vdev,
1936 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_y0_1,
1937 arg->sw_rawawb_nor_y1_1),
1938 ISP21_RAWAWB_XY_DETC_NOR_Y_1);
1939
1940 rkisp_iowrite32(params_vdev,
1941 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_x0_1,
1942 arg->sw_rawawb_big_x1_1),
1943 ISP21_RAWAWB_XY_DETC_BIG_X_1);
1944
1945 rkisp_iowrite32(params_vdev,
1946 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_y0_1,
1947 arg->sw_rawawb_big_y1_1),
1948 ISP21_RAWAWB_XY_DETC_BIG_Y_1);
1949
1950 rkisp_iowrite32(params_vdev,
1951 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_x0_2,
1952 arg->sw_rawawb_nor_x1_2),
1953 ISP21_RAWAWB_XY_DETC_NOR_X_2);
1954
1955 rkisp_iowrite32(params_vdev,
1956 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_y0_2,
1957 arg->sw_rawawb_nor_y1_2),
1958 ISP21_RAWAWB_XY_DETC_NOR_Y_2);
1959
1960 rkisp_iowrite32(params_vdev,
1961 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_x0_2,
1962 arg->sw_rawawb_big_x1_2),
1963 ISP21_RAWAWB_XY_DETC_BIG_X_2);
1964
1965 rkisp_iowrite32(params_vdev,
1966 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_y0_2,
1967 arg->sw_rawawb_big_y1_2),
1968 ISP21_RAWAWB_XY_DETC_BIG_Y_2);
1969
1970 rkisp_iowrite32(params_vdev,
1971 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_x0_3,
1972 arg->sw_rawawb_nor_x1_3),
1973 ISP21_RAWAWB_XY_DETC_NOR_X_3);
1974
1975 rkisp_iowrite32(params_vdev,
1976 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_y0_3,
1977 arg->sw_rawawb_nor_y1_3),
1978 ISP21_RAWAWB_XY_DETC_NOR_Y_3);
1979
1980 rkisp_iowrite32(params_vdev,
1981 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_x0_3,
1982 arg->sw_rawawb_big_x1_3),
1983 ISP21_RAWAWB_XY_DETC_BIG_X_3);
1984
1985 rkisp_iowrite32(params_vdev,
1986 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_y0_3,
1987 arg->sw_rawawb_big_y1_3),
1988 ISP21_RAWAWB_XY_DETC_BIG_Y_3);
1989
1990 rkisp_iowrite32(params_vdev,
1991 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_x0_4,
1992 arg->sw_rawawb_nor_x1_4),
1993 ISP21_RAWAWB_XY_DETC_NOR_X_4);
1994
1995 rkisp_iowrite32(params_vdev,
1996 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_y0_4,
1997 arg->sw_rawawb_nor_y1_4),
1998 ISP21_RAWAWB_XY_DETC_NOR_Y_4);
1999
2000 rkisp_iowrite32(params_vdev,
2001 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_x0_4,
2002 arg->sw_rawawb_big_x1_4),
2003 ISP21_RAWAWB_XY_DETC_BIG_X_4);
2004
2005 rkisp_iowrite32(params_vdev,
2006 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_y0_4,
2007 arg->sw_rawawb_big_y1_4),
2008 ISP21_RAWAWB_XY_DETC_BIG_Y_4);
2009
2010 rkisp_iowrite32(params_vdev,
2011 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_x0_5,
2012 arg->sw_rawawb_nor_x1_5),
2013 ISP21_RAWAWB_XY_DETC_NOR_X_5);
2014
2015 rkisp_iowrite32(params_vdev,
2016 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_y0_5,
2017 arg->sw_rawawb_nor_y1_5),
2018 ISP21_RAWAWB_XY_DETC_NOR_Y_5);
2019
2020 rkisp_iowrite32(params_vdev,
2021 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_x0_5,
2022 arg->sw_rawawb_big_x1_5),
2023 ISP21_RAWAWB_XY_DETC_BIG_X_5);
2024
2025 rkisp_iowrite32(params_vdev,
2026 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_y0_5,
2027 arg->sw_rawawb_big_y1_5),
2028 ISP21_RAWAWB_XY_DETC_BIG_Y_5);
2029
2030 rkisp_iowrite32(params_vdev,
2031 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_x0_6,
2032 arg->sw_rawawb_nor_x1_6),
2033 ISP21_RAWAWB_XY_DETC_NOR_X_6);
2034
2035 rkisp_iowrite32(params_vdev,
2036 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_y0_6,
2037 arg->sw_rawawb_nor_y1_6),
2038 ISP21_RAWAWB_XY_DETC_NOR_Y_6);
2039
2040 rkisp_iowrite32(params_vdev,
2041 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_x0_6,
2042 arg->sw_rawawb_big_x1_6),
2043 ISP21_RAWAWB_XY_DETC_BIG_X_6);
2044
2045 rkisp_iowrite32(params_vdev,
2046 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_y0_6,
2047 arg->sw_rawawb_big_y1_6),
2048 ISP21_RAWAWB_XY_DETC_BIG_Y_6);
2049
2050 rkisp_iowrite32(params_vdev,
2051 (arg->sw_rawawb_exc_wp_region0_excen0 & 0x1) << 0 |
2052 (arg->sw_rawawb_exc_wp_region0_excen1 & 0x1) << 1 |
2053 (arg->sw_rawawb_exc_wp_region0_domain & 0x1) << 3 |
2054 (arg->sw_rawawb_exc_wp_region1_excen0 & 0x1) << 4 |
2055 (arg->sw_rawawb_exc_wp_region1_excen1 & 0x1) << 5 |
2056 (arg->sw_rawawb_exc_wp_region1_domain & 0x1) << 7 |
2057 (arg->sw_rawawb_exc_wp_region2_excen0 & 0x1) << 8 |
2058 (arg->sw_rawawb_exc_wp_region2_excen1 & 0x1) << 9 |
2059 (arg->sw_rawawb_exc_wp_region2_domain & 0x1) << 11 |
2060 (arg->sw_rawawb_exc_wp_region3_excen0 & 0x1) << 12 |
2061 (arg->sw_rawawb_exc_wp_region3_excen1 & 0x1) << 13 |
2062 (arg->sw_rawawb_exc_wp_region3_domain & 0x1) << 15 |
2063 (arg->sw_rawawb_exc_wp_region4_excen0 & 0x1) << 16 |
2064 (arg->sw_rawawb_exc_wp_region4_excen1 & 0x1) << 17 |
2065 (arg->sw_rawawb_exc_wp_region4_domain & 0x1) << 19 |
2066 (arg->sw_rawawb_exc_wp_region5_excen0 & 0x1) << 20 |
2067 (arg->sw_rawawb_exc_wp_region5_excen1 & 0x1) << 21 |
2068 (arg->sw_rawawb_exc_wp_region5_domain & 0x1) << 23 |
2069 (arg->sw_rawawb_exc_wp_region6_excen0 & 0x1) << 24 |
2070 (arg->sw_rawawb_exc_wp_region6_excen1 & 0x1) << 25 |
2071 (arg->sw_rawawb_exc_wp_region6_domain & 0x1) << 27,
2072 ISP21_RAWAWB_MULTIWINDOW_EXC_CTRL);
2073
2074 rkisp_iowrite32(params_vdev,
2075 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region0_xu0,
2076 arg->sw_rawawb_exc_wp_region0_xu1),
2077 ISP21_RAWAWB_EXC_WP_REGION0_XU);
2078
2079 rkisp_iowrite32(params_vdev,
2080 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region0_yv0,
2081 arg->sw_rawawb_exc_wp_region0_yv1),
2082 ISP21_RAWAWB_EXC_WP_REGION0_YV);
2083
2084 rkisp_iowrite32(params_vdev,
2085 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region1_xu0,
2086 arg->sw_rawawb_exc_wp_region1_xu1),
2087 ISP21_RAWAWB_EXC_WP_REGION1_XU);
2088
2089 rkisp_iowrite32(params_vdev,
2090 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region1_yv0,
2091 arg->sw_rawawb_exc_wp_region1_yv1),
2092 ISP21_RAWAWB_EXC_WP_REGION1_YV);
2093
2094 rkisp_iowrite32(params_vdev,
2095 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region2_xu0,
2096 arg->sw_rawawb_exc_wp_region2_xu1),
2097 ISP21_RAWAWB_EXC_WP_REGION2_XU);
2098
2099 rkisp_iowrite32(params_vdev,
2100 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region2_yv0,
2101 arg->sw_rawawb_exc_wp_region2_yv1),
2102 ISP21_RAWAWB_EXC_WP_REGION2_YV);
2103
2104 rkisp_iowrite32(params_vdev,
2105 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region3_xu0,
2106 arg->sw_rawawb_exc_wp_region3_xu1),
2107 ISP21_RAWAWB_EXC_WP_REGION3_XU);
2108
2109 rkisp_iowrite32(params_vdev,
2110 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region3_yv0,
2111 arg->sw_rawawb_exc_wp_region3_yv1),
2112 ISP21_RAWAWB_EXC_WP_REGION3_YV);
2113
2114 rkisp_iowrite32(params_vdev,
2115 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region4_xu0,
2116 arg->sw_rawawb_exc_wp_region4_xu1),
2117 ISP21_RAWAWB_EXC_WP_REGION4_XU);
2118
2119 rkisp_iowrite32(params_vdev,
2120 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region4_yv0,
2121 arg->sw_rawawb_exc_wp_region4_yv1),
2122 ISP21_RAWAWB_EXC_WP_REGION4_YV);
2123
2124 rkisp_iowrite32(params_vdev,
2125 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region5_xu0,
2126 arg->sw_rawawb_exc_wp_region5_xu1),
2127 ISP21_RAWAWB_EXC_WP_REGION5_XU);
2128
2129 rkisp_iowrite32(params_vdev,
2130 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region5_yv0,
2131 arg->sw_rawawb_exc_wp_region5_yv1),
2132 ISP21_RAWAWB_EXC_WP_REGION5_YV);
2133
2134 rkisp_iowrite32(params_vdev,
2135 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region6_xu0,
2136 arg->sw_rawawb_exc_wp_region6_xu1),
2137 ISP21_RAWAWB_EXC_WP_REGION6_XU);
2138
2139 rkisp_iowrite32(params_vdev,
2140 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region6_yv0,
2141 arg->sw_rawawb_exc_wp_region6_yv1),
2142 ISP21_RAWAWB_EXC_WP_REGION6_YV);
2143
2144 if (params_vdev->dev->hw_dev->is_single)
2145 isp_rawawb_cfg_sram(params_vdev, arg, false);
2146 else
2147 memcpy(arg_rec->sw_rawawb_wp_blk_wei_w,
2148 arg->sw_rawawb_wp_blk_wei_w,
2149 ISP21_RAWAWB_WEIGHT_NUM);
2150
2151 /* avoid to override the old enable value */
2152 value = rkisp_ioread32(params_vdev, ISP21_RAWAWB_CTRL);
2153 value &= ISP2X_RAWAWB_ENA;
2154 value &= ~ISP2X_REG_WR_MASK;
2155 rkisp_iowrite32(params_vdev,
2156 value |
2157 (arg->sw_rawawb_uv_en0 & 0x1) << 1 |
2158 (arg->sw_rawawb_xy_en0 & 0x1) << 2 |
2159 (arg->sw_rawawb_3dyuv_en0 & 0x1) << 3 |
2160 (arg->sw_rawawb_3dyuv_ls_idx0 & 0x7) << 4 |
2161 (arg->sw_rawawb_3dyuv_ls_idx1 & 0x7) << 7 |
2162 (arg->sw_rawawb_3dyuv_ls_idx2 & 0x7) << 10 |
2163 (arg->sw_rawawb_3dyuv_ls_idx3 & 0x7) << 13 |
2164 (arg->sw_rawawb_wind_size & 0x1) << 18 |
2165 (arg->sw_rawlsc_bypass_en & 0x1) << 19 |
2166 (arg->sw_rawawb_light_num & 0x7) << 20 |
2167 (arg->sw_rawawb_uv_en1 & 0x1) << 24 |
2168 (arg->sw_rawawb_xy_en1 & 0x1) << 25 |
2169 (arg->sw_rawawb_3dyuv_en1 & 0x1) << 26,
2170 ISP21_RAWAWB_CTRL);
2171
2172 value = rkisp_ioread32(params_vdev, CTRL_VI_ISP_PATH);
2173 value &= ~(ISP2X_ISPPATH_RAWAWB_SEL_SET(3));
2174 value |= ISP2X_ISPPATH_RAWAWB_SEL_SET(arg->rawawb_sel);
2175 rkisp_iowrite32(params_vdev, value, CTRL_VI_ISP_PATH);
2176 }
2177
2178 static void
isp_rawawb_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2179 isp_rawawb_enable(struct rkisp_isp_params_vdev *params_vdev,
2180 bool en)
2181 {
2182 u32 awb_ctrl;
2183
2184 awb_ctrl = rkisp_ioread32(params_vdev, ISP21_RAWAWB_CTRL);
2185 awb_ctrl &= ~ISP2X_REG_WR_MASK;
2186 if (en)
2187 awb_ctrl |= ISP2X_RAWAWB_ENA;
2188 else
2189 awb_ctrl &= ~ISP2X_RAWAWB_ENA;
2190
2191 rkisp_iowrite32(params_vdev, awb_ctrl, ISP21_RAWAWB_CTRL);
2192 }
2193
2194 static void
isp_rawhstlite_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistlite_cfg * arg)2195 isp_rawhstlite_config(struct rkisp_isp_params_vdev *params_vdev,
2196 const struct isp2x_rawhistlite_cfg *arg)
2197 {
2198 u32 i;
2199 u32 value;
2200 u32 hist_ctrl;
2201 u32 block_hsize, block_vsize;
2202
2203 /* avoid to override the old enable value */
2204 hist_ctrl = rkisp_ioread32(params_vdev,
2205 ISP_RAWHIST_LITE_CTRL);
2206 hist_ctrl &= ISP2X_RAWHSTLITE_CTRL_EN_MASK;
2207 hist_ctrl &= ~ISP2X_REG_WR_MASK;
2208 hist_ctrl = hist_ctrl |
2209 ISP2X_RAWHSTLITE_CTRL_MODE_SET(arg->mode) |
2210 ISP2X_RAWHSTLITE_CTRL_DATASEL_SET(arg->data_sel) |
2211 ISP2X_RAWHSTLITE_CTRL_WATERLINE_SET(arg->waterline) |
2212 ISP2X_RAWHSTLITE_CTRL_STEPSIZE_SET(arg->stepsize);
2213 rkisp_iowrite32(params_vdev, hist_ctrl,
2214 ISP_RAWHIST_LITE_CTRL);
2215
2216 rkisp_iowrite32(params_vdev,
2217 ISP2X_RAWHSTLITE_OFFS_SET(arg->win.h_offs & 0xFFFE,
2218 arg->win.v_offs & 0xFFFE),
2219 ISP_RAWHIST_LITE_OFFS);
2220
2221 block_hsize = arg->win.h_size / ISP2X_RAWHSTLITE_ROW_NUM - 1;
2222 block_vsize = arg->win.v_size / ISP2X_RAWHSTLITE_COLUMN_NUM - 1;
2223 block_hsize &= 0xFFFE;
2224 block_vsize &= 0xFFFE;
2225 rkisp_iowrite32(params_vdev,
2226 ISP2X_RAWHSTLITE_SIZE_SET(block_hsize, block_vsize),
2227 ISP_RAWHIST_LITE_SIZE);
2228
2229 rkisp_iowrite32(params_vdev,
2230 ISP2X_PACK_4BYTE(arg->rcc, arg->gcc, arg->bcc, arg->off),
2231 ISP_RAWHIST_LITE_RAW2Y_CC);
2232
2233 for (i = 0; i < (ISP2X_RAWHSTLITE_WEIGHT_REG_SIZE / 4); i++) {
2234 value = ISP2X_RAWHSTLITE_WEIGHT_SET(
2235 arg->weight[4 * i + 0],
2236 arg->weight[4 * i + 1],
2237 arg->weight[4 * i + 2],
2238 arg->weight[4 * i + 3]);
2239 rkisp_iowrite32(params_vdev, value,
2240 ISP_RAWHIST_LITE_WEIGHT + 4 * i);
2241 }
2242
2243 value = ISP2X_RAWHSTLITE_WEIGHT_SET(
2244 arg->weight[4 * i + 0], 0, 0, 0);
2245 rkisp_iowrite32(params_vdev, value,
2246 ISP_RAWHIST_LITE_WEIGHT + 4 * i);
2247 }
2248
2249 static void
isp_rawhstlite_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2250 isp_rawhstlite_enable(struct rkisp_isp_params_vdev *params_vdev,
2251 bool en)
2252 {
2253 u32 hist_ctrl;
2254
2255 hist_ctrl = rkisp_ioread32(params_vdev,
2256 ISP_RAWHIST_LITE_CTRL);
2257 hist_ctrl &= ~(ISP2X_RAWHSTLITE_CTRL_EN_MASK | ISP2X_REG_WR_MASK);
2258
2259 if (en)
2260 hist_ctrl |= ISP2X_RAWHSTLITE_CTRL_EN_SET(0x1);
2261
2262 rkisp_iowrite32(params_vdev, hist_ctrl,
2263 ISP_RAWHIST_LITE_CTRL);
2264 }
2265
2266 static void
isp_rawhstbig_cfg_sram(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg,u32 blk_no,bool is_check)2267 isp_rawhstbig_cfg_sram(struct rkisp_isp_params_vdev *params_vdev,
2268 const struct isp2x_rawhistbig_cfg *arg,
2269 u32 blk_no, bool is_check)
2270 {
2271 u32 i, j, wnd_num_idx, value;
2272 u8 weight15x15[ISP2X_RAWHSTBIG_WEIGHT_REG_SIZE];
2273 const u32 hist_wnd_num[] = { 5, 5, 15, 15 };
2274 u32 addr;
2275
2276 switch (blk_no) {
2277 case 1:
2278 addr = ISP_RAWHIST_BIG2_BASE;
2279 break;
2280 case 2:
2281 addr = ISP_RAWHIST_BIG3_BASE;
2282 break;
2283 case 0:
2284 default:
2285 addr = ISP_RAWHIST_BIG1_BASE;
2286 break;
2287 }
2288
2289 value = ISP2X_RAWHSTBIG_CTRL_EN_MASK;
2290 if (is_check &&
2291 !(rkisp_ioread32(params_vdev, addr + ISP_RAWHIST_BIG_CTRL) & value))
2292 return;
2293
2294 wnd_num_idx = arg->wnd_num;
2295 memset(weight15x15, 0, sizeof(weight15x15));
2296 for (i = 0; i < hist_wnd_num[wnd_num_idx]; i++) {
2297 for (j = 0; j < hist_wnd_num[wnd_num_idx]; j++) {
2298 weight15x15[i * ISP2X_RAWHSTBIG_ROW_NUM + j] =
2299 arg->weight[i * hist_wnd_num[wnd_num_idx] + j];
2300 }
2301 }
2302
2303 for (i = 0; i < (ISP2X_RAWHSTBIG_WEIGHT_REG_SIZE / 5); i++) {
2304 value = ISP2X_RAWHSTBIG_WEIGHT_SET(weight15x15[5 * i + 0],
2305 weight15x15[5 * i + 1],
2306 weight15x15[5 * i + 2],
2307 weight15x15[5 * i + 3],
2308 weight15x15[5 * i + 4]);
2309 rkisp_write(params_vdev->dev, addr + ISP_RAWHIST_BIG_WEIGHT_BASE,
2310 value, true);
2311 }
2312 }
2313
2314 static void
isp_rawhstbig_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg,u32 blk_no)2315 isp_rawhstbig_config(struct rkisp_isp_params_vdev *params_vdev,
2316 const struct isp2x_rawhistbig_cfg *arg, u32 blk_no)
2317 {
2318 struct isp21_isp_params_cfg *params_rec = params_vdev->isp21_params;
2319 struct rkisp_device *dev = params_vdev->dev;
2320 struct isp2x_rawhistbig_cfg *arg_rec;
2321 u32 hist_ctrl, block_hsize, block_vsize, wnd_num_idx;
2322 const u32 hist_wnd_num[] = { 5, 5, 15, 15 };
2323 u32 addr;
2324
2325 switch (blk_no) {
2326 case 1:
2327 addr = ISP_RAWHIST_BIG2_BASE;
2328 arg_rec = ¶ms_rec->meas.rawhist1;
2329 break;
2330 case 2:
2331 addr = ISP_RAWHIST_BIG3_BASE;
2332 arg_rec = ¶ms_rec->meas.rawhist2;
2333 break;
2334 case 0:
2335 default:
2336 addr = ISP_RAWHIST_BIG1_BASE;
2337 arg_rec = ¶ms_rec->meas.rawhist3;
2338 break;
2339 }
2340
2341 wnd_num_idx = arg->wnd_num;
2342 /* avoid to override the old enable value */
2343 hist_ctrl = rkisp_ioread32(params_vdev, addr + ISP_RAWHIST_BIG_CTRL);
2344 hist_ctrl &= ISP2X_RAWHSTBIG_CTRL_EN_MASK;
2345 hist_ctrl &= ~ISP2X_REG_WR_MASK;
2346 hist_ctrl = hist_ctrl |
2347 ISP2X_RAWHSTBIG_CTRL_MODE_SET(arg->mode) |
2348 ISP2X_RAWHSTBIG_CTRL_DATASEL_SET(arg->data_sel) |
2349 ISP2X_RAWHSTBIG_CTRL_WATERLINE_SET(arg->waterline) |
2350 ISP2X_RAWHSTBIG_CTRL_WNDNUM_SET(arg->wnd_num) |
2351 ISP2X_RAWHSTBIG_CTRL_STEPSIZE_SET(arg->stepsize);
2352 rkisp_iowrite32(params_vdev, hist_ctrl, addr + ISP_RAWHIST_BIG_CTRL);
2353
2354 rkisp_iowrite32(params_vdev,
2355 ISP2X_RAWHSTBIG_OFFS_SET(arg->win.h_offs & 0xFFFE,
2356 arg->win.v_offs & 0xFFFE),
2357 addr + ISP_RAWHIST_BIG_OFFS);
2358
2359 block_hsize = arg->win.h_size / hist_wnd_num[wnd_num_idx] - 1;
2360 block_vsize = arg->win.v_size / hist_wnd_num[wnd_num_idx] - 1;
2361 block_hsize &= 0xFFFE;
2362 block_vsize &= 0xFFFE;
2363 rkisp_iowrite32(params_vdev,
2364 ISP2X_RAWHSTBIG_SIZE_SET(block_hsize, block_vsize),
2365 addr + ISP_RAWHIST_BIG_SIZE);
2366
2367 rkisp_iowrite32(params_vdev,
2368 ISP2X_PACK_4BYTE(arg->rcc, arg->gcc, arg->bcc, arg->off),
2369 addr + ISP_RAWHIST_BIG_RAW2Y_CC);
2370
2371 if (dev->hw_dev->is_single)
2372 isp_rawhstbig_cfg_sram(params_vdev, arg, blk_no, false);
2373 else
2374 *arg_rec = *arg;
2375 }
2376
2377 static void
isp_rawhstbig_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 blk_no)2378 isp_rawhstbig_enable(struct rkisp_isp_params_vdev *params_vdev,
2379 bool en, u32 blk_no)
2380 {
2381 u32 hist_ctrl;
2382 u32 addr;
2383
2384 switch (blk_no) {
2385 case 0:
2386 addr = ISP_RAWHIST_BIG1_BASE;
2387 break;
2388 case 1:
2389 addr = ISP_RAWHIST_BIG2_BASE;
2390 break;
2391 case 2:
2392 addr = ISP_RAWHIST_BIG3_BASE;
2393 break;
2394 default:
2395 addr = ISP_RAWHIST_BIG1_BASE;
2396 break;
2397 }
2398
2399 hist_ctrl = rkisp_ioread32(params_vdev, addr + ISP_RAWHIST_BIG_CTRL);
2400 hist_ctrl &= ~(ISP2X_RAWHSTBIG_CTRL_EN_MASK | ISP2X_REG_WR_MASK);
2401 if (en)
2402 hist_ctrl |= ISP2X_RAWHSTBIG_CTRL_EN_SET(0x1);
2403
2404 rkisp_iowrite32(params_vdev, hist_ctrl, addr + ISP_RAWHIST_BIG_CTRL);
2405 }
2406
2407 static void
isp_rawhst1_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg)2408 isp_rawhst1_config(struct rkisp_isp_params_vdev *params_vdev,
2409 const struct isp2x_rawhistbig_cfg *arg)
2410 {
2411 isp_rawhstbig_config(params_vdev, arg, 1);
2412 }
2413
2414 static void
isp_rawhst1_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2415 isp_rawhst1_enable(struct rkisp_isp_params_vdev *params_vdev,
2416 bool en)
2417 {
2418 isp_rawhstbig_enable(params_vdev, en, 1);
2419 }
2420
2421 static void
isp_rawhst2_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg)2422 isp_rawhst2_config(struct rkisp_isp_params_vdev *params_vdev,
2423 const struct isp2x_rawhistbig_cfg *arg)
2424 {
2425 isp_rawhstbig_config(params_vdev, arg, 2);
2426 }
2427
2428 static void
isp_rawhst2_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2429 isp_rawhst2_enable(struct rkisp_isp_params_vdev *params_vdev,
2430 bool en)
2431 {
2432 isp_rawhstbig_enable(params_vdev, en, 2);
2433 }
2434
2435 static void
isp_rawhst3_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg)2436 isp_rawhst3_config(struct rkisp_isp_params_vdev *params_vdev,
2437 const struct isp2x_rawhistbig_cfg *arg)
2438 {
2439 isp_rawhstbig_config(params_vdev, arg, 0);
2440 }
2441
2442 static void
isp_rawhst3_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2443 isp_rawhst3_enable(struct rkisp_isp_params_vdev *params_vdev,
2444 bool en)
2445 {
2446 isp_rawhstbig_enable(params_vdev, en, 0);
2447 }
2448
2449 static void
isp_hdrmge_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_hdrmge_cfg * arg,enum rkisp_params_type type)2450 isp_hdrmge_config(struct rkisp_isp_params_vdev *params_vdev,
2451 const struct isp2x_hdrmge_cfg *arg, enum rkisp_params_type type)
2452 {
2453 u32 value;
2454 int i;
2455
2456 if (type == RKISP_PARAMS_SHD || type == RKISP_PARAMS_ALL) {
2457 value = ISP2X_PACK_2SHORT(arg->gain0, arg->gain0_inv);
2458 rkisp_iowrite32(params_vdev, value, ISP_HDRMGE_GAIN0);
2459
2460 value = ISP2X_PACK_2SHORT(arg->gain1, arg->gain1_inv);
2461 rkisp_iowrite32(params_vdev, value, ISP_HDRMGE_GAIN1);
2462
2463 value = arg->gain2;
2464 rkisp_iowrite32(params_vdev, value, ISP_HDRMGE_GAIN2);
2465 }
2466
2467 if (type == RKISP_PARAMS_IMD || type == RKISP_PARAMS_ALL) {
2468 value = ISP2X_PACK_4BYTE(arg->ms_dif_0p8, arg->ms_diff_0p15,
2469 arg->lm_dif_0p9, arg->lm_dif_0p15);
2470 rkisp_iowrite32(params_vdev, value, ISP_HDRMGE_CONS_DIFF);
2471
2472 for (i = 0; i < ISP2X_HDRMGE_L_CURVE_NUM; i++) {
2473 value = ISP2X_PACK_2SHORT(arg->curve.curve_0[i], arg->curve.curve_1[i]);
2474 rkisp_iowrite32(params_vdev, value, ISP_HDRMGE_DIFF_Y0 + 4 * i);
2475 }
2476
2477 for (i = 0; i < ISP2X_HDRMGE_E_CURVE_NUM; i++) {
2478 value = arg->e_y[i];
2479 rkisp_iowrite32(params_vdev, value, ISP_HDRMGE_OVER_Y0 + 4 * i);
2480 }
2481 }
2482 }
2483
2484 static void
isp_hdrmge_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2485 isp_hdrmge_enable(struct rkisp_isp_params_vdev *params_vdev,
2486 bool en)
2487 {
2488 }
2489
2490 static void
isp_hdrdrc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_drc_cfg * arg,enum rkisp_params_type type)2491 isp_hdrdrc_config(struct rkisp_isp_params_vdev *params_vdev,
2492 const struct isp21_drc_cfg *arg, enum rkisp_params_type type)
2493 {
2494 u32 i, value;
2495
2496 if (type == RKISP_PARAMS_IMD)
2497 return;
2498
2499 value = (arg->sw_drc_offset_pow2 & 0x0F) << 28 |
2500 (arg->sw_drc_compres_scl & 0x1FFF) << 14 |
2501 (arg->sw_drc_position & 0x03FFF);
2502 rkisp_iowrite32(params_vdev, value, ISP21_DRC_CTRL1);
2503
2504 value = (arg->sw_drc_delta_scalein & 0xFF) << 24 |
2505 (arg->sw_drc_hpdetail_ratio & 0xFFF) << 12 |
2506 (arg->sw_drc_lpdetail_ratio & 0xFFF);
2507 rkisp_iowrite32(params_vdev, value, ISP21_DRC_LPRATIO);
2508
2509 value = ISP2X_PACK_4BYTE(0, 0, arg->sw_drc_weipre_frame, arg->sw_drc_weicur_pix);
2510 rkisp_iowrite32(params_vdev, value, ISP21_DRC_EXPLRATIO);
2511
2512 value = (arg->sw_drc_force_sgm_inv0 & 0xFFFF) << 16 |
2513 (arg->sw_drc_motion_scl & 0xFF) << 8 |
2514 (arg->sw_drc_edge_scl & 0xFF);
2515 rkisp_iowrite32(params_vdev, value, ISP21_DRC_SIGMA);
2516
2517 value = ISP2X_PACK_2SHORT(arg->sw_drc_space_sgm_inv0, arg->sw_drc_space_sgm_inv1);
2518 rkisp_iowrite32(params_vdev, value, ISP21_DRC_SPACESGM);
2519
2520 value = ISP2X_PACK_2SHORT(arg->sw_drc_range_sgm_inv0, arg->sw_drc_range_sgm_inv1);
2521 rkisp_iowrite32(params_vdev, value, ISP21_DRC_RANESGM);
2522
2523 value = ISP2X_PACK_4BYTE(arg->sw_drc_weig_bilat, arg->sw_drc_weig_maxl, 0, 0);
2524 rkisp_iowrite32(params_vdev, value, ISP21_DRC_BILAT);
2525
2526 for (i = 0; i < ISP21_DRC_Y_NUM / 2; i++) {
2527 value = ISP2X_PACK_2SHORT(arg->sw_drc_gain_y[2 * i],
2528 arg->sw_drc_gain_y[2 * i + 1]);
2529 rkisp_iowrite32(params_vdev, value, ISP21_DRC_GAIN_Y0 + 4 * i);
2530 }
2531
2532 value = ISP2X_PACK_2SHORT(arg->sw_drc_gain_y[2 * i], 0);
2533 rkisp_iowrite32(params_vdev, value, ISP21_DRC_GAIN_Y0 + 4 * i);
2534
2535 for (i = 0; i < ISP21_DRC_Y_NUM / 2; i++) {
2536 value = ISP2X_PACK_2SHORT(arg->sw_drc_compres_y[2 * i],
2537 arg->sw_drc_compres_y[2 * i + 1]);
2538 rkisp_iowrite32(params_vdev, value, ISP21_DRC_COMPRES_Y0 + 4 * i);
2539 }
2540
2541 value = ISP2X_PACK_2SHORT(arg->sw_drc_compres_y[2 * i], 0);
2542 rkisp_iowrite32(params_vdev, value, ISP21_DRC_COMPRES_Y0 + 4 * i);
2543
2544 for (i = 0; i < ISP21_DRC_Y_NUM / 2; i++) {
2545 value = ISP2X_PACK_2SHORT(arg->sw_drc_scale_y[2 * i],
2546 arg->sw_drc_scale_y[2 * i + 1]);
2547 rkisp_iowrite32(params_vdev, value, ISP21_DRC_SCALE_Y0 + 4 * i);
2548 }
2549
2550 value = ISP2X_PACK_2SHORT(arg->sw_drc_scale_y[2 * i], 0);
2551 rkisp_iowrite32(params_vdev, value, ISP21_DRC_SCALE_Y0 + 4 * i);
2552
2553 value = ISP2X_PACK_2SHORT(arg->sw_drc_min_ogain, arg->sw_drc_iir_weight);
2554 rkisp_iowrite32(params_vdev, value, ISP21_DRC_IIRWG_GAIN);
2555 }
2556
2557 static void
isp_hdrdrc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2558 isp_hdrdrc_enable(struct rkisp_isp_params_vdev *params_vdev,
2559 bool en)
2560 {
2561 u32 value;
2562 bool real_en;
2563
2564 value = rkisp_ioread32(params_vdev, ISP21_DRC_CTRL0);
2565 real_en = !!(value & ISP_DRC_EN);
2566 if ((en && real_en) || (!en && !real_en))
2567 return;
2568
2569 if (en) {
2570 value |= ISP_DRC_EN;
2571 rkisp_set_bits(params_vdev->dev, ISP_CTRL1,
2572 ISP2X_SYS_ADRC_FST, ISP2X_SYS_ADRC_FST, false);
2573 } else {
2574 value = 0;
2575 }
2576 rkisp_iowrite32(params_vdev, value, ISP21_DRC_CTRL0);
2577 }
2578
2579 static void
isp_gic_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_gic_cfg * arg)2580 isp_gic_config(struct rkisp_isp_params_vdev *params_vdev,
2581 const struct isp21_gic_cfg *arg)
2582 {
2583 u32 value;
2584 s32 i;
2585
2586 value = (arg->regmingradthrdark2 & 0x03FF) << 20 |
2587 (arg->regmingradthrdark1 & 0x03FF) << 10 |
2588 (arg->regminbusythre & 0x03FF);
2589 rkisp_iowrite32(params_vdev, value, ISP_GIC_DIFF_PARA1);
2590
2591 value = (arg->regdarkthre & 0x07FF) << 21 |
2592 (arg->regmaxcorvboth & 0x03FF) << 11 |
2593 (arg->regdarktthrehi & 0x07FF);
2594 rkisp_iowrite32(params_vdev, value, ISP_GIC_DIFF_PARA2);
2595
2596 value = (arg->regkgrad2dark & 0x0F) << 28 |
2597 (arg->regkgrad1dark & 0x0F) << 24 |
2598 (arg->regstrengthglobal_fix & 0xFF) << 16 |
2599 (arg->regdarkthrestep & 0x0F) << 12 |
2600 (arg->regkgrad2 & 0x0F) << 8 |
2601 (arg->regkgrad1 & 0x0F) << 4 |
2602 (arg->reggbthre & 0x0F);
2603 rkisp_iowrite32(params_vdev, value, ISP_GIC_DIFF_PARA3);
2604
2605 value = (arg->regmaxcorv & 0x03FF) << 20 |
2606 (arg->regmingradthr2 & 0x03FF) << 10 |
2607 (arg->regmingradthr1 & 0x03FF);
2608 rkisp_iowrite32(params_vdev, value, ISP_GIC_DIFF_PARA4);
2609
2610 value = (arg->gr_ratio & 0x03) << 28 |
2611 (arg->noise_scale & 0x7F) << 12 |
2612 (arg->noise_base & 0xFFF);
2613 rkisp_iowrite32(params_vdev, value, ISP_GIC_NOISE_PARA1);
2614
2615 rkisp_iowrite32(params_vdev, arg->diff_clip, ISP_GIC_NOISE_PARA2);
2616
2617 for (i = 0; i < ISP2X_GIC_SIGMA_Y_NUM / 2; i++) {
2618 value = ISP2X_PACK_2SHORT(arg->sigma_y[2 * i], arg->sigma_y[2 * i + 1]);
2619 rkisp_iowrite32(params_vdev, value, ISP_GIC_SIGMA_VALUE0 + 4 * i);
2620 }
2621 value = ISP2X_PACK_2SHORT(arg->sigma_y[2 * i], 0);
2622 rkisp_iowrite32(params_vdev, value, ISP_GIC_SIGMA_VALUE0 + 4 * i);
2623 }
2624
2625 static void
isp_gic_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2626 isp_gic_enable(struct rkisp_isp_params_vdev *params_vdev,
2627 bool en)
2628 {
2629 u32 value = 0;
2630
2631 if (en)
2632 value |= ISP_GIC_ENA;
2633 rkisp_iowrite32(params_vdev, value, ISP_GIC_CONTROL);
2634 }
2635
2636 static void
isp_dhaz_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_dhaz_cfg * arg)2637 isp_dhaz_config(struct rkisp_isp_params_vdev *params_vdev,
2638 const struct isp21_dhaz_cfg *arg)
2639 {
2640 u32 i, value;
2641
2642 value = rkisp_ioread32(params_vdev, ISP21_DHAZ_CTRL);
2643 value &= ISP_DHAZ_ENMUX;
2644
2645 value |= (arg->enhance_en & 0x1) << 20 |
2646 (arg->air_lc_en & 0x1) << 16 |
2647 (arg->hpara_en & 0x1) << 12 |
2648 (arg->hist_en & 0x1) << 8 |
2649 (arg->dc_en & 0x1) << 4;
2650 if (!params_vdev->dev->hw_dev->is_single)
2651 value |= ISP21_SELF_FORCE_UPD;
2652 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_CTRL);
2653
2654 value = ISP2X_PACK_4BYTE(arg->dc_min_th, arg->dc_max_th,
2655 arg->yhist_th, arg->yblk_th);
2656 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_ADP0);
2657
2658 value = ISP2X_PACK_4BYTE(arg->bright_min, arg->bright_max,
2659 arg->wt_max, 0);
2660 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_ADP1);
2661
2662 value = ISP2X_PACK_4BYTE(arg->air_min, arg->air_max,
2663 arg->dark_th, arg->tmax_base);
2664 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_ADP2);
2665
2666 value = ISP2X_PACK_2SHORT(arg->tmax_off, arg->tmax_max);
2667 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_ADP_TMAX);
2668
2669 value = (arg->hist_min & 0xFFFF) << 16 |
2670 (arg->hist_th_off & 0xFF) << 8 |
2671 (arg->hist_k & 0x1F);
2672 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_ADP_HIST0);
2673
2674 value = ISP2X_PACK_2SHORT(arg->hist_scale, arg->hist_gratio);
2675 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_ADP_HIST1);
2676
2677 value = ISP2X_PACK_2SHORT(arg->enhance_chroma, arg->enhance_value);
2678 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_ENHANCE);
2679
2680 value = (arg->iir_wt_sigma & 0x07FF) << 16 |
2681 (arg->iir_sigma & 0xFF) << 8 |
2682 (arg->stab_fnum & 0x1F);
2683 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_IIR0);
2684
2685 value = (arg->iir_pre_wet & 0x0F) << 24 |
2686 (arg->iir_tmax_sigma & 0x7FF) << 8 |
2687 (arg->iir_air_sigma & 0xFF);
2688 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_IIR1);
2689
2690 value = (arg->cfg_wt & 0x01FF) << 16 |
2691 (arg->cfg_air & 0xFF) << 8 |
2692 (arg->cfg_alpha & 0xFF);
2693 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_SOFT_CFG0);
2694
2695 value = ISP2X_PACK_2SHORT(arg->cfg_tmax, arg->cfg_gratio);
2696 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_SOFT_CFG1);
2697
2698 value = (arg->range_sima & 0x01FF) << 16 |
2699 (arg->space_sigma_pre & 0xFF) << 8 |
2700 (arg->space_sigma_cur & 0xFF);
2701 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_BF_SIGMA);
2702
2703 value = ISP2X_PACK_2SHORT(arg->bf_weight, arg->dc_weitcur);
2704 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_BF_WET);
2705
2706 for (i = 0; i < ISP21_DHAZ_ENH_CURVE_NUM / 2; i++) {
2707 value = ISP2X_PACK_2SHORT(arg->enh_curve[2 * i], arg->enh_curve[2 * i + 1]);
2708 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_ENH_CURVE0 + 4 * i);
2709 }
2710
2711 value = ISP2X_PACK_2SHORT(arg->enh_curve[2 * i], 0);
2712 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_ENH_CURVE0 + 4 * i);
2713
2714 value = ISP2X_PACK_4BYTE(arg->gaus_h0, arg->gaus_h1, arg->gaus_h2, 0);
2715 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_GAUS);
2716 }
2717
2718 static void
isp_dhaz_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2719 isp_dhaz_enable(struct rkisp_isp_params_vdev *params_vdev,
2720 bool en)
2721 {
2722 u32 value;
2723 bool real_en;
2724
2725 value = rkisp_ioread32(params_vdev, ISP21_DHAZ_CTRL);
2726 real_en = !!(value & ISP_DHAZ_ENMUX);
2727 if ((en && real_en) || (!en && !real_en))
2728 return;
2729
2730 if (en) {
2731 value |= ISP21_SELF_FORCE_UPD | ISP_DHAZ_ENMUX;
2732 rkisp_set_bits(params_vdev->dev, ISP_CTRL1,
2733 ISP2X_SYS_DHAZ_FST, ISP2X_SYS_DHAZ_FST, false);
2734 } else {
2735 value &= ~ISP_DHAZ_ENMUX;
2736 }
2737
2738 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_CTRL);
2739 }
2740
2741 static void
isp_3dlut_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_3dlut_cfg * arg)2742 isp_3dlut_config(struct rkisp_isp_params_vdev *params_vdev,
2743 const struct isp2x_3dlut_cfg *arg)
2744 {
2745 struct rkisp_isp_params_val_v21 *priv_val;
2746 u32 value, buf_idx, i;
2747 u32 *data;
2748
2749 priv_val = (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
2750 buf_idx = (priv_val->buf_3dlut_idx++) % RKISP_PARAM_3DLUT_BUF_NUM;
2751
2752 data = (u32 *)priv_val->buf_3dlut[buf_idx].vaddr;
2753 for (i = 0; i < arg->actual_size; i++)
2754 data[i] = (arg->lut_b[i] & 0x3FF) |
2755 (arg->lut_g[i] & 0xFFF) << 10 |
2756 (arg->lut_r[i] & 0x3FF) << 22;
2757 rkisp_prepare_buffer(params_vdev->dev, &priv_val->buf_3dlut[buf_idx]);
2758 value = priv_val->buf_3dlut[buf_idx].dma_addr;
2759 rkisp_iowrite32(params_vdev, value, MI_LUT_3D_RD_BASE);
2760 rkisp_iowrite32(params_vdev, arg->actual_size, MI_LUT_3D_RD_WSIZE);
2761
2762 value = rkisp_ioread32(params_vdev, ISP_3DLUT_CTRL);
2763 value &= ISP_3DLUT_EN;
2764
2765 if (value)
2766 isp_param_set_bits(params_vdev, ISP_3DLUT_UPDATE, 0x01);
2767
2768 if (arg->bypass_en)
2769 value |= ISP_3DLUT_BYPASS;
2770
2771 rkisp_iowrite32(params_vdev, value, ISP_3DLUT_CTRL);
2772 }
2773
2774 static void
isp_3dlut_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2775 isp_3dlut_enable(struct rkisp_isp_params_vdev *params_vdev,
2776 bool en)
2777 {
2778 u32 value;
2779 bool en_state;
2780
2781 value = rkisp_ioread32(params_vdev, ISP_3DLUT_CTRL);
2782 en_state = (value & ISP_3DLUT_EN) ? true : false;
2783
2784 if (en == en_state)
2785 return;
2786
2787 if (en) {
2788 isp_param_set_bits(params_vdev, ISP_3DLUT_CTRL, 0x01);
2789 isp_param_set_bits(params_vdev, ISP_3DLUT_UPDATE, 0x01);
2790 } else {
2791 isp_param_clear_bits(params_vdev, ISP_3DLUT_CTRL, 0x01);
2792 isp_param_clear_bits(params_vdev, ISP_3DLUT_UPDATE, 0x01);
2793 }
2794 }
2795
2796 static void
isp_ldch_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_ldch_cfg * arg)2797 isp_ldch_config(struct rkisp_isp_params_vdev *params_vdev,
2798 const struct isp2x_ldch_cfg *arg)
2799 {
2800 struct rkisp_device *dev = params_vdev->dev;
2801 struct rkisp_isp_params_val_v21 *priv_val;
2802 struct isp2x_ldch_head *ldch_head;
2803 int buf_idx, i;
2804 u32 value;
2805
2806 priv_val = (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
2807 for (i = 0; i < ISP2X_LDCH_BUF_NUM; i++) {
2808 if (arg->buf_fd == priv_val->buf_ldch[i].dma_fd)
2809 break;
2810 }
2811 if (i == ISP2X_LDCH_BUF_NUM) {
2812 dev_err(dev->dev, "cannot find ldch buf fd(%d)\n", arg->buf_fd);
2813 return;
2814 }
2815
2816 if (!priv_val->buf_ldch[i].vaddr) {
2817 dev_err(dev->dev, "no ldch buffer allocated\n");
2818 return;
2819 }
2820
2821 buf_idx = priv_val->buf_ldch_idx;
2822 ldch_head = (struct isp2x_ldch_head *)priv_val->buf_ldch[buf_idx].vaddr;
2823 ldch_head->stat = LDCH_BUF_INIT;
2824
2825 buf_idx = i;
2826 ldch_head = (struct isp2x_ldch_head *)priv_val->buf_ldch[buf_idx].vaddr;
2827 ldch_head->stat = LDCH_BUF_CHIPINUSE;
2828 priv_val->buf_ldch_idx = buf_idx;
2829 rkisp_prepare_buffer(dev, &priv_val->buf_ldch[buf_idx]);
2830 value = priv_val->buf_ldch[buf_idx].dma_addr + ldch_head->data_oft;
2831 rkisp_iowrite32(params_vdev, value, MI_LUT_LDCH_RD_BASE);
2832 rkisp_iowrite32(params_vdev, arg->hsize, MI_LUT_LDCH_RD_H_WSIZE);
2833 rkisp_iowrite32(params_vdev, arg->vsize, MI_LUT_LDCH_RD_V_SIZE);
2834 }
2835
2836 static void
isp_ldch_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2837 isp_ldch_enable(struct rkisp_isp_params_vdev *params_vdev,
2838 bool en)
2839 {
2840 struct rkisp_device *dev = params_vdev->dev;
2841 struct rkisp_isp_params_val_v21 *priv_val;
2842 u32 buf_idx;
2843
2844 priv_val = (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
2845 if (en) {
2846 buf_idx = priv_val->buf_ldch_idx;
2847 if (!priv_val->buf_ldch[buf_idx].vaddr) {
2848 dev_err(dev->dev, "no ldch buffer allocated\n");
2849 return;
2850 }
2851 isp_param_set_bits(params_vdev, ISP_LDCH_STS, 0x01);
2852 } else {
2853 isp_param_clear_bits(params_vdev, ISP_LDCH_STS, 0x01);
2854 }
2855 }
2856
2857 static void
isp_ynr_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_ynr_cfg * arg)2858 isp_ynr_config(struct rkisp_isp_params_vdev *params_vdev,
2859 const struct isp21_ynr_cfg *arg)
2860 {
2861 u32 i, value;
2862
2863 value = rkisp_ioread32(params_vdev, ISP21_YNR_GLOBAL_CTRL);
2864 value &= ISP21_YNR_EN;
2865
2866 value |= (arg->sw_ynr_thumb_mix_cur_en & 0x1) << 24 |
2867 (arg->sw_ynr_global_gain_alpha & 0xF) << 20 |
2868 (arg->sw_ynr_global_gain & 0x3FF) << 8 |
2869 (arg->sw_ynr_flt1x1_bypass_sel & 0x3) << 6 |
2870 (arg->sw_ynr_sft5x5_bypass & 0x1) << 5 |
2871 (arg->sw_ynr_flt1x1_bypass & 0x1) << 4 |
2872 (arg->sw_ynr_lgft3x3_bypass & 0x1) << 3 |
2873 (arg->sw_ynr_lbft5x5_bypass & 0x1) << 2 |
2874 (arg->sw_ynr_bft3x3_bypass & 0x1) << 1;
2875 rkisp_iowrite32(params_vdev, value, ISP21_YNR_GLOBAL_CTRL);
2876
2877 rkisp_iowrite32(params_vdev, arg->sw_ynr_rnr_max_r, ISP21_YNR_RNR_MAX_R);
2878
2879 value = ISP2X_PACK_2SHORT(arg->sw_ynr_low_bf_inv0, arg->sw_ynr_low_bf_inv1);
2880 rkisp_iowrite32(params_vdev, value, ISP21_YNR_LOWNR_CTRL0);
2881
2882 value = ISP2X_PACK_2SHORT(arg->sw_ynr_low_thred_adj, arg->sw_ynr_low_peak_supress);
2883 rkisp_iowrite32(params_vdev, value, ISP21_YNR_LOWNR_CTRL1);
2884
2885 value = ISP2X_PACK_2SHORT(arg->sw_ynr_low_edge_adj_thresh, arg->sw_ynr_low_dist_adj);
2886 rkisp_iowrite32(params_vdev, value, ISP21_YNR_LOWNR_CTRL2);
2887
2888 value = (arg->sw_ynr_low_bi_weight & 0xFF) << 24 |
2889 (arg->sw_ynr_low_weight & 0xFF) << 16 |
2890 (arg->sw_ynr_low_center_weight & 0xFFFF);
2891 rkisp_iowrite32(params_vdev, value, ISP21_YNR_LOWNR_CTRL3);
2892
2893 value = ISP2X_PACK_2SHORT(arg->sw_ynr_high_thred_adj, arg->sw_ynr_hi_min_adj);
2894 rkisp_iowrite32(params_vdev, value, ISP21_YNR_HIGHNR_CTRL0);
2895
2896 value = ISP2X_PACK_2SHORT(arg->sw_ynr_hi_edge_thed, arg->sw_ynr_high_retain_weight);
2897 rkisp_iowrite32(params_vdev, value, ISP21_YNR_HIGHNR_CTRL1);
2898
2899 value = ISP2X_PACK_4BYTE(arg->sw_ynr_base_filter_weight0,
2900 arg->sw_ynr_base_filter_weight1,
2901 arg->sw_ynr_base_filter_weight2,
2902 0);
2903 rkisp_iowrite32(params_vdev, value, ISP21_YNR_HIGHNR_BASE_FILTER_WEIGHT);
2904
2905 value = (arg->sw_ynr_low_gauss1_coeff2 & 0xFFFF) << 16 |
2906 (arg->sw_ynr_low_gauss1_coeff1 & 0xFF) << 8 |
2907 (arg->sw_ynr_low_gauss1_coeff0 & 0xFF);
2908 rkisp_iowrite32(params_vdev, value, ISP21_YNR_GAUSS1_COEFF);
2909
2910 value = (arg->sw_ynr_low_gauss2_coeff2 & 0xFFFF) << 16 |
2911 (arg->sw_ynr_low_gauss2_coeff1 & 0xFF) << 8 |
2912 (arg->sw_ynr_low_gauss2_coeff0 & 0xFF);
2913 rkisp_iowrite32(params_vdev, value, ISP21_YNR_GAUSS2_COEFF);
2914
2915 value = ISP2X_PACK_4BYTE(arg->sw_ynr_direction_weight0,
2916 arg->sw_ynr_direction_weight1,
2917 arg->sw_ynr_direction_weight2,
2918 arg->sw_ynr_direction_weight3);
2919 rkisp_iowrite32(params_vdev, value, ISP21_YNR_DIRECTION_W_0_3);
2920
2921 value = ISP2X_PACK_4BYTE(arg->sw_ynr_direction_weight4,
2922 arg->sw_ynr_direction_weight5,
2923 arg->sw_ynr_direction_weight6,
2924 arg->sw_ynr_direction_weight7);
2925 rkisp_iowrite32(params_vdev, value, ISP21_YNR_DIRECTION_W_4_7);
2926
2927 for (i = 0; i < ISP21_YNR_XY_NUM / 2; i++) {
2928 value = ISP2X_PACK_2SHORT(arg->sw_ynr_luma_points_x[2 * i],
2929 arg->sw_ynr_luma_points_x[2 * i + 1]);
2930 rkisp_iowrite32(params_vdev, value, ISP21_YNR_SGM_DX_0_1 + 4 * i);
2931 }
2932
2933 value = ISP2X_PACK_2SHORT(arg->sw_ynr_luma_points_x[2 * i], 0);
2934 rkisp_iowrite32(params_vdev, value, ISP21_YNR_SGM_DX_0_1 + 4 * i);
2935
2936 for (i = 0; i < ISP21_YNR_XY_NUM / 2; i++) {
2937 value = ISP2X_PACK_2SHORT(arg->sw_ynr_lsgm_y[2 * i],
2938 arg->sw_ynr_lsgm_y[2 * i + 1]);
2939 rkisp_iowrite32(params_vdev, value, ISP21_YNR_LSGM_Y_0_1 + 4 * i);
2940 }
2941
2942 value = ISP2X_PACK_2SHORT(arg->sw_ynr_lsgm_y[2 * i], 0);
2943 rkisp_iowrite32(params_vdev, value, ISP21_YNR_LSGM_Y_0_1 + 4 * i);
2944
2945 for (i = 0; i < ISP21_YNR_XY_NUM / 2; i++) {
2946 value = ISP2X_PACK_2SHORT(arg->sw_ynr_hsgm_y[2 * i],
2947 arg->sw_ynr_hsgm_y[2 * i + 1]);
2948 rkisp_iowrite32(params_vdev, value, ISP21_YNR_HSGM_Y_0_1 + 4 * i);
2949 }
2950
2951 value = ISP2X_PACK_2SHORT(arg->sw_ynr_hsgm_y[2 * i], 0);
2952 rkisp_iowrite32(params_vdev, value, ISP21_YNR_HSGM_Y_0_1 + 4 * i);
2953
2954 for (i = 0; i < ISP21_YNR_XY_NUM / 4; i++) {
2955 value = ISP2X_PACK_4BYTE(arg->sw_ynr_rnr_strength3[4 * i],
2956 arg->sw_ynr_rnr_strength3[4 * i + 1],
2957 arg->sw_ynr_rnr_strength3[4 * i + 2],
2958 arg->sw_ynr_rnr_strength3[4 * i + 3]);
2959 rkisp_iowrite32(params_vdev, value, ISP21_YNR_RNR_STRENGTH03 + 4 * i);
2960 }
2961
2962 value = ISP2X_PACK_4BYTE(arg->sw_ynr_rnr_strength3[4 * i], 0, 0, 0);
2963 rkisp_iowrite32(params_vdev, value, ISP21_YNR_RNR_STRENGTH03 + 4 * i);
2964 }
2965
2966 static void
isp_ynr_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,const struct isp21_ynr_cfg * arg)2967 isp_ynr_enable(struct rkisp_isp_params_vdev *params_vdev,
2968 bool en, const struct isp21_ynr_cfg *arg)
2969 {
2970 u32 ynr_ctrl, value = 0;
2971 bool real_en;
2972
2973 if (arg) {
2974 value = (arg->sw_ynr_thumb_mix_cur_en & 0x1) << 24 |
2975 (arg->sw_ynr_global_gain_alpha & 0xF) << 20 |
2976 (arg->sw_ynr_global_gain & 0x3FF) << 8 |
2977 (arg->sw_ynr_flt1x1_bypass_sel & 0x3) << 6 |
2978 (arg->sw_ynr_sft5x5_bypass & 0x1) << 5 |
2979 (arg->sw_ynr_flt1x1_bypass & 0x1) << 4 |
2980 (arg->sw_ynr_lgft3x3_bypass & 0x1) << 3 |
2981 (arg->sw_ynr_lbft5x5_bypass & 0x1) << 2 |
2982 (arg->sw_ynr_bft3x3_bypass & 0x1) << 1;
2983 }
2984
2985 ynr_ctrl = rkisp_ioread32(params_vdev, ISP21_YNR_GLOBAL_CTRL);
2986 real_en = !!(ynr_ctrl & ISP21_YNR_EN);
2987 if ((en && real_en) || (!en && !real_en))
2988 return;
2989
2990 if (en) {
2991 value |= ISP21_YNR_EN;
2992 rkisp_set_bits(params_vdev->dev, ISP_CTRL1,
2993 ISP2X_SYS_YNR_FST, ISP2X_SYS_YNR_FST, false);
2994 }
2995
2996 rkisp_iowrite32(params_vdev, value, ISP21_YNR_GLOBAL_CTRL);
2997 }
2998
2999 static void
isp_cnr_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_cnr_cfg * arg)3000 isp_cnr_config(struct rkisp_isp_params_vdev *params_vdev,
3001 const struct isp21_cnr_cfg *arg)
3002 {
3003 u32 value;
3004
3005 value = rkisp_ioread32(params_vdev, ISP21_CNR_CTRL);
3006 value &= ISP21_CNR_EN;
3007
3008 value |= (arg->sw_cnr_thumb_mix_cur_en & 0x1) << 4 |
3009 (arg->sw_cnr_lq_bila_bypass & 0x1) << 3 |
3010 (arg->sw_cnr_hq_bila_bypass & 0x1) << 2 |
3011 (arg->sw_cnr_exgain_bypass & 0x1) << 1;
3012 rkisp_iowrite32(params_vdev, value, ISP21_CNR_CTRL);
3013
3014 rkisp_iowrite32(params_vdev, arg->sw_cnr_exgain_mux, ISP21_CNR_EXGAIN);
3015
3016 value = ISP2X_PACK_4BYTE(arg->sw_cnr_gain_1sigma, arg->sw_cnr_gain_offset,
3017 arg->sw_cnr_gain_iso, 0);
3018 rkisp_iowrite32(params_vdev, value, ISP21_CNR_GAIN_PARA);
3019
3020 value = ISP2X_PACK_4BYTE(arg->sw_cnr_gain_uvgain0, arg->sw_cnr_gain_uvgain1, 0, 0);
3021 rkisp_iowrite32(params_vdev, value, ISP21_CNR_GAIN_UV_PARA);
3022
3023 rkisp_iowrite32(params_vdev, arg->sw_cnr_lmed3_alpha, ISP21_CNR_LMED3);
3024
3025 value = ISP2X_PACK_4BYTE(arg->sw_cnr_lbf5_gain_c, arg->sw_cnr_lbf5_gain_y, 0, 0);
3026 rkisp_iowrite32(params_vdev, value, ISP21_CNR_LBF5_GAIN);
3027
3028 value = ISP2X_PACK_4BYTE(arg->sw_cnr_lbf5_weit_d0, arg->sw_cnr_lbf5_weit_d1,
3029 arg->sw_cnr_lbf5_weit_d2, arg->sw_cnr_lbf5_weit_d3);
3030 rkisp_iowrite32(params_vdev, value, ISP21_CNR_LBF5_WEITD0_3);
3031
3032 rkisp_iowrite32(params_vdev, arg->sw_cnr_lbf5_weit_d4, ISP21_CNR_LBF5_WEITD4);
3033
3034 rkisp_iowrite32(params_vdev, arg->sw_cnr_hmed3_alpha, ISP21_CNR_HMED3);
3035
3036 value = (arg->sw_cnr_hbf5_weit_src & 0xFF) << 24 |
3037 (arg->sw_cnr_hbf5_min_wgt & 0xFF) << 16 |
3038 (arg->sw_cnr_hbf5_sigma & 0xFFFF);
3039 rkisp_iowrite32(params_vdev, value, ISP21_CNR_HBF5);
3040
3041 value = ISP2X_PACK_2SHORT(arg->sw_cnr_lbf3_sigma, arg->sw_cnr_lbf5_weit_src);
3042 rkisp_iowrite32(params_vdev, value, ISP21_CNR_LBF3);
3043 }
3044
3045 static void
isp_cnr_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,const struct isp21_cnr_cfg * arg)3046 isp_cnr_enable(struct rkisp_isp_params_vdev *params_vdev,
3047 bool en, const struct isp21_cnr_cfg *arg)
3048 {
3049 u32 cnr_ctrl, value = 0;
3050 bool real_en;
3051
3052 if (arg) {
3053 value = (arg->sw_cnr_thumb_mix_cur_en & 0x1) << 4 |
3054 (arg->sw_cnr_lq_bila_bypass & 0x1) << 3 |
3055 (arg->sw_cnr_hq_bila_bypass & 0x1) << 2 |
3056 (arg->sw_cnr_exgain_bypass & 0x1) << 1;
3057 }
3058
3059 cnr_ctrl = rkisp_ioread32(params_vdev, ISP21_CNR_CTRL);
3060 real_en = !!(cnr_ctrl & ISP21_CNR_EN);
3061 if ((en && real_en) || (!en && !real_en))
3062 return;
3063
3064 if (en) {
3065 value |= ISP21_CNR_EN;
3066 rkisp_set_bits(params_vdev->dev, ISP_CTRL1,
3067 ISP2X_SYS_CNR_FST, ISP2X_SYS_CNR_FST, false);
3068 }
3069
3070 rkisp_iowrite32(params_vdev, value, ISP21_CNR_CTRL);
3071 }
3072
3073 static void
isp_sharp_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_sharp_cfg * arg)3074 isp_sharp_config(struct rkisp_isp_params_vdev *params_vdev,
3075 const struct isp21_sharp_cfg *arg)
3076 {
3077 u32 value;
3078
3079 value = rkisp_ioread32(params_vdev, ISP21_SHARP_SHARP_EN);
3080 value &= ISP21_SHARP_EN;
3081
3082 value |= (arg->sw_sharp_bypass & 0x1) << 1;
3083 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_EN);
3084
3085 value = ISP2X_PACK_4BYTE(arg->sw_sharp_pbf_ratio, arg->sw_sharp_gaus_ratio,
3086 arg->sw_sharp_bf_ratio, arg->sw_sharp_sharp_ratio);
3087 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_RATIO);
3088
3089 value = (arg->sw_sharp_luma_dx[6] & 0x0F) << 24 |
3090 (arg->sw_sharp_luma_dx[5] & 0x0F) << 20 |
3091 (arg->sw_sharp_luma_dx[4] & 0x0F) << 16 |
3092 (arg->sw_sharp_luma_dx[3] & 0x0F) << 12 |
3093 (arg->sw_sharp_luma_dx[2] & 0x0F) << 8 |
3094 (arg->sw_sharp_luma_dx[1] & 0x0F) << 4 |
3095 (arg->sw_sharp_luma_dx[0] & 0x0F);
3096 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_LUMA_DX);
3097
3098 value = (arg->sw_sharp_pbf_sigma_inv[2] & 0x3FF) << 20 |
3099 (arg->sw_sharp_pbf_sigma_inv[1] & 0x3FF) << 10 |
3100 (arg->sw_sharp_pbf_sigma_inv[0] & 0x3FF);
3101 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_PBF_SIGMA_INV_0);
3102
3103 value = (arg->sw_sharp_pbf_sigma_inv[5] & 0x3FF) << 20 |
3104 (arg->sw_sharp_pbf_sigma_inv[4] & 0x3FF) << 10 |
3105 (arg->sw_sharp_pbf_sigma_inv[3] & 0x3FF);
3106 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_PBF_SIGMA_INV_1);
3107
3108 value = (arg->sw_sharp_pbf_sigma_inv[7] & 0x3FF) << 10 |
3109 (arg->sw_sharp_pbf_sigma_inv[6] & 0x3FF);
3110 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_PBF_SIGMA_INV_2);
3111
3112 value = (arg->sw_sharp_bf_sigma_inv[2] & 0x3FF) << 20 |
3113 (arg->sw_sharp_bf_sigma_inv[1] & 0x3FF) << 10 |
3114 (arg->sw_sharp_bf_sigma_inv[0] & 0x3FF);
3115 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_BF_SIGMA_INV_0);
3116
3117 value = (arg->sw_sharp_bf_sigma_inv[5] & 0x3FF) << 20 |
3118 (arg->sw_sharp_bf_sigma_inv[4] & 0x3FF) << 10 |
3119 (arg->sw_sharp_bf_sigma_inv[3] & 0x3FF);
3120 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_BF_SIGMA_INV_1);
3121
3122 value = (arg->sw_sharp_bf_sigma_inv[7] & 0x3FF) << 10 |
3123 (arg->sw_sharp_bf_sigma_inv[6] & 0x3FF);
3124 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_BF_SIGMA_INV_2);
3125
3126 value = (arg->sw_sharp_bf_sigma_shift & 0x0F) << 4 |
3127 (arg->sw_sharp_pbf_sigma_shift & 0x0F);
3128 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_SIGMA_SHIFT);
3129
3130 value = (arg->sw_sharp_ehf_th[2] & 0x3FF) << 20 |
3131 (arg->sw_sharp_ehf_th[1] & 0x3FF) << 10 |
3132 (arg->sw_sharp_ehf_th[0] & 0x3FF);
3133 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_EHF_TH_0);
3134
3135 value = (arg->sw_sharp_ehf_th[5] & 0x3FF) << 20 |
3136 (arg->sw_sharp_ehf_th[4] & 0x3FF) << 10 |
3137 (arg->sw_sharp_ehf_th[3] & 0x3FF);
3138 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_EHF_TH_1);
3139
3140 value = (arg->sw_sharp_ehf_th[7] & 0x3FF) << 10 |
3141 (arg->sw_sharp_ehf_th[6] & 0x3FF);
3142 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_EHF_TH_2);
3143
3144 value = (arg->sw_sharp_clip_hf[2] & 0x3FF) << 20 |
3145 (arg->sw_sharp_clip_hf[1] & 0x3FF) << 10 |
3146 (arg->sw_sharp_clip_hf[0] & 0x3FF);
3147 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_CLIP_HF_0);
3148
3149 value = (arg->sw_sharp_clip_hf[5] & 0x3FF) << 20 |
3150 (arg->sw_sharp_clip_hf[4] & 0x3FF) << 10 |
3151 (arg->sw_sharp_clip_hf[3] & 0x3FF);
3152 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_CLIP_HF_1);
3153
3154 value = (arg->sw_sharp_clip_hf[7] & 0x3FF) << 10 |
3155 (arg->sw_sharp_clip_hf[6] & 0x3FF);
3156 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_CLIP_HF_2);
3157
3158 value = ISP2X_PACK_4BYTE(arg->sw_sharp_pbf_coef_0, arg->sw_sharp_pbf_coef_1,
3159 arg->sw_sharp_pbf_coef_2, 0);
3160 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_PBF_COEF);
3161
3162 value = ISP2X_PACK_4BYTE(arg->sw_sharp_bf_coef_0, arg->sw_sharp_bf_coef_1,
3163 arg->sw_sharp_bf_coef_2, 0);
3164 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_BF_COEF);
3165
3166 value = ISP2X_PACK_4BYTE(arg->sw_sharp_gaus_coef_0, arg->sw_sharp_gaus_coef_1,
3167 arg->sw_sharp_gaus_coef_2, 0);
3168 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_GAUS_COEF);
3169 }
3170
3171 static void
isp_sharp_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)3172 isp_sharp_enable(struct rkisp_isp_params_vdev *params_vdev,
3173 bool en)
3174 {
3175 u32 value;
3176
3177 value = rkisp_ioread32(params_vdev, ISP21_SHARP_SHARP_EN);
3178 value &= ~ISP21_SHARP_EN;
3179
3180 if (en)
3181 value |= ISP21_SHARP_EN;
3182
3183 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_EN);
3184 }
3185
3186 static void
isp_baynr_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_baynr_cfg * arg)3187 isp_baynr_config(struct rkisp_isp_params_vdev *params_vdev,
3188 const struct isp21_baynr_cfg *arg)
3189 {
3190 u32 i, value;
3191
3192 value = rkisp_ioread32(params_vdev, ISP21_BAYNR_CTRL);
3193 value &= ISP21_BAYNR_EN;
3194
3195 value |= (arg->sw_baynr_gauss_en & 0x1) << 8 |
3196 (arg->sw_baynr_log_bypass & 0x1) << 4;
3197 rkisp_iowrite32(params_vdev, value, ISP21_BAYNR_CTRL);
3198
3199 value = ISP2X_PACK_2SHORT(arg->sw_baynr_dgain0, arg->sw_baynr_dgain1);
3200 rkisp_iowrite32(params_vdev, value, ISP21_BAYNR_DGAIN0);
3201
3202 rkisp_iowrite32(params_vdev, arg->sw_baynr_dgain2, ISP21_BAYNR_DGAIN1);
3203 rkisp_iowrite32(params_vdev, arg->sw_baynr_pix_diff, ISP21_BAYNR_PIXDIFF);
3204
3205 value = ISP2X_PACK_2SHORT(arg->sw_baynr_softthld, arg->sw_baynr_diff_thld);
3206 rkisp_iowrite32(params_vdev, value, ISP21_BAYNR_THLD);
3207
3208 value = ISP2X_PACK_2SHORT(arg->sw_baynr_reg_w1, arg->sw_bltflt_streng);
3209 rkisp_iowrite32(params_vdev, value, ISP21_BAYNR_W1_STRENG);
3210
3211 for (i = 0; i < ISP21_BAYNR_XY_NUM / 2; i++) {
3212 value = ISP2X_PACK_2SHORT(arg->sw_sigma_x[2 * i], arg->sw_sigma_x[2 * i + 1]);
3213 rkisp_iowrite32(params_vdev, value, ISP21_BAYNR_SIGMAX01 + 4 * i);
3214 }
3215
3216 for (i = 0; i < ISP21_BAYNR_XY_NUM / 2; i++) {
3217 value = ISP2X_PACK_2SHORT(arg->sw_sigma_y[2 * i], arg->sw_sigma_y[2 * i + 1]);
3218 rkisp_iowrite32(params_vdev, value, ISP21_BAYNR_SIGMAY01 + 4 * i);
3219 }
3220
3221 value = (arg->weit_d2 & 0x3FF) << 20 |
3222 (arg->weit_d1 & 0x3FF) << 10 |
3223 (arg->weit_d0 & 0x3FF);
3224 rkisp_iowrite32(params_vdev, value, ISP21_BAYNR_WRIT_D);
3225 }
3226
3227 static void
isp_baynr_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)3228 isp_baynr_enable(struct rkisp_isp_params_vdev *params_vdev,
3229 bool en)
3230 {
3231 u32 value;
3232
3233 value = rkisp_ioread32(params_vdev, ISP21_BAYNR_CTRL);
3234 value &= ~ISP21_BAYNR_EN;
3235
3236 if (en)
3237 value |= ISP21_BAYNR_EN;
3238
3239 rkisp_iowrite32(params_vdev, value, ISP21_BAYNR_CTRL);
3240 }
3241
3242 static void
isp_bay3d_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_bay3d_cfg * arg)3243 isp_bay3d_config(struct rkisp_isp_params_vdev *params_vdev,
3244 const struct isp21_bay3d_cfg *arg)
3245 {
3246 u32 i, value;
3247
3248 value = rkisp_ioread32(params_vdev, ISP21_BAY3D_CTRL);
3249 value &= ISP21_BAY3D_EN;
3250
3251 value |= (arg->sw_bay3d_exp_sel & 0x1) << 16 |
3252 (arg->sw_bay3d_bypass_en & 0x1) << 12 |
3253 (arg->sw_bay3d_pk_en & 0x1) << 4;
3254 rkisp_iowrite32(params_vdev, value, ISP21_BAY3D_CTRL);
3255
3256 value = ISP2X_PACK_2SHORT(arg->sw_bay3d_sigratio, arg->sw_bay3d_softwgt);
3257 rkisp_iowrite32(params_vdev, value, ISP21_BAY3D_KALRATIO);
3258
3259 rkisp_iowrite32(params_vdev, arg->sw_bay3d_glbpk2, ISP21_BAY3D_GLBPK2);
3260
3261 value = ISP2X_PACK_2SHORT(arg->sw_bay3d_str, arg->sw_bay3d_exp_str);
3262 rkisp_iowrite32(params_vdev, value, ISP21_BAY3D_KALSTR);
3263
3264 value = ISP2X_PACK_2SHORT(arg->sw_bay3d_wgtlmt_l, arg->sw_bay3d_wgtlmt_h);
3265 rkisp_iowrite32(params_vdev, value, ISP21_BAY3D_WGTLMT);
3266
3267 for (i = 0; i < ISP21_BAY3D_XY_NUM / 2; i++) {
3268 value = ISP2X_PACK_2SHORT(arg->sw_bay3d_sig_x[2 * i],
3269 arg->sw_bay3d_sig_x[2 * i + 1]);
3270 rkisp_iowrite32(params_vdev, value, ISP21_BAY3D_SIG_X0 + 4 * i);
3271 }
3272
3273 for (i = 0; i < ISP21_BAY3D_XY_NUM / 2; i++) {
3274 value = ISP2X_PACK_2SHORT(arg->sw_bay3d_sig_y[2 * i],
3275 arg->sw_bay3d_sig_y[2 * i + 1]);
3276 rkisp_iowrite32(params_vdev, value, ISP21_BAY3D_SIG_Y0 + 4 * i);
3277 }
3278 }
3279
3280 static void
isp_bay3d_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)3281 isp_bay3d_enable(struct rkisp_isp_params_vdev *params_vdev,
3282 bool en)
3283 {
3284 struct rkisp_device *ispdev = params_vdev->dev;
3285 struct rkisp_isp_params_val_v21 *priv_val;
3286 u32 value, bay3d_ctrl;
3287
3288 priv_val = (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
3289 bay3d_ctrl = rkisp_ioread32(params_vdev, ISP21_BAY3D_CTRL);
3290 if ((en && (bay3d_ctrl & ISP21_BAY3D_EN)) ||
3291 (!en && !(bay3d_ctrl & ISP21_BAY3D_EN)))
3292 return;
3293
3294 if (en) {
3295 if (!priv_val->buf_3dnr.size) {
3296 dev_err(ispdev->dev, "no bay3d buffer available\n");
3297 return;
3298 }
3299
3300 value = priv_val->buf_3dnr.size;
3301 rkisp_iowrite32(params_vdev, value, ISP21_MI_BAY3D_WR_SIZE);
3302 value = priv_val->buf_3dnr.dma_addr;
3303 rkisp_iowrite32(params_vdev, value, ISP21_MI_BAY3D_WR_BASE);
3304 rkisp_iowrite32(params_vdev, value, ISP21_MI_BAY3D_RD_BASE);
3305
3306 rkisp_set_bits(params_vdev->dev, MI_RD_CTRL2,
3307 BAY3D_RW_ONEADDR_EN, BAY3D_RW_ONEADDR_EN, false);
3308 rkisp_set_bits(params_vdev->dev, MI_WR_CTRL2,
3309 SW_BAY3D_WR_AUTOUPD | SW_BAY3D_FORCEUPD,
3310 SW_BAY3D_WR_AUTOUPD | SW_BAY3D_FORCEUPD, false);
3311
3312 rkisp_set_bits(params_vdev->dev, ISP_CTRL1,
3313 ISP2X_SYS_BAY3D_FST, ISP2X_SYS_BAY3D_FST, false);
3314
3315 bay3d_ctrl |= ISP21_BAY3D_EN;
3316 } else {
3317 bay3d_ctrl &= ~ISP21_BAY3D_EN;
3318 }
3319
3320 rkisp_iowrite32(params_vdev, bay3d_ctrl, ISP21_BAY3D_CTRL);
3321 }
3322
3323 static void
isp_csm_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_csm_cfg * arg)3324 isp_csm_config(struct rkisp_isp_params_vdev *params_vdev,
3325 const struct isp21_csm_cfg *arg)
3326 {
3327 u32 i, val;
3328
3329 for (i = 0; i < ISP21_CSM_COEFF_NUM; i++) {
3330 if (i == 0)
3331 val = (arg->csm_y_offset & 0x3f) << 24 |
3332 (arg->csm_c_offset & 0xff) << 16 |
3333 (arg->csm_coeff[i] & 0x1ff);
3334 else
3335 val = arg->csm_coeff[i] & 0x1ff;
3336 rkisp_iowrite32(params_vdev, val, ISP_CC_COEFF_0 + i * 4);
3337 }
3338
3339 val = CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA | CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA;
3340 isp_param_set_bits(params_vdev, ISP_CTRL, val);
3341 }
3342
3343 static void
isp_cgc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_cgc_cfg * arg)3344 isp_cgc_config(struct rkisp_isp_params_vdev *params_vdev,
3345 const struct isp21_cgc_cfg *arg)
3346 {
3347 u32 val = rkisp_ioread32(params_vdev, ISP_CTRL);
3348 u32 eff_ctrl, cproc_ctrl;
3349
3350 params_vdev->quantization = V4L2_QUANTIZATION_FULL_RANGE;
3351 val &= ~(ISP21_CGC_YUV_LIMIT | ISP21_CGC_RATIO_EN);
3352 if (arg->yuv_limit) {
3353 val |= ISP21_CGC_YUV_LIMIT;
3354 params_vdev->quantization = V4L2_QUANTIZATION_LIM_RANGE;
3355 }
3356 if (arg->ratio_en)
3357 val |= ISP21_CGC_RATIO_EN;
3358 rkisp_iowrite32(params_vdev, val, ISP_CTRL);
3359
3360 cproc_ctrl = rkisp_ioread32(params_vdev, CPROC_CTRL);
3361 if (cproc_ctrl & CIF_C_PROC_CTR_ENABLE) {
3362 val = CIF_C_PROC_YOUT_FULL | CIF_C_PROC_YIN_FULL | CIF_C_PROC_COUT_FULL;
3363 if (arg->yuv_limit)
3364 cproc_ctrl &= ~val;
3365 else
3366 cproc_ctrl |= val;
3367 rkisp_iowrite32(params_vdev, cproc_ctrl, CPROC_CTRL);
3368 }
3369
3370 eff_ctrl = rkisp_ioread32(params_vdev, CIF_IMG_EFF_CTRL);
3371 if (eff_ctrl & CIF_IMG_EFF_CTRL_ENABLE) {
3372 if (arg->yuv_limit)
3373 eff_ctrl &= ~CIF_IMG_EFF_CTRL_YCBCR_FULL;
3374 else
3375 eff_ctrl |= CIF_IMG_EFF_CTRL_YCBCR_FULL;
3376 rkisp_iowrite32(params_vdev, eff_ctrl, CIF_IMG_EFF_CTRL);
3377 }
3378 }
3379
3380 struct rkisp_isp_params_v21_ops rkisp_v21_isp_params_ops = {
3381 .dpcc_config = isp_dpcc_config,
3382 .dpcc_enable = isp_dpcc_enable,
3383 .bls_config = isp_bls_config,
3384 .bls_enable = isp_bls_enable,
3385 .sdg_config = isp_sdg_config,
3386 .sdg_enable = isp_sdg_enable,
3387 .lsc_config = isp_lsc_config,
3388 .lsc_enable = isp_lsc_enable,
3389 .awbgain_config = isp_awbgain_config,
3390 .awbgain_enable = isp_awbgain_enable,
3391 .debayer_config = isp_debayer_config,
3392 .debayer_enable = isp_debayer_enable,
3393 .ccm_config = isp_ccm_config,
3394 .ccm_enable = isp_ccm_enable,
3395 .goc_config = isp_goc_config,
3396 .goc_enable = isp_goc_enable,
3397 .cproc_config = isp_cproc_config,
3398 .cproc_enable = isp_cproc_enable,
3399 .ie_config = isp_ie_config,
3400 .ie_enable = isp_ie_enable,
3401 .rawaf_config = isp_rawaf_config,
3402 .rawaf_enable = isp_rawaf_enable,
3403 .rawae0_config = isp_rawaelite_config,
3404 .rawae0_enable = isp_rawaelite_enable,
3405 .rawae1_config = isp_rawae1_config,
3406 .rawae1_enable = isp_rawae1_enable,
3407 .rawae2_config = isp_rawae2_config,
3408 .rawae2_enable = isp_rawae2_enable,
3409 .rawae3_config = isp_rawae3_config,
3410 .rawae3_enable = isp_rawae3_enable,
3411 .rawawb_config = isp_rawawb_config,
3412 .rawawb_enable = isp_rawawb_enable,
3413 .rawhst0_config = isp_rawhstlite_config,
3414 .rawhst0_enable = isp_rawhstlite_enable,
3415 .rawhst1_config = isp_rawhst1_config,
3416 .rawhst1_enable = isp_rawhst1_enable,
3417 .rawhst2_config = isp_rawhst2_config,
3418 .rawhst2_enable = isp_rawhst2_enable,
3419 .rawhst3_config = isp_rawhst3_config,
3420 .rawhst3_enable = isp_rawhst3_enable,
3421 .hdrmge_config = isp_hdrmge_config,
3422 .hdrmge_enable = isp_hdrmge_enable,
3423 .hdrdrc_config = isp_hdrdrc_config,
3424 .hdrdrc_enable = isp_hdrdrc_enable,
3425 .gic_config = isp_gic_config,
3426 .gic_enable = isp_gic_enable,
3427 .dhaz_config = isp_dhaz_config,
3428 .dhaz_enable = isp_dhaz_enable,
3429 .isp3dlut_config = isp_3dlut_config,
3430 .isp3dlut_enable = isp_3dlut_enable,
3431 .ldch_config = isp_ldch_config,
3432 .ldch_enable = isp_ldch_enable,
3433 .ynr_config = isp_ynr_config,
3434 .ynr_enable = isp_ynr_enable,
3435 .cnr_config = isp_cnr_config,
3436 .cnr_enable = isp_cnr_enable,
3437 .sharp_config = isp_sharp_config,
3438 .sharp_enable = isp_sharp_enable,
3439 .baynr_config = isp_baynr_config,
3440 .baynr_enable = isp_baynr_enable,
3441 .bay3d_config = isp_bay3d_config,
3442 .bay3d_enable = isp_bay3d_enable,
3443 .csm_config = isp_csm_config,
3444 .cgc_config = isp_cgc_config,
3445 };
3446
3447 static __maybe_unused
__isp_isr_other_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_isp_params_cfg * new_params,enum rkisp_params_type type)3448 void __isp_isr_other_config(struct rkisp_isp_params_vdev *params_vdev,
3449 const struct isp21_isp_params_cfg *new_params,
3450 enum rkisp_params_type type)
3451 {
3452 struct rkisp_isp_params_v21_ops *ops =
3453 (struct rkisp_isp_params_v21_ops *)params_vdev->priv_ops;
3454 u64 module_cfg_update = new_params->module_cfg_update;
3455
3456 if (type == RKISP_PARAMS_SHD) {
3457 if ((module_cfg_update & ISP2X_MODULE_HDRMGE))
3458 ops->hdrmge_config(params_vdev, &new_params->others.hdrmge_cfg, type);
3459
3460 if ((module_cfg_update & ISP2X_MODULE_DRC))
3461 ops->hdrdrc_config(params_vdev, &new_params->others.drc_cfg, type);
3462 return;
3463 }
3464
3465 if ((module_cfg_update & ISP2X_MODULE_DPCC))
3466 ops->dpcc_config(params_vdev, &new_params->others.dpcc_cfg);
3467
3468 if ((module_cfg_update & ISP2X_MODULE_BLS))
3469 ops->bls_config(params_vdev, &new_params->others.bls_cfg);
3470
3471 if ((module_cfg_update & ISP2X_MODULE_SDG))
3472 ops->sdg_config(params_vdev, &new_params->others.sdg_cfg);
3473
3474 if ((module_cfg_update & ISP2X_MODULE_LSC))
3475 ops->lsc_config(params_vdev, &new_params->others.lsc_cfg);
3476
3477 if ((module_cfg_update & ISP2X_MODULE_AWB_GAIN))
3478 ops->awbgain_config(params_vdev, &new_params->others.awb_gain_cfg);
3479
3480 if ((module_cfg_update & ISP2X_MODULE_DEBAYER))
3481 ops->debayer_config(params_vdev, &new_params->others.debayer_cfg);
3482
3483 if ((module_cfg_update & ISP2X_MODULE_CCM))
3484 ops->ccm_config(params_vdev, &new_params->others.ccm_cfg);
3485
3486 if ((module_cfg_update & ISP2X_MODULE_GOC))
3487 ops->goc_config(params_vdev, &new_params->others.gammaout_cfg);
3488
3489 /* range csm->cgc->cproc->ie */
3490 if ((module_cfg_update & ISP2X_MODULE_CSM))
3491 ops->csm_config(params_vdev, &new_params->others.csm_cfg);
3492
3493 if ((module_cfg_update & ISP2X_MODULE_CGC))
3494 ops->cgc_config(params_vdev, &new_params->others.cgc_cfg);
3495
3496 if ((module_cfg_update & ISP2X_MODULE_CPROC))
3497 ops->cproc_config(params_vdev, &new_params->others.cproc_cfg);
3498
3499 if ((module_cfg_update & ISP2X_MODULE_IE))
3500 ops->ie_config(params_vdev, &new_params->others.ie_cfg);
3501
3502 if ((module_cfg_update & ISP2X_MODULE_HDRMGE))
3503 ops->hdrmge_config(params_vdev, &new_params->others.hdrmge_cfg, type);
3504
3505 if ((module_cfg_update & ISP2X_MODULE_DRC))
3506 ops->hdrdrc_config(params_vdev, &new_params->others.drc_cfg, type);
3507
3508 if ((module_cfg_update & ISP2X_MODULE_GIC))
3509 ops->gic_config(params_vdev, &new_params->others.gic_cfg);
3510
3511 if ((module_cfg_update & ISP2X_MODULE_DHAZ))
3512 ops->dhaz_config(params_vdev, &new_params->others.dhaz_cfg);
3513
3514 if ((module_cfg_update & ISP2X_MODULE_3DLUT))
3515 ops->isp3dlut_config(params_vdev, &new_params->others.isp3dlut_cfg);
3516
3517 if ((module_cfg_update & ISP2X_MODULE_LDCH))
3518 ops->ldch_config(params_vdev, &new_params->others.ldch_cfg);
3519
3520 if ((module_cfg_update & ISP2X_MODULE_YNR))
3521 ops->ynr_config(params_vdev, &new_params->others.ynr_cfg);
3522
3523 if ((module_cfg_update & ISP2X_MODULE_CNR))
3524 ops->cnr_config(params_vdev, &new_params->others.cnr_cfg);
3525
3526 if ((module_cfg_update & ISP2X_MODULE_SHARP))
3527 ops->sharp_config(params_vdev, &new_params->others.sharp_cfg);
3528
3529 if ((module_cfg_update & ISP2X_MODULE_BAYNR))
3530 ops->baynr_config(params_vdev, &new_params->others.baynr_cfg);
3531
3532 if ((module_cfg_update & ISP2X_MODULE_BAY3D))
3533 ops->bay3d_config(params_vdev, &new_params->others.bay3d_cfg);
3534 }
3535
3536 static __maybe_unused
__isp_isr_other_en(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_isp_params_cfg * new_params,enum rkisp_params_type type)3537 void __isp_isr_other_en(struct rkisp_isp_params_vdev *params_vdev,
3538 const struct isp21_isp_params_cfg *new_params,
3539 enum rkisp_params_type type)
3540 {
3541 struct rkisp_isp_params_v21_ops *ops =
3542 (struct rkisp_isp_params_v21_ops *)params_vdev->priv_ops;
3543 struct rkisp_isp_params_val_v21 *priv_val =
3544 (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
3545 struct rkisp_device *ispdev = params_vdev->dev;
3546 bool is_feature_on = ispdev->hw_dev->is_feature_on;
3547 u64 iq_feature = ispdev->hw_dev->iq_feature;
3548 u64 module_en_update = new_params->module_en_update;
3549 u64 module_ens = new_params->module_ens;
3550
3551 if (type == RKISP_PARAMS_SHD)
3552 return;
3553
3554 if (is_feature_on) {
3555 module_en_update &= ~ISP2X_MODULE_HDRMGE;
3556 if (module_en_update & ~iq_feature) {
3557 dev_err(ispdev->dev,
3558 "some iq features(0x%llx, 0x%llx) are not supported\n",
3559 module_en_update, iq_feature);
3560 module_en_update &= iq_feature;
3561 }
3562 }
3563
3564 if (module_en_update & ISP2X_MODULE_HDRMGE) {
3565 ops->hdrmge_enable(params_vdev, !!(module_ens & ISP2X_MODULE_HDRMGE));
3566 priv_val->mge_en = !!(module_ens & ISP2X_MODULE_HDRMGE);
3567 }
3568
3569 if (module_en_update & ISP2X_MODULE_DRC)
3570 ops->hdrdrc_enable(params_vdev, !!(module_ens & ISP2X_MODULE_DRC));
3571
3572 if (module_en_update & ISP2X_MODULE_DPCC)
3573 ops->dpcc_enable(params_vdev, !!(module_ens & ISP2X_MODULE_DPCC));
3574
3575 if (module_en_update & ISP2X_MODULE_BLS)
3576 ops->bls_enable(params_vdev, !!(module_ens & ISP2X_MODULE_BLS));
3577
3578 if (module_en_update & ISP2X_MODULE_SDG)
3579 ops->sdg_enable(params_vdev, !!(module_ens & ISP2X_MODULE_SDG));
3580
3581 if (module_en_update & ISP2X_MODULE_LSC) {
3582 ops->lsc_enable(params_vdev, !!(module_ens & ISP2X_MODULE_LSC));
3583 priv_val->lsc_en = !!(module_ens & ISP2X_MODULE_LSC);
3584 }
3585
3586 if (module_en_update & ISP2X_MODULE_AWB_GAIN)
3587 ops->awbgain_enable(params_vdev, !!(module_ens & ISP2X_MODULE_AWB_GAIN));
3588
3589 if (module_en_update & ISP2X_MODULE_DEBAYER)
3590 ops->debayer_enable(params_vdev, !!(module_ens & ISP2X_MODULE_DEBAYER));
3591
3592 if (module_en_update & ISP2X_MODULE_CCM)
3593 ops->ccm_enable(params_vdev, !!(module_ens & ISP2X_MODULE_CCM));
3594
3595 if (module_en_update & ISP2X_MODULE_GOC)
3596 ops->goc_enable(params_vdev, !!(module_ens & ISP2X_MODULE_GOC));
3597
3598 if (module_en_update & ISP2X_MODULE_CPROC)
3599 ops->cproc_enable(params_vdev, !!(module_ens & ISP2X_MODULE_CPROC));
3600
3601 if (module_en_update & ISP2X_MODULE_IE)
3602 ops->ie_enable(params_vdev, !!(module_ens & ISP2X_MODULE_IE));
3603
3604 if (module_en_update & ISP2X_MODULE_HDRMGE) {
3605 ops->hdrmge_enable(params_vdev, !!(module_ens & ISP2X_MODULE_HDRMGE));
3606 priv_val->mge_en = !!(module_ens & ISP2X_MODULE_HDRMGE);
3607 }
3608
3609 if (module_en_update & ISP2X_MODULE_DRC)
3610 ops->hdrdrc_enable(params_vdev, !!(module_ens & ISP2X_MODULE_DRC));
3611
3612 if (module_en_update & ISP2X_MODULE_GIC)
3613 ops->gic_enable(params_vdev, !!(module_ens & ISP2X_MODULE_GIC));
3614
3615 if (module_en_update & ISP2X_MODULE_DHAZ) {
3616 ops->dhaz_enable(params_vdev, !!(module_ens & ISP2X_MODULE_DHAZ));
3617 priv_val->dhaz_en = !!(module_ens & ISP2X_MODULE_DHAZ);
3618 }
3619
3620 if (module_en_update & ISP2X_MODULE_3DLUT)
3621 ops->isp3dlut_enable(params_vdev, !!(module_ens & ISP2X_MODULE_3DLUT));
3622
3623 if (module_en_update & ISP2X_MODULE_LDCH)
3624 ops->ldch_enable(params_vdev, !!(module_ens & ISP2X_MODULE_LDCH));
3625
3626 if (module_en_update & ISP2X_MODULE_YNR)
3627 ops->ynr_enable(params_vdev, !!(module_ens & ISP2X_MODULE_YNR), &new_params->others.ynr_cfg);
3628
3629 if (module_en_update & ISP2X_MODULE_CNR)
3630 ops->cnr_enable(params_vdev, !!(module_ens & ISP2X_MODULE_CNR), &new_params->others.cnr_cfg);
3631
3632 if (module_en_update & ISP2X_MODULE_SHARP)
3633 ops->sharp_enable(params_vdev, !!(module_ens & ISP2X_MODULE_SHARP));
3634
3635 if (module_en_update & ISP2X_MODULE_BAYNR)
3636 ops->baynr_enable(params_vdev, !!(module_ens & ISP2X_MODULE_BAYNR));
3637
3638 if (module_en_update & ISP2X_MODULE_BAY3D)
3639 ops->bay3d_enable(params_vdev, !!(module_ens & ISP2X_MODULE_BAY3D));
3640 }
3641
3642 static __maybe_unused
__isp_isr_meas_config(struct rkisp_isp_params_vdev * params_vdev,struct isp21_isp_params_cfg * new_params,enum rkisp_params_type type)3643 void __isp_isr_meas_config(struct rkisp_isp_params_vdev *params_vdev,
3644 struct isp21_isp_params_cfg *new_params,
3645 enum rkisp_params_type type)
3646 {
3647 struct rkisp_isp_params_v21_ops *ops =
3648 (struct rkisp_isp_params_v21_ops *)params_vdev->priv_ops;
3649 u64 module_cfg_update = new_params->module_cfg_update;
3650
3651 params_vdev->cur_frame_id = new_params->frame_id;
3652 if (type == RKISP_PARAMS_SHD)
3653 return;
3654
3655 if ((module_cfg_update & ISP2X_MODULE_RAWAE0))
3656 ops->rawae0_config(params_vdev, &new_params->meas.rawae0);
3657
3658 if ((module_cfg_update & ISP2X_MODULE_RAWAE1))
3659 ops->rawae1_config(params_vdev, &new_params->meas.rawae1);
3660
3661 if ((module_cfg_update & ISP2X_MODULE_RAWAE2))
3662 ops->rawae2_config(params_vdev, &new_params->meas.rawae2);
3663
3664 if ((module_cfg_update & ISP2X_MODULE_RAWAE3))
3665 ops->rawae3_config(params_vdev, &new_params->meas.rawae3);
3666
3667 if ((module_cfg_update & ISP2X_MODULE_RAWHIST0))
3668 ops->rawhst0_config(params_vdev, &new_params->meas.rawhist0);
3669
3670 if ((module_cfg_update & ISP2X_MODULE_RAWHIST1))
3671 ops->rawhst1_config(params_vdev, &new_params->meas.rawhist1);
3672
3673 if ((module_cfg_update & ISP2X_MODULE_RAWHIST2))
3674 ops->rawhst2_config(params_vdev, &new_params->meas.rawhist2);
3675
3676 if ((module_cfg_update & ISP2X_MODULE_RAWHIST3))
3677 ops->rawhst3_config(params_vdev, &new_params->meas.rawhist3);
3678
3679 if ((module_cfg_update & ISP2X_MODULE_RAWAWB))
3680 ops->rawawb_config(params_vdev, &new_params->meas.rawawb);
3681
3682 if ((module_cfg_update & ISP2X_MODULE_RAWAF))
3683 ops->rawaf_config(params_vdev, &new_params->meas.rawaf);
3684 }
3685
3686 static __maybe_unused
__isp_isr_meas_en(struct rkisp_isp_params_vdev * params_vdev,struct isp21_isp_params_cfg * new_params,enum rkisp_params_type type)3687 void __isp_isr_meas_en(struct rkisp_isp_params_vdev *params_vdev,
3688 struct isp21_isp_params_cfg *new_params,
3689 enum rkisp_params_type type)
3690 {
3691 struct rkisp_isp_params_v21_ops *ops =
3692 (struct rkisp_isp_params_v21_ops *)params_vdev->priv_ops;
3693 struct rkisp_device *ispdev = params_vdev->dev;
3694 bool is_feature_on = ispdev->hw_dev->is_feature_on;
3695 u64 iq_feature = ispdev->hw_dev->iq_feature;
3696 u64 module_en_update = new_params->module_en_update;
3697 u64 module_ens = new_params->module_ens;
3698
3699 if (type == RKISP_PARAMS_SHD)
3700 return;
3701
3702 if (is_feature_on) {
3703 module_en_update &= ~ISP2X_MODULE_HDRMGE;
3704 if (module_en_update & ~iq_feature) {
3705 dev_err(ispdev->dev,
3706 "some iq features(0x%llx, 0x%llx) are not supported\n",
3707 module_en_update, iq_feature);
3708 module_en_update &= iq_feature;
3709 }
3710 }
3711
3712 if (module_en_update & ISP2X_MODULE_RAWAE0)
3713 ops->rawae0_enable(params_vdev, !!(module_ens & ISP2X_MODULE_RAWAE0));
3714
3715 if (module_en_update & ISP2X_MODULE_RAWAE1)
3716 ops->rawae1_enable(params_vdev, !!(module_ens & ISP2X_MODULE_RAWAE1));
3717
3718 if (module_en_update & ISP2X_MODULE_RAWAE2)
3719 ops->rawae2_enable(params_vdev, !!(module_ens & ISP2X_MODULE_RAWAE2));
3720
3721 if (module_en_update & ISP2X_MODULE_RAWAE3)
3722 ops->rawae3_enable(params_vdev, !!(module_ens & ISP2X_MODULE_RAWAE3));
3723
3724 if (module_en_update & ISP2X_MODULE_RAWHIST0)
3725 ops->rawhst0_enable(params_vdev, !!(module_ens & ISP2X_MODULE_RAWHIST0));
3726
3727 if (module_en_update & ISP2X_MODULE_RAWHIST1)
3728 ops->rawhst1_enable(params_vdev, !!(module_ens & ISP2X_MODULE_RAWHIST1));
3729
3730 if (module_en_update & ISP2X_MODULE_RAWHIST2)
3731 ops->rawhst2_enable(params_vdev, !!(module_ens & ISP2X_MODULE_RAWHIST2));
3732
3733 if (module_en_update & ISP2X_MODULE_RAWHIST3)
3734 ops->rawhst3_enable(params_vdev, !!(module_ens & ISP2X_MODULE_RAWHIST3));
3735
3736 if (module_en_update & ISP2X_MODULE_RAWAWB)
3737 ops->rawawb_enable(params_vdev, !!(module_ens & ISP2X_MODULE_RAWAWB));
3738
3739 if (module_en_update & ISP2X_MODULE_RAWAF)
3740 ops->rawaf_enable(params_vdev, !!(module_ens & ISP2X_MODULE_RAWAF));
3741 }
3742
3743 static __maybe_unused
__isp_config_hdrshd(struct rkisp_isp_params_vdev * params_vdev)3744 void __isp_config_hdrshd(struct rkisp_isp_params_vdev *params_vdev)
3745 {
3746 struct rkisp_isp_params_v21_ops *ops =
3747 (struct rkisp_isp_params_v21_ops *)params_vdev->priv_ops;
3748 struct rkisp_isp_params_val_v21 *priv_val =
3749 (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
3750
3751 ops->hdrmge_config(params_vdev, &priv_val->last_hdrmge, RKISP_PARAMS_SHD);
3752
3753 ops->hdrdrc_config(params_vdev, &priv_val->last_hdrdrc, RKISP_PARAMS_SHD);
3754 }
3755
3756 static
rkisp_params_cfgsram_v21(struct rkisp_isp_params_vdev * params_vdev)3757 void rkisp_params_cfgsram_v21(struct rkisp_isp_params_vdev *params_vdev)
3758 {
3759 struct isp21_isp_params_cfg *params = params_vdev->isp21_params;
3760
3761 isp_lsc_matrix_cfg_sram(params_vdev, ¶ms->others.lsc_cfg, true);
3762 isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist1, 1, true);
3763 isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist2, 2, true);
3764 isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist3, 0, true);
3765 isp_rawawb_cfg_sram(params_vdev, ¶ms->meas.rawawb, true);
3766 }
3767
3768 static void
rkisp_alloc_bay3d_buf(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_isp_params_cfg * new_params)3769 rkisp_alloc_bay3d_buf(struct rkisp_isp_params_vdev *params_vdev,
3770 const struct isp21_isp_params_cfg *new_params)
3771 {
3772 struct rkisp_device *ispdev = params_vdev->dev;
3773 struct rkisp_isp_subdev *isp_sdev = &ispdev->isp_sdev;
3774 struct rkisp_isp_params_val_v21 *priv_val;
3775 u64 module_en_update, module_ens;
3776 u32 w, h, size;
3777 int ret;
3778
3779 module_en_update = new_params->module_en_update;
3780 module_ens = new_params->module_ens;
3781
3782 if ((module_en_update & ISP2X_MODULE_BAY3D) &&
3783 (module_ens & ISP2X_MODULE_BAY3D)) {
3784 w = isp_sdev->in_crop.width;
3785 h = isp_sdev->in_crop.height;
3786 size = 2 * ALIGN((ALIGN(w, 16) + (w + 15) / 8) * h, 16);
3787 priv_val = (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
3788 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr);
3789 priv_val->buf_3dnr.size = size;
3790 ret = rkisp_alloc_buffer(ispdev, &priv_val->buf_3dnr);
3791 if (ret)
3792 dev_err(ispdev->dev, "can not alloc bay3d buffer\n");
3793 }
3794 }
3795
3796 static bool
rkisp_params_check_bigmode_v21(struct rkisp_isp_params_vdev * params_vdev)3797 rkisp_params_check_bigmode_v21(struct rkisp_isp_params_vdev *params_vdev)
3798 {
3799 struct rkisp_device *ispdev = params_vdev->dev;
3800 struct device *dev = params_vdev->dev->dev;
3801 struct rkisp_hw_dev *hw = params_vdev->dev->hw_dev;
3802 struct v4l2_rect *crop = ¶ms_vdev->dev->isp_sdev.in_crop;
3803 u32 width = hw->max_in.w, height = hw->max_in.h, size = width * height;
3804 u32 bigmode_max_w, bigmode_max_size;
3805 int k = 0, idx1[DEV_MAX] = { 0 };
3806 int n = 0, idx2[DEV_MAX] = { 0 };
3807 int i = 0, j = 0;
3808 bool is_bigmode = false;
3809
3810 multi_overflow:
3811 if (hw->is_multi_overflow) {
3812 ispdev->multi_index = 0;
3813 ispdev->multi_mode = 0;
3814 bigmode_max_w = ISP21_AUTO_BIGMODE_WIDTH;
3815 bigmode_max_size = ISP21_NOBIG_OVERFLOW_SIZE;
3816 dev_warn(dev, "over virtual isp max resolution, force to 2 readback\n");
3817 goto end;
3818 }
3819
3820 switch (hw->dev_link_num) {
3821 case 4:
3822 bigmode_max_w = ISP21_VIR4_AUTO_BIGMODE_WIDTH;
3823 bigmode_max_size = ISP21_VIR4_NOBIG_OVERFLOW_SIZE;
3824 ispdev->multi_index = ispdev->dev_id;
3825 ispdev->multi_mode = 2;
3826 /* internal buf of hw divided to four parts
3827 * bigmode nobigmode
3828 * _________ max width:1920 max width:960
3829 * |_sensor0_| max size:1920*1080 max size:960*540
3830 * |_sensor1_| max size:1920*1080 max size:960*540
3831 * |_sensor2_| max size:1920*1080 max size:960*540
3832 * |_sensor3_| max size:1920*1080 max size:960*540
3833 */
3834 for (i = 0; i < hw->dev_num; i++) {
3835 if (hw->isp_size[i].w <= ISP21_VIR4_MAX_WIDTH &&
3836 hw->isp_size[i].size <= ISP21_VIR4_MAX_SIZE)
3837 continue;
3838 dev_warn(dev, "isp%d %dx%d over four vir isp max:1920x1080\n",
3839 i, hw->isp_size[i].w, hw->isp_size[i].h);
3840 hw->is_multi_overflow = true;
3841 goto multi_overflow;
3842 }
3843 break;
3844 case 3:
3845 bigmode_max_w = ISP21_VIR4_AUTO_BIGMODE_WIDTH;
3846 bigmode_max_size = ISP21_VIR4_NOBIG_OVERFLOW_SIZE;
3847 ispdev->multi_index = ispdev->dev_id;
3848 ispdev->multi_mode = 2;
3849 /* case0: bigmode nobigmode
3850 * _________ max width:1920 max width:960
3851 * |_sensor0_| max size:1920*1080 max size:960*540
3852 * |_sensor1_| max size:1920*1080 max size:960*540
3853 * |_sensor2_| max size:1920*1080 max size:960*540
3854 * |_________|
3855 *
3856 * case1: bigmode special reg cfg
3857 * _________ max width:3840
3858 * | sensor0 | max size:3840*2160 mode=1 index=0
3859 * |_________|
3860 * |_sensor1_| max size:1920*1080 mode=2 index=2
3861 * |_sensor2_| max size:1920*1080 mode=2 index=3
3862 * max width:1920
3863 */
3864 for (i = 0; i < hw->dev_num; i++) {
3865 if (!hw->isp_size[i].size) {
3866 if (i < hw->dev_link_num)
3867 idx2[n++] = i;
3868 continue;
3869 }
3870 if (hw->isp_size[i].w <= ISP21_VIR4_MAX_WIDTH &&
3871 hw->isp_size[i].size <= ISP21_VIR4_MAX_SIZE)
3872 continue;
3873 idx1[k++] = i;
3874 }
3875 if (k) {
3876 is_bigmode = true;
3877 if (k != 1 ||
3878 (hw->isp_size[idx1[0]].size > ISP21_VIR2_MAX_SIZE)) {
3879 dev_warn(dev, "isp%d %dx%d over three vir isp max:1920x1080\n",
3880 idx1[0], hw->isp_size[idx1[0]].h, hw->isp_size[idx1[0]].w);
3881 hw->is_multi_overflow = true;
3882 goto multi_overflow;
3883 } else {
3884 if (idx1[0] == ispdev->dev_id) {
3885 ispdev->multi_mode = 1;
3886 ispdev->multi_index = 0;
3887 } else {
3888 ispdev->multi_mode = 2;
3889 if (ispdev->multi_index == 0 ||
3890 ispdev->multi_index == 1)
3891 ispdev->multi_index = 3;
3892 }
3893 }
3894 } else if (ispdev->multi_index >= hw->dev_link_num) {
3895 ispdev->multi_index = idx2[ispdev->multi_index - hw->dev_link_num];
3896 }
3897 break;
3898 case 2:
3899 bigmode_max_w = ISP21_VIR2_AUTO_BIGMODE_WIDTH;
3900 bigmode_max_size = ISP21_VIR2_NOBIG_OVERFLOW_SIZE;
3901 ispdev->multi_index = ispdev->dev_id;
3902 ispdev->multi_mode = 1;
3903 /* case0: bigmode nobigmode
3904 * _________ max width:3840 max width:1920
3905 * | sensor0 | max size:3840*2160 max size:1920*1080
3906 * |_________|
3907 * | sensor1 | max size:3840*2160 max size:1920*1080
3908 * |_________|
3909 *
3910 * case1: bigmode special reg cfg
3911 * _________ max width:4096
3912 * | sensor0 | max size: mode=0 index=0
3913 * | | 3840*2160+1920*1080
3914 * |_________|
3915 * |_sensor1_| max size:1920*1080 mode=2 index=3
3916 * max width:1920
3917 */
3918 for (i = 0; i < hw->dev_num; i++) {
3919 if (!hw->isp_size[i].size) {
3920 if (i < hw->dev_link_num)
3921 idx2[n++] = i;
3922 continue;
3923 }
3924 if (hw->isp_size[i].w <= ISP21_VIR2_MAX_WIDTH &&
3925 hw->isp_size[i].size <= ISP21_VIR2_MAX_SIZE) {
3926 if (hw->isp_size[i].w > ISP21_VIR4_MAX_WIDTH ||
3927 hw->isp_size[i].size > ISP21_VIR4_MAX_SIZE)
3928 j++;
3929 continue;
3930 }
3931 idx1[k++] = i;
3932 }
3933 if (k) {
3934 is_bigmode = true;
3935 if (k == 2 || j ||
3936 hw->isp_size[idx1[k - 1]].size > (ISP21_VIR4_MAX_SIZE + ISP21_VIR2_MAX_SIZE)) {
3937 dev_warn(dev, "isp%d %dx%d over two vir isp max:3840x2160\n",
3938 idx1[k - 1], hw->isp_size[idx1[k - 1]].w, hw->isp_size[idx1[k - 1]].h);
3939 hw->is_multi_overflow = true;
3940 goto multi_overflow;
3941 } else {
3942 if (idx1[0] == ispdev->dev_id) {
3943 ispdev->multi_mode = 0;
3944 ispdev->multi_index = 0;
3945 } else {
3946 ispdev->multi_mode = 2;
3947 ispdev->multi_index = 3;
3948 }
3949 }
3950 } else if (ispdev->multi_index >= hw->dev_link_num) {
3951 ispdev->multi_index = idx2[ispdev->multi_index - hw->dev_link_num];
3952 }
3953 break;
3954 default:
3955 bigmode_max_w = ISP21_AUTO_BIGMODE_WIDTH;
3956 bigmode_max_size = ISP21_NOBIG_OVERFLOW_SIZE;
3957 ispdev->multi_mode = 0;
3958 ispdev->multi_index = 0;
3959 width = crop->width;
3960 height = crop->height;
3961 size = width * height;
3962 break;
3963 }
3964
3965 end:
3966 if (!is_bigmode &&
3967 (width > bigmode_max_w || size > bigmode_max_size))
3968 is_bigmode = true;
3969
3970 return ispdev->is_bigmode = is_bigmode;
3971 }
3972
3973 /* Not called when the camera active, thus not isr protection. */
3974 static void
rkisp_params_first_cfg_v2x(struct rkisp_isp_params_vdev * params_vdev)3975 rkisp_params_first_cfg_v2x(struct rkisp_isp_params_vdev *params_vdev)
3976 {
3977 struct rkisp_device *dev = params_vdev->dev;
3978 struct rkisp_isp_params_val_v21 *priv_val =
3979 (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
3980
3981 dev->is_bigmode = rkisp_params_check_bigmode_v21(params_vdev);
3982 spin_lock(¶ms_vdev->config_lock);
3983 /* override the default things */
3984 if (!params_vdev->isp21_params->module_cfg_update &&
3985 !params_vdev->isp21_params->module_en_update)
3986 dev_warn(dev->dev, "can not get first iq setting in stream on\n");
3987
3988 priv_val->dhaz_en = 0;
3989 priv_val->wdr_en = 0;
3990 priv_val->tmo_en = 0;
3991 priv_val->lsc_en = 0;
3992 priv_val->mge_en = 0;
3993 __isp_isr_meas_config(params_vdev, params_vdev->isp21_params, RKISP_PARAMS_ALL);
3994 __isp_isr_other_config(params_vdev, params_vdev->isp21_params, RKISP_PARAMS_ALL);
3995 __isp_isr_other_en(params_vdev, params_vdev->isp21_params, RKISP_PARAMS_ALL);
3996 __isp_isr_meas_en(params_vdev, params_vdev->isp21_params, RKISP_PARAMS_ALL);
3997 if (dev->is_bigmode)
3998 rkisp_set_bits(params_vdev->dev, ISP_CTRL1,
3999 ISP2X_SYS_BIGMODE_MANUAL | ISP2X_SYS_BIGMODE_FORCEEN,
4000 ISP2X_SYS_BIGMODE_MANUAL | ISP2X_SYS_BIGMODE_FORCEEN, false);
4001
4002 priv_val->cur_hdrmge = params_vdev->isp21_params->others.hdrmge_cfg;
4003 priv_val->cur_hdrdrc = params_vdev->isp21_params->others.drc_cfg;
4004 priv_val->last_hdrmge = priv_val->cur_hdrmge;
4005 priv_val->last_hdrdrc = priv_val->cur_hdrdrc;
4006 spin_unlock(¶ms_vdev->config_lock);
4007 }
4008
rkisp_save_first_param_v2x(struct rkisp_isp_params_vdev * params_vdev,void * param)4009 static void rkisp_save_first_param_v2x(struct rkisp_isp_params_vdev *params_vdev, void *param)
4010 {
4011 struct isp21_isp_params_cfg *new_params;
4012
4013 new_params = (struct isp21_isp_params_cfg *)param;
4014 *params_vdev->isp21_params = *new_params;
4015 rkisp_alloc_bay3d_buf(params_vdev, params_vdev->isp21_params);
4016 }
4017
rkisp_clear_first_param_v2x(struct rkisp_isp_params_vdev * params_vdev)4018 static void rkisp_clear_first_param_v2x(struct rkisp_isp_params_vdev *params_vdev)
4019 {
4020 params_vdev->isp21_params->module_cfg_update = 0;
4021 params_vdev->isp21_params->module_en_update = 0;
4022 }
4023
rkisp_get_ldch_meshsize(struct rkisp_isp_params_vdev * params_vdev,struct rkisp_ldchbuf_size * ldchsize)4024 static u32 rkisp_get_ldch_meshsize(struct rkisp_isp_params_vdev *params_vdev,
4025 struct rkisp_ldchbuf_size *ldchsize)
4026 {
4027 int mesh_w, mesh_h, map_align;
4028
4029 mesh_w = ((ldchsize->meas_width + (1 << 4) - 1) >> 4) + 1;
4030 mesh_h = ((ldchsize->meas_height + (1 << 3) - 1) >> 3) + 1;
4031
4032 map_align = ((mesh_w + 1) >> 1) << 1;
4033 return map_align * mesh_h;
4034 }
4035
rkisp_deinit_ldch_buf(struct rkisp_isp_params_vdev * params_vdev)4036 static void rkisp_deinit_ldch_buf(struct rkisp_isp_params_vdev *params_vdev)
4037 {
4038 struct rkisp_isp_params_val_v21 *priv_val;
4039 int i;
4040
4041 priv_val = params_vdev->priv_val;
4042 if (!priv_val)
4043 return;
4044
4045 for (i = 0; i < ISP2X_LDCH_BUF_NUM; i++)
4046 rkisp_free_buffer(params_vdev->dev, &priv_val->buf_ldch[i]);
4047 }
4048
rkisp_init_ldch_buf(struct rkisp_isp_params_vdev * params_vdev,struct rkisp_ldchbuf_size * ldchsize)4049 static int rkisp_init_ldch_buf(struct rkisp_isp_params_vdev *params_vdev,
4050 struct rkisp_ldchbuf_size *ldchsize)
4051 {
4052 struct device *dev = params_vdev->dev->dev;
4053 struct rkisp_isp_params_val_v21 *priv_val;
4054 struct isp2x_ldch_head *ldch_head;
4055 u32 mesh_size, buf_size;
4056 int i, ret;
4057
4058 priv_val = params_vdev->priv_val;
4059 if (!priv_val) {
4060 dev_err(dev, "priv_val is NULL\n");
4061 return -EINVAL;
4062 }
4063
4064 priv_val->buf_ldch_idx = 0;
4065 mesh_size = rkisp_get_ldch_meshsize(params_vdev, ldchsize);
4066 buf_size = PAGE_ALIGN(mesh_size * sizeof(u16) + ALIGN(sizeof(struct isp2x_ldch_head), 16));
4067 for (i = 0; i < ISP2X_LDCH_BUF_NUM; i++) {
4068 priv_val->buf_ldch[i].is_need_vaddr = true;
4069 priv_val->buf_ldch[i].is_need_dbuf = true;
4070 priv_val->buf_ldch[i].is_need_dmafd = true;
4071 priv_val->buf_ldch[i].size = buf_size;
4072 ret = rkisp_alloc_buffer(params_vdev->dev, &priv_val->buf_ldch[i]);
4073 if (ret) {
4074 dev_err(dev, "can not alloc buffer\n");
4075 goto err;
4076 }
4077
4078 ldch_head = (struct isp2x_ldch_head *)priv_val->buf_ldch[i].vaddr;
4079 ldch_head->stat = LDCH_BUF_INIT;
4080 ldch_head->data_oft = ALIGN(sizeof(struct isp2x_ldch_head), 16);
4081 }
4082
4083 return 0;
4084
4085 err:
4086 rkisp_deinit_ldch_buf(params_vdev);
4087
4088 return -ENOMEM;
4089
4090 }
4091
4092 static void
rkisp_get_param_size_v2x(struct rkisp_isp_params_vdev * params_vdev,unsigned int sizes[])4093 rkisp_get_param_size_v2x(struct rkisp_isp_params_vdev *params_vdev,
4094 unsigned int sizes[])
4095 {
4096 sizes[0] = sizeof(struct isp2x_isp_params_cfg);
4097 }
4098
4099 static void
rkisp_params_get_ldchbuf_inf_v2x(struct rkisp_isp_params_vdev * params_vdev,void * buf)4100 rkisp_params_get_ldchbuf_inf_v2x(struct rkisp_isp_params_vdev *params_vdev,
4101 void *buf)
4102 {
4103 struct rkisp_isp_params_val_v21 *priv_val;
4104 struct rkisp_ldchbuf_info *ldchbuf = buf;
4105 int i;
4106
4107 priv_val = params_vdev->priv_val;
4108 for (i = 0; i < ISP2X_LDCH_BUF_NUM; i++) {
4109 ldchbuf->buf_fd[i] = priv_val->buf_ldch[i].dma_fd;
4110 ldchbuf->buf_size[i] = priv_val->buf_ldch[i].size;
4111 }
4112 }
4113
4114 static int
rkisp_params_set_ldchbuf_size_v2x(struct rkisp_isp_params_vdev * params_vdev,void * size)4115 rkisp_params_set_ldchbuf_size_v2x(struct rkisp_isp_params_vdev *params_vdev,
4116 void *size)
4117 {
4118 struct rkisp_ldchbuf_size *ldchsize = size;
4119
4120 rkisp_deinit_ldch_buf(params_vdev);
4121 return rkisp_init_ldch_buf(params_vdev, ldchsize);
4122 }
4123
4124 static void
rkisp_params_free_meshbuf_v21(struct rkisp_isp_params_vdev * params_vdev,u64 module_id)4125 rkisp_params_free_meshbuf_v21(struct rkisp_isp_params_vdev *params_vdev,
4126 u64 module_id)
4127 {
4128 rkisp_deinit_ldch_buf(params_vdev);
4129 }
4130
4131 static void
rkisp_params_stream_stop_v2x(struct rkisp_isp_params_vdev * params_vdev)4132 rkisp_params_stream_stop_v2x(struct rkisp_isp_params_vdev *params_vdev)
4133 {
4134 struct rkisp_device *ispdev = params_vdev->dev;
4135 struct rkisp_isp_params_val_v21 *priv_val;
4136
4137 priv_val = (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
4138 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr);
4139 }
4140
4141 static void
rkisp_params_fop_release_v2x(struct rkisp_isp_params_vdev * params_vdev)4142 rkisp_params_fop_release_v2x(struct rkisp_isp_params_vdev *params_vdev)
4143 {
4144 rkisp_deinit_ldch_buf(params_vdev);
4145 }
4146
4147 /* Not called when the camera active, thus not isr protection. */
4148 static void
rkisp_params_disable_isp_v2x(struct rkisp_isp_params_vdev * params_vdev)4149 rkisp_params_disable_isp_v2x(struct rkisp_isp_params_vdev *params_vdev)
4150 {
4151 struct rkisp_isp_params_v21_ops *ops =
4152 (struct rkisp_isp_params_v21_ops *)params_vdev->priv_ops;
4153
4154 ops->dpcc_enable(params_vdev, false);
4155 ops->bls_enable(params_vdev, false);
4156 ops->sdg_enable(params_vdev, false);
4157 ops->lsc_enable(params_vdev, false);
4158 ops->awbgain_enable(params_vdev, false);
4159 ops->debayer_enable(params_vdev, false);
4160 ops->ccm_enable(params_vdev, false);
4161 ops->goc_enable(params_vdev, false);
4162 ops->cproc_enable(params_vdev, false);
4163 ops->ie_enable(params_vdev, false);
4164 ops->rawaf_enable(params_vdev, false);
4165 ops->rawae0_enable(params_vdev, false);
4166 ops->rawae1_enable(params_vdev, false);
4167 ops->rawae2_enable(params_vdev, false);
4168 ops->rawae3_enable(params_vdev, false);
4169 ops->rawawb_enable(params_vdev, false);
4170 ops->rawhst0_enable(params_vdev, false);
4171 ops->rawhst1_enable(params_vdev, false);
4172 ops->rawhst2_enable(params_vdev, false);
4173 ops->rawhst3_enable(params_vdev, false);
4174 ops->hdrmge_enable(params_vdev, false);
4175 ops->hdrdrc_enable(params_vdev, false);
4176 ops->gic_enable(params_vdev, false);
4177 ops->dhaz_enable(params_vdev, false);
4178 ops->isp3dlut_enable(params_vdev, false);
4179 ops->ldch_enable(params_vdev, false);
4180 ops->ynr_enable(params_vdev, false, NULL);
4181 ops->cnr_enable(params_vdev, false, NULL);
4182 ops->sharp_enable(params_vdev, false);
4183 ops->baynr_enable(params_vdev, false);
4184 ops->bay3d_enable(params_vdev, false);
4185 }
4186
4187 static void
ldch_data_abandon(struct rkisp_isp_params_vdev * params_vdev,struct isp21_isp_params_cfg * params)4188 ldch_data_abandon(struct rkisp_isp_params_vdev *params_vdev,
4189 struct isp21_isp_params_cfg *params)
4190 {
4191 const struct isp2x_ldch_cfg *arg = ¶ms->others.ldch_cfg;
4192 struct rkisp_isp_params_val_v21 *priv_val;
4193 struct isp2x_ldch_head *ldch_head;
4194 int i;
4195
4196 priv_val = (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
4197 for (i = 0; i < ISP2X_LDCH_BUF_NUM; i++) {
4198 if (arg->buf_fd == priv_val->buf_ldch[i].dma_fd &&
4199 priv_val->buf_ldch[i].vaddr) {
4200 ldch_head = (struct isp2x_ldch_head *)priv_val->buf_ldch[i].vaddr;
4201 ldch_head->stat = LDCH_BUF_CHIPINUSE;
4202 break;
4203 }
4204 }
4205 }
4206
4207 static void
rkisp_params_cfg_v2x(struct rkisp_isp_params_vdev * params_vdev,u32 frame_id,enum rkisp_params_type type)4208 rkisp_params_cfg_v2x(struct rkisp_isp_params_vdev *params_vdev,
4209 u32 frame_id, enum rkisp_params_type type)
4210 {
4211 struct isp21_isp_params_cfg *new_params = NULL;
4212 struct rkisp_buffer *cur_buf = params_vdev->cur_buf;
4213 struct rkisp_device *dev = params_vdev->dev;
4214 struct rkisp_hw_dev *hw_dev = dev->hw_dev;
4215
4216 spin_lock(¶ms_vdev->config_lock);
4217 if (!params_vdev->streamon)
4218 goto unlock;
4219
4220 /* get buffer by frame_id */
4221 while (!list_empty(¶ms_vdev->params) && !cur_buf) {
4222 cur_buf = list_first_entry(¶ms_vdev->params,
4223 struct rkisp_buffer, queue);
4224
4225 new_params = (struct isp21_isp_params_cfg *)(cur_buf->vaddr[0]);
4226 if (new_params->frame_id < frame_id) {
4227 list_del(&cur_buf->queue);
4228 if (list_empty(¶ms_vdev->params))
4229 break;
4230 else if (new_params->module_en_update ||
4231 (new_params->module_cfg_update & ISP2X_MODULE_FORCE)) {
4232 /* update en immediately */
4233 __isp_isr_meas_config(params_vdev, new_params, type);
4234 __isp_isr_other_config(params_vdev, new_params, type);
4235 __isp_isr_other_en(params_vdev, new_params, type);
4236 __isp_isr_meas_en(params_vdev, new_params, type);
4237 new_params->module_cfg_update = 0;
4238 }
4239 if (new_params->module_cfg_update & ISP2X_MODULE_LDCH)
4240 ldch_data_abandon(params_vdev, new_params);
4241 vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
4242 cur_buf = NULL;
4243 continue;
4244 } else if (new_params->frame_id == frame_id) {
4245 list_del(&cur_buf->queue);
4246 } else {
4247 cur_buf = NULL;
4248 }
4249 break;
4250 }
4251
4252 if (!cur_buf)
4253 goto unlock;
4254
4255 new_params = (struct isp21_isp_params_cfg *)(cur_buf->vaddr[0]);
4256 __isp_isr_meas_config(params_vdev, new_params, type);
4257 __isp_isr_other_config(params_vdev, new_params, type);
4258 __isp_isr_other_en(params_vdev, new_params, type);
4259 __isp_isr_meas_en(params_vdev, new_params, type);
4260 if (!hw_dev->is_single && type != RKISP_PARAMS_SHD)
4261 __isp_config_hdrshd(params_vdev);
4262
4263 if (type != RKISP_PARAMS_IMD) {
4264 struct rkisp_isp_params_val_v21 *priv_val =
4265 (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
4266
4267 priv_val->last_hdrmge = priv_val->cur_hdrmge;
4268 priv_val->last_hdrdrc = priv_val->cur_hdrdrc;
4269 priv_val->cur_hdrmge = new_params->others.hdrmge_cfg;
4270 priv_val->cur_hdrdrc = new_params->others.drc_cfg;
4271 new_params->module_cfg_update = 0;
4272 vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
4273 cur_buf = NULL;
4274 }
4275
4276 unlock:
4277 params_vdev->cur_buf = cur_buf;
4278 spin_unlock(¶ms_vdev->config_lock);
4279 }
4280
4281 static void
rkisp_params_clear_fstflg(struct rkisp_isp_params_vdev * params_vdev)4282 rkisp_params_clear_fstflg(struct rkisp_isp_params_vdev *params_vdev)
4283 {
4284 u32 value;
4285
4286 value = rkisp_ioread32(params_vdev, ISP_CTRL1);
4287 if (value & ISP2X_SYS_YNR_FST)
4288 rkisp_clear_bits(params_vdev->dev, ISP_CTRL1,
4289 ISP2X_SYS_YNR_FST, false);
4290 if (value & ISP2X_SYS_ADRC_FST)
4291 rkisp_clear_bits(params_vdev->dev, ISP_CTRL1,
4292 ISP2X_SYS_ADRC_FST, false);
4293 if (value & ISP2X_SYS_DHAZ_FST)
4294 rkisp_clear_bits(params_vdev->dev, ISP_CTRL1,
4295 ISP2X_SYS_DHAZ_FST, false);
4296 if (value & ISP2X_SYS_CNR_FST)
4297 rkisp_clear_bits(params_vdev->dev, ISP_CTRL1,
4298 ISP2X_SYS_CNR_FST, false);
4299 if (value & ISP2X_SYS_BAY3D_FST)
4300 rkisp_clear_bits(params_vdev->dev, ISP_CTRL1,
4301 ISP2X_SYS_BAY3D_FST, false);
4302 }
4303
4304 static void
rkisp_params_isr_v2x(struct rkisp_isp_params_vdev * params_vdev,u32 isp_mis)4305 rkisp_params_isr_v2x(struct rkisp_isp_params_vdev *params_vdev,
4306 u32 isp_mis)
4307 {
4308 struct rkisp_device *dev = params_vdev->dev;
4309 u32 cur_frame_id;
4310
4311 rkisp_dmarx_get_frame(dev, &cur_frame_id, NULL, NULL, true);
4312 if (isp_mis & CIF_ISP_V_START) {
4313 if (params_vdev->rdbk_times)
4314 params_vdev->rdbk_times--;
4315 if (!params_vdev->cur_buf)
4316 return;
4317
4318 if (IS_HDR_RDBK(dev->rd_mode) && !params_vdev->rdbk_times) {
4319 rkisp_params_cfg_v2x(params_vdev, cur_frame_id, RKISP_PARAMS_SHD);
4320 return;
4321 }
4322 }
4323
4324 if (isp_mis & CIF_ISP_FRAME)
4325 rkisp_params_clear_fstflg(params_vdev);
4326
4327 if ((isp_mis & CIF_ISP_FRAME) && !IS_HDR_RDBK(dev->rd_mode))
4328 rkisp_params_cfg_v2x(params_vdev, cur_frame_id + 1, RKISP_PARAMS_ALL);
4329 }
4330
4331 static struct rkisp_isp_params_ops rkisp_isp_params_ops_tbl = {
4332 .save_first_param = rkisp_save_first_param_v2x,
4333 .clear_first_param = rkisp_clear_first_param_v2x,
4334 .get_param_size = rkisp_get_param_size_v2x,
4335 .first_cfg = rkisp_params_first_cfg_v2x,
4336 .disable_isp = rkisp_params_disable_isp_v2x,
4337 .isr_hdl = rkisp_params_isr_v2x,
4338 .param_cfg = rkisp_params_cfg_v2x,
4339 .param_cfgsram = rkisp_params_cfgsram_v21,
4340 .get_meshbuf_inf = rkisp_params_get_ldchbuf_inf_v2x,
4341 .set_meshbuf_size = rkisp_params_set_ldchbuf_size_v2x,
4342 .free_meshbuf = rkisp_params_free_meshbuf_v21,
4343 .stream_stop = rkisp_params_stream_stop_v2x,
4344 .fop_release = rkisp_params_fop_release_v2x,
4345 .check_bigmode = rkisp_params_check_bigmode_v21,
4346 };
4347
rkisp_init_params_vdev_v21(struct rkisp_isp_params_vdev * params_vdev)4348 int rkisp_init_params_vdev_v21(struct rkisp_isp_params_vdev *params_vdev)
4349 {
4350 struct device *dev = params_vdev->dev->dev;
4351 struct rkisp_isp_params_val_v21 *priv_val;
4352 int i, ret;
4353
4354 priv_val = kzalloc(sizeof(*priv_val), GFP_KERNEL);
4355 if (!priv_val)
4356 return -ENOMEM;
4357
4358 params_vdev->isp21_params = vmalloc(sizeof(*params_vdev->isp21_params));
4359 if (!params_vdev->isp21_params) {
4360 kfree(priv_val);
4361 return -ENOMEM;
4362 }
4363
4364 priv_val->buf_3dlut_idx = 0;
4365 for (i = 0; i < RKISP_PARAM_3DLUT_BUF_NUM; i++) {
4366 priv_val->buf_3dlut[i].is_need_vaddr = true;
4367 priv_val->buf_3dlut[i].size = RKISP_PARAM_3DLUT_BUF_SIZE;
4368 ret = rkisp_alloc_buffer(params_vdev->dev, &priv_val->buf_3dlut[i]);
4369 if (ret) {
4370 dev_err(dev, "can not alloc buffer\n");
4371 goto err;
4372 }
4373 }
4374
4375 priv_val->buf_lsclut_idx = 0;
4376 for (i = 0; i < RKISP_PARAM_LSC_LUT_BUF_NUM; i++) {
4377 priv_val->buf_lsclut[i].is_need_vaddr = true;
4378 priv_val->buf_lsclut[i].size = RKISP_PARAM_LSC_LUT_BUF_SIZE;
4379 ret = rkisp_alloc_buffer(params_vdev->dev, &priv_val->buf_lsclut[i]);
4380 if (ret) {
4381 dev_err(dev, "can not alloc buffer\n");
4382 goto err;
4383 }
4384 }
4385
4386 params_vdev->priv_val = (void *)priv_val;
4387 params_vdev->ops = &rkisp_isp_params_ops_tbl;
4388 params_vdev->priv_ops = &rkisp_v21_isp_params_ops;
4389 rkisp_clear_first_param_v2x(params_vdev);
4390 return 0;
4391
4392 err:
4393 for (i = 0; i < RKISP_PARAM_3DLUT_BUF_NUM; i++)
4394 rkisp_free_buffer(params_vdev->dev, &priv_val->buf_3dlut[i]);
4395
4396 for (i = 0; i < RKISP_PARAM_LSC_LUT_BUF_NUM; i++)
4397 rkisp_free_buffer(params_vdev->dev, &priv_val->buf_lsclut[i]);
4398 vfree(params_vdev->isp21_params);
4399
4400 return ret;
4401 }
4402
rkisp_uninit_params_vdev_v21(struct rkisp_isp_params_vdev * params_vdev)4403 void rkisp_uninit_params_vdev_v21(struct rkisp_isp_params_vdev *params_vdev)
4404 {
4405 struct rkisp_isp_params_val_v21 *priv_val;
4406 int i;
4407
4408 priv_val = params_vdev->priv_val;
4409 if (!priv_val)
4410 return;
4411
4412 rkisp_deinit_ldch_buf(params_vdev);
4413 for (i = 0; i < RKISP_PARAM_3DLUT_BUF_NUM; i++)
4414 rkisp_free_buffer(params_vdev->dev, &priv_val->buf_3dlut[i]);
4415
4416 for (i = 0; i < RKISP_PARAM_LSC_LUT_BUF_NUM; i++)
4417 rkisp_free_buffer(params_vdev->dev, &priv_val->buf_lsclut[i]);
4418 vfree(params_vdev->isp21_params);
4419 kfree(priv_val);
4420 params_vdev->priv_val = NULL;
4421 }
4422
4423