1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2021 Rockchip Electronics Co., Ltd. */
3
4 #include <media/v4l2-common.h>
5 #include <media/v4l2-ioctl.h>
6 #include <media/videobuf2-core.h>
7 #include <media/videobuf2-vmalloc.h> /* for ISP params */
8 #include "dev.h"
9 #include "regs.h"
10 #include "isp_params_v32.h"
11
12 #define ISP32_MODULE_EN BIT(0)
13 #define ISP32_SELF_FORCE_UPD BIT(31)
14 #define ISP32_REG_WR_MASK BIT(31) //disable write protect
15
16 #define ISP32_NOBIG_OVERFLOW_SIZE (1536 * 896)
17 #define ISP32_AUTO_BIGMODE_WIDTH 1536
18 #define ISP32_VIR2_NOBIG_OVERFLOW_SIZE (960 * 540)
19 #define ISP32_VIR2_AUTO_BIGMODE_WIDTH 960
20 #define ISP32_VIR4_NOBIG_OVERFLOW_SIZE (640 * 400)
21 #define ISP32_VIR4_AUTO_BIGMODE_WIDTH 640
22
23 #define ISP32_VIR2_MAX_WIDTH 1920
24 #define ISP32_VIR2_MAX_SIZE (1920 * 1080)
25 #define ISP32_VIR4_MAX_WIDTH 1280
26 #define ISP32_VIR4_MAX_SIZE (1280 * 800)
27
28 #define ISP32_LITE_NOBIG_OVERFLOW_SIZE (2688 * 1536)
29 #define ISP32_LITE_AUTO_BIGMODE_WIDTH 2688
30 #define ISP32_LITE_VIR2_NOBIG_OVERFLOW_SIZE (1920 * 1080)
31 #define ISP32_LITE_VIR2_AUTO_BIGMODE_WIDTH 1920
32 #define ISP32_LITE_VIR4_NOBIG_OVERFLOW_SIZE (1280 * 800)
33 #define ISP32_LITE_VIR4_AUTO_BIGMODE_WIDTH 1280
34 #define ISP32_LITE_VIR2_MAX_WIDTH 3840
35 #define ISP32_LITE_VIR2_MAX_SIZE (3840 * 2160)
36 #define ISP32_LITE_VIR4_MAX_WIDTH 2688
37 #define ISP32_LITE_VIR4_MAX_SIZE (2688 * 1536)
38
39 #define ISP32_LITE_FRM_BUF_SIZE 0x1d000
40
41 static inline void
isp3_param_write_direct(struct rkisp_isp_params_vdev * params_vdev,u32 value,u32 addr)42 isp3_param_write_direct(struct rkisp_isp_params_vdev *params_vdev,
43 u32 value, u32 addr)
44 {
45 rkisp_write(params_vdev->dev, addr, value, true);
46 }
47
48 static inline void
isp3_param_write(struct rkisp_isp_params_vdev * params_vdev,u32 value,u32 addr)49 isp3_param_write(struct rkisp_isp_params_vdev *params_vdev,
50 u32 value, u32 addr)
51 {
52 rkisp_write(params_vdev->dev, addr, value, false);
53 }
54
55 static inline u32
isp3_param_read_direct(struct rkisp_isp_params_vdev * params_vdev,u32 addr)56 isp3_param_read_direct(struct rkisp_isp_params_vdev *params_vdev, u32 addr)
57 {
58 return rkisp_read(params_vdev->dev, addr, true);
59 }
60
61 static inline u32
isp3_param_read(struct rkisp_isp_params_vdev * params_vdev,u32 addr)62 isp3_param_read(struct rkisp_isp_params_vdev *params_vdev, u32 addr)
63 {
64 return rkisp_read(params_vdev->dev, addr, false);
65 }
66
67 static inline u32
isp3_param_read_cache(struct rkisp_isp_params_vdev * params_vdev,u32 addr)68 isp3_param_read_cache(struct rkisp_isp_params_vdev *params_vdev, u32 addr)
69 {
70 return rkisp_read_reg_cache(params_vdev->dev, addr);
71 }
72
73 static inline void
isp3_param_set_bits(struct rkisp_isp_params_vdev * params_vdev,u32 reg,u32 bit_mask)74 isp3_param_set_bits(struct rkisp_isp_params_vdev *params_vdev,
75 u32 reg, u32 bit_mask)
76 {
77 rkisp_set_bits(params_vdev->dev, reg, 0, bit_mask, false);
78 }
79
80 static inline void
isp3_param_clear_bits(struct rkisp_isp_params_vdev * params_vdev,u32 reg,u32 bit_mask)81 isp3_param_clear_bits(struct rkisp_isp_params_vdev *params_vdev,
82 u32 reg, u32 bit_mask)
83 {
84 rkisp_clear_bits(params_vdev->dev, reg, bit_mask, false);
85 }
86
87 static void
isp_dpcc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_dpcc_cfg * arg)88 isp_dpcc_config(struct rkisp_isp_params_vdev *params_vdev,
89 const struct isp2x_dpcc_cfg *arg)
90 {
91 u32 value;
92 int i;
93
94 value = isp3_param_read(params_vdev, ISP3X_DPCC0_MODE);
95 value &= ISP_DPCC_EN;
96
97 value |= !!arg->stage1_enable << 2 |
98 !!arg->grayscale_mode << 1;
99 isp3_param_write(params_vdev, value, ISP3X_DPCC0_MODE);
100 isp3_param_write(params_vdev, value, ISP3X_DPCC1_MODE);
101
102 value = (arg->sw_rk_out_sel & 0x03) << 5 |
103 !!arg->sw_dpcc_output_sel << 4 |
104 !!arg->stage1_rb_3x3 << 3 |
105 !!arg->stage1_g_3x3 << 2 |
106 !!arg->stage1_incl_rb_center << 1 |
107 !!arg->stage1_incl_green_center;
108 isp3_param_write(params_vdev, value, ISP3X_DPCC0_OUTPUT_MODE);
109 isp3_param_write(params_vdev, value, ISP3X_DPCC1_OUTPUT_MODE);
110
111 value = !!arg->stage1_use_fix_set << 3 |
112 !!arg->stage1_use_set_3 << 2 |
113 !!arg->stage1_use_set_2 << 1 |
114 !!arg->stage1_use_set_1;
115 isp3_param_write(params_vdev, value, ISP3X_DPCC0_SET_USE);
116 isp3_param_write(params_vdev, value, ISP3X_DPCC1_SET_USE);
117
118 value = !!arg->sw_rk_red_blue1_en << 13 |
119 !!arg->rg_red_blue1_enable << 12 |
120 !!arg->rnd_red_blue1_enable << 11 |
121 !!arg->ro_red_blue1_enable << 10 |
122 !!arg->lc_red_blue1_enable << 9 |
123 !!arg->pg_red_blue1_enable << 8 |
124 !!arg->sw_rk_green1_en << 5 |
125 !!arg->rg_green1_enable << 4 |
126 !!arg->rnd_green1_enable << 3 |
127 !!arg->ro_green1_enable << 2 |
128 !!arg->lc_green1_enable << 1 |
129 !!arg->pg_green1_enable;
130 isp3_param_write(params_vdev, value, ISP3X_DPCC0_METHODS_SET_1);
131 isp3_param_write(params_vdev, value, ISP3X_DPCC1_METHODS_SET_1);
132
133 value = !!arg->sw_rk_red_blue2_en << 13 |
134 !!arg->rg_red_blue2_enable << 12 |
135 !!arg->rnd_red_blue2_enable << 11 |
136 !!arg->ro_red_blue2_enable << 10 |
137 !!arg->lc_red_blue2_enable << 9 |
138 !!arg->pg_red_blue2_enable << 8 |
139 !!arg->sw_rk_green2_en << 5 |
140 !!arg->rg_green2_enable << 4 |
141 !!arg->rnd_green2_enable << 3 |
142 !!arg->ro_green2_enable << 2 |
143 !!arg->lc_green2_enable << 1 |
144 !!arg->pg_green2_enable;
145 isp3_param_write(params_vdev, value, ISP3X_DPCC0_METHODS_SET_2);
146 isp3_param_write(params_vdev, value, ISP3X_DPCC1_METHODS_SET_2);
147
148 value = !!arg->sw_rk_red_blue3_en << 13 |
149 !!arg->rg_red_blue3_enable << 12 |
150 !!arg->rnd_red_blue3_enable << 11 |
151 !!arg->ro_red_blue3_enable << 10 |
152 !!arg->lc_red_blue3_enable << 9 |
153 !!arg->pg_red_blue3_enable << 8 |
154 !!arg->sw_rk_green3_en << 5 |
155 !!arg->rg_green3_enable << 4 |
156 !!arg->rnd_green3_enable << 3 |
157 !!arg->ro_green3_enable << 2 |
158 !!arg->lc_green3_enable << 1 |
159 !!arg->pg_green3_enable;
160 isp3_param_write(params_vdev, value, ISP3X_DPCC0_METHODS_SET_3);
161 isp3_param_write(params_vdev, value, ISP3X_DPCC1_METHODS_SET_3);
162
163 value = ISP_PACK_4BYTE(arg->line_thr_1_g, arg->line_thr_1_rb,
164 arg->sw_mindis1_g, arg->sw_mindis1_rb);
165 isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_THRESH_1);
166 isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_THRESH_1);
167
168 value = ISP_PACK_4BYTE(arg->line_mad_fac_1_g, arg->line_mad_fac_1_rb,
169 arg->sw_dis_scale_max1, arg->sw_dis_scale_min1);
170 isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_MAD_FAC_1);
171 isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_MAD_FAC_1);
172
173 value = ISP_PACK_4BYTE(arg->pg_fac_1_g, arg->pg_fac_1_rb, 0, 0);
174 isp3_param_write(params_vdev, value, ISP3X_DPCC0_PG_FAC_1);
175 isp3_param_write(params_vdev, value, ISP3X_DPCC1_PG_FAC_1);
176
177 value = ISP_PACK_4BYTE(arg->rnd_thr_1_g, arg->rnd_thr_1_rb, 0, 0);
178 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_THRESH_1);
179 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_THRESH_1);
180
181 value = ISP_PACK_4BYTE(arg->rg_fac_1_g, arg->rg_fac_1_rb, 0, 0);
182 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RG_FAC_1);
183 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RG_FAC_1);
184
185 value = ISP_PACK_4BYTE(arg->line_thr_2_g, arg->line_thr_2_rb,
186 arg->sw_mindis2_g, arg->sw_mindis2_rb);
187 isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_THRESH_2);
188 isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_THRESH_2);
189
190 value = ISP_PACK_4BYTE(arg->line_mad_fac_2_g, arg->line_mad_fac_2_rb,
191 arg->sw_dis_scale_max2, arg->sw_dis_scale_min2);
192 isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_MAD_FAC_2);
193 isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_MAD_FAC_2);
194
195 value = ISP_PACK_4BYTE(arg->pg_fac_2_g, arg->pg_fac_2_rb, 0, 0);
196 isp3_param_write(params_vdev, value, ISP3X_DPCC0_PG_FAC_2);
197 isp3_param_write(params_vdev, value, ISP3X_DPCC1_PG_FAC_2);
198
199 value = ISP_PACK_4BYTE(arg->rnd_thr_2_g, arg->rnd_thr_2_rb, 0, 0);
200 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_THRESH_2);
201 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_THRESH_2);
202
203 value = ISP_PACK_4BYTE(arg->rg_fac_2_g, arg->rg_fac_2_rb, 0, 0);
204 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RG_FAC_2);
205 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RG_FAC_2);
206
207 value = ISP_PACK_4BYTE(arg->line_thr_3_g, arg->line_thr_3_rb,
208 arg->sw_mindis3_g, arg->sw_mindis3_rb);
209 isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_THRESH_3);
210 isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_THRESH_3);
211
212 value = ISP_PACK_4BYTE(arg->line_mad_fac_3_g, arg->line_mad_fac_3_rb,
213 arg->sw_dis_scale_max3, arg->sw_dis_scale_min3);
214 isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_MAD_FAC_3);
215 isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_MAD_FAC_3);
216
217 value = ISP_PACK_4BYTE(arg->pg_fac_3_g, arg->pg_fac_3_rb, 0, 0);
218 isp3_param_write(params_vdev, value, ISP3X_DPCC0_PG_FAC_3);
219 isp3_param_write(params_vdev, value, ISP3X_DPCC1_PG_FAC_3);
220
221 value = ISP_PACK_4BYTE(arg->rnd_thr_3_g, arg->rnd_thr_3_rb, 0, 0);
222 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_THRESH_3);
223 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_THRESH_3);
224
225 value = ISP_PACK_4BYTE(arg->rg_fac_3_g, arg->rg_fac_3_rb, 0, 0);
226 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RG_FAC_3);
227 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RG_FAC_3);
228
229 value = (arg->ro_lim_3_rb & 0x03) << 10 |
230 (arg->ro_lim_3_g & 0x03) << 8 |
231 (arg->ro_lim_2_rb & 0x03) << 6 |
232 (arg->ro_lim_2_g & 0x03) << 4 |
233 (arg->ro_lim_1_rb & 0x03) << 2 |
234 (arg->ro_lim_1_g & 0x03);
235 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RO_LIMITS);
236 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RO_LIMITS);
237
238 value = (arg->rnd_offs_3_rb & 0x03) << 10 |
239 (arg->rnd_offs_3_g & 0x03) << 8 |
240 (arg->rnd_offs_2_rb & 0x03) << 6 |
241 (arg->rnd_offs_2_g & 0x03) << 4 |
242 (arg->rnd_offs_1_rb & 0x03) << 2 |
243 (arg->rnd_offs_1_g & 0x03);
244 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_OFFS);
245 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_OFFS);
246
247 value = !!arg->bpt_rb_3x3 << 11 |
248 !!arg->bpt_g_3x3 << 10 |
249 !!arg->bpt_incl_rb_center << 9 |
250 !!arg->bpt_incl_green_center << 8 |
251 !!arg->bpt_use_fix_set << 7 |
252 !!arg->bpt_use_set_3 << 6 |
253 !!arg->bpt_use_set_2 << 5 |
254 !!arg->bpt_use_set_1 << 4 |
255 !!arg->bpt_cor_en << 1 |
256 !!arg->bpt_det_en;
257 isp3_param_write(params_vdev, value, ISP3X_DPCC0_BPT_CTRL);
258 isp3_param_write(params_vdev, value, ISP3X_DPCC1_BPT_CTRL);
259
260 isp3_param_write(params_vdev, arg->bp_number, ISP3X_DPCC0_BPT_NUMBER);
261 isp3_param_write(params_vdev, arg->bp_number, ISP3X_DPCC1_BPT_NUMBER);
262 isp3_param_write(params_vdev, arg->bp_table_addr, ISP3X_DPCC0_BPT_ADDR);
263 isp3_param_write(params_vdev, arg->bp_table_addr, ISP3X_DPCC1_BPT_ADDR);
264
265 value = ISP_PACK_2SHORT(arg->bpt_h_addr, arg->bpt_v_addr);
266 isp3_param_write(params_vdev, value, ISP3X_DPCC0_BPT_DATA);
267 isp3_param_write(params_vdev, value, ISP3X_DPCC1_BPT_DATA);
268
269 isp3_param_write(params_vdev, arg->bp_cnt, ISP3X_DPCC0_BP_CNT);
270 isp3_param_write(params_vdev, arg->bp_cnt, ISP3X_DPCC1_BP_CNT);
271
272 isp3_param_write(params_vdev, arg->sw_pdaf_en, ISP3X_DPCC0_PDAF_EN);
273 isp3_param_write(params_vdev, arg->sw_pdaf_en, ISP3X_DPCC1_PDAF_EN);
274
275 value = 0;
276 for (i = 0; i < ISP32_DPCC_PDAF_POINT_NUM; i++)
277 value |= !!arg->pdaf_point_en[i] << i;
278 isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_POINT_EN);
279 isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_POINT_EN);
280
281 value = ISP_PACK_2SHORT(arg->pdaf_offsetx, arg->pdaf_offsety);
282 isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_OFFSET);
283 isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_OFFSET);
284
285 value = ISP_PACK_2SHORT(arg->pdaf_wrapx, arg->pdaf_wrapy);
286 isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_WRAP);
287 isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_WRAP);
288
289 value = ISP_PACK_2SHORT(arg->pdaf_wrapx_num, arg->pdaf_wrapy_num);
290 isp3_param_write(params_vdev, value, ISP_DPCC0_PDAF_SCOPE);
291 isp3_param_write(params_vdev, value, ISP_DPCC1_PDAF_SCOPE);
292
293 for (i = 0; i < ISP32_DPCC_PDAF_POINT_NUM / 2; i++) {
294 value = ISP_PACK_4BYTE(arg->point[2 * i].x, arg->point[2 * i].y,
295 arg->point[2 * i + 1].x, arg->point[2 * i + 1].y);
296 isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_POINT_0 + 4 * i);
297 isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_POINT_0 + 4 * i);
298 }
299
300 isp3_param_write(params_vdev, arg->pdaf_forward_med, ISP3X_DPCC0_PDAF_FORWARD_MED);
301 isp3_param_write(params_vdev, arg->pdaf_forward_med, ISP3X_DPCC1_PDAF_FORWARD_MED);
302 }
303
304 static void
isp_dpcc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)305 isp_dpcc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
306 {
307 u32 value;
308
309 value = isp3_param_read(params_vdev, ISP3X_DPCC0_MODE);
310 value &= ~ISP_DPCC_EN;
311
312 if (en)
313 value |= ISP_DPCC_EN;
314 isp3_param_write(params_vdev, value, ISP3X_DPCC0_MODE);
315 isp3_param_write(params_vdev, value, ISP3X_DPCC1_MODE);
316 }
317
318 static void
isp_bls_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp32_bls_cfg * arg)319 isp_bls_config(struct rkisp_isp_params_vdev *params_vdev,
320 const struct isp32_bls_cfg *arg)
321 {
322 const struct isp2x_bls_fixed_val *pval;
323 u32 new_control, value;
324
325 new_control = isp3_param_read(params_vdev, ISP3X_BLS_CTRL);
326 new_control &= (ISP_BLS_ENA | ISP32_BLS_BLS2_EN);
327
328 pval = &arg->bls1_val;
329 if (arg->bls1_en) {
330 new_control |= ISP_BLS_BLS1_EN;
331
332 switch (params_vdev->raw_type) {
333 case RAW_BGGR:
334 isp3_param_write(params_vdev, pval->r, ISP3X_BLS1_D_FIXED);
335 isp3_param_write(params_vdev, pval->gr, ISP3X_BLS1_C_FIXED);
336 isp3_param_write(params_vdev, pval->gb, ISP3X_BLS1_B_FIXED);
337 isp3_param_write(params_vdev, pval->b, ISP3X_BLS1_A_FIXED);
338 break;
339 case RAW_GBRG:
340 isp3_param_write(params_vdev, pval->r, ISP3X_BLS1_C_FIXED);
341 isp3_param_write(params_vdev, pval->gr, ISP3X_BLS1_D_FIXED);
342 isp3_param_write(params_vdev, pval->gb, ISP3X_BLS1_A_FIXED);
343 isp3_param_write(params_vdev, pval->b, ISP3X_BLS1_B_FIXED);
344 break;
345 case RAW_GRBG:
346 isp3_param_write(params_vdev, pval->r, ISP3X_BLS1_B_FIXED);
347 isp3_param_write(params_vdev, pval->gr, ISP3X_BLS1_A_FIXED);
348 isp3_param_write(params_vdev, pval->gb, ISP3X_BLS1_D_FIXED);
349 isp3_param_write(params_vdev, pval->b, ISP3X_BLS1_C_FIXED);
350 break;
351 case RAW_RGGB:
352 default:
353 isp3_param_write(params_vdev, pval->r, ISP3X_BLS1_A_FIXED);
354 isp3_param_write(params_vdev, pval->gr, ISP3X_BLS1_B_FIXED);
355 isp3_param_write(params_vdev, pval->gb, ISP3X_BLS1_C_FIXED);
356 isp3_param_write(params_vdev, pval->b, ISP3X_BLS1_D_FIXED);
357 break;
358 }
359 }
360
361 /* fixed subtraction values */
362 pval = &arg->fixed_val;
363 if (!arg->enable_auto) {
364 switch (params_vdev->raw_type) {
365 case RAW_BGGR:
366 isp3_param_write(params_vdev, pval->r, ISP3X_BLS_D_FIXED);
367 isp3_param_write(params_vdev, pval->gr, ISP3X_BLS_C_FIXED);
368 isp3_param_write(params_vdev, pval->gb, ISP3X_BLS_B_FIXED);
369 isp3_param_write(params_vdev, pval->b, ISP3X_BLS_A_FIXED);
370 break;
371 case RAW_GBRG:
372 isp3_param_write(params_vdev, pval->r, ISP3X_BLS_C_FIXED);
373 isp3_param_write(params_vdev, pval->gr, ISP3X_BLS_D_FIXED);
374 isp3_param_write(params_vdev, pval->gb, ISP3X_BLS_A_FIXED);
375 isp3_param_write(params_vdev, pval->b, ISP3X_BLS_B_FIXED);
376 break;
377 case RAW_GRBG:
378 isp3_param_write(params_vdev, pval->r, ISP3X_BLS_B_FIXED);
379 isp3_param_write(params_vdev, pval->gr, ISP3X_BLS_A_FIXED);
380 isp3_param_write(params_vdev, pval->gb, ISP3X_BLS_D_FIXED);
381 isp3_param_write(params_vdev, pval->b, ISP3X_BLS_C_FIXED);
382 break;
383 case RAW_RGGB:
384 default:
385 isp3_param_write(params_vdev, pval->r, ISP3X_BLS_A_FIXED);
386 isp3_param_write(params_vdev, pval->gr, ISP3X_BLS_B_FIXED);
387 isp3_param_write(params_vdev, pval->gb, ISP3X_BLS_C_FIXED);
388 isp3_param_write(params_vdev, pval->b, ISP3X_BLS_D_FIXED);
389 break;
390 }
391 } else {
392 if (arg->en_windows & BIT(1)) {
393 isp3_param_write(params_vdev, arg->bls_window2.h_offs, ISP3X_BLS_H2_START);
394 value = arg->bls_window2.h_offs + arg->bls_window2.h_size;
395 isp3_param_write(params_vdev, value, ISP3X_BLS_H2_STOP);
396 isp3_param_write(params_vdev, arg->bls_window2.v_offs, ISP3X_BLS_V2_START);
397 value = arg->bls_window2.v_offs + arg->bls_window2.v_size;
398 isp3_param_write(params_vdev, value, ISP3X_BLS_V2_STOP);
399 new_control |= ISP_BLS_WINDOW_2;
400 }
401
402 if (arg->en_windows & BIT(0)) {
403 isp3_param_write(params_vdev, arg->bls_window1.h_offs, ISP3X_BLS_H1_START);
404 value = arg->bls_window1.h_offs + arg->bls_window1.h_size;
405 isp3_param_write(params_vdev, value, ISP3X_BLS_H1_STOP);
406 isp3_param_write(params_vdev, arg->bls_window1.v_offs, ISP3X_BLS_V1_START);
407 value = arg->bls_window1.v_offs + arg->bls_window1.v_size;
408 isp3_param_write(params_vdev, value, ISP3X_BLS_V1_STOP);
409 new_control |= ISP_BLS_WINDOW_1;
410 }
411
412 isp3_param_write(params_vdev, arg->bls_samples, ISP3X_BLS_SAMPLES);
413
414 new_control |= ISP_BLS_MODE_MEASURED;
415 }
416 isp3_param_write(params_vdev, new_control, ISP3X_BLS_CTRL);
417
418 isp3_param_write(params_vdev, arg->isp_ob_offset, ISP32_BLS_ISP_OB_OFFSET);
419 isp3_param_write(params_vdev, arg->isp_ob_predgain, ISP32_BLS_ISP_OB_PREDGAIN);
420 isp3_param_write(params_vdev, arg->isp_ob_max, ISP32_BLS_ISP_OB_MAX);
421 }
422
423 static void
isp_bls_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)424 isp_bls_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
425 {
426 u32 new_control;
427
428 new_control = isp3_param_read(params_vdev, ISP3X_BLS_CTRL);
429 if (en)
430 new_control |= ISP_BLS_ENA;
431 else
432 new_control &= ~ISP_BLS_ENA;
433 isp3_param_write(params_vdev, new_control, ISP3X_BLS_CTRL);
434 }
435
436 static void
isp_sdg_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_sdg_cfg * arg)437 isp_sdg_config(struct rkisp_isp_params_vdev *params_vdev,
438 const struct isp2x_sdg_cfg *arg)
439 {
440 int i;
441
442 isp3_param_write(params_vdev, arg->xa_pnts.gamma_dx0, ISP3X_ISP_GAMMA_DX_LO);
443 isp3_param_write(params_vdev, arg->xa_pnts.gamma_dx1, ISP3X_ISP_GAMMA_DX_HI);
444
445 for (i = 0; i < ISP32_DEGAMMA_CURVE_SIZE; i++) {
446 isp3_param_write(params_vdev, arg->curve_r.gamma_y[i],
447 ISP3X_ISP_GAMMA_R_Y_0 + i * 4);
448 isp3_param_write(params_vdev, arg->curve_g.gamma_y[i],
449 ISP3X_ISP_GAMMA_G_Y_0 + i * 4);
450 isp3_param_write(params_vdev, arg->curve_b.gamma_y[i],
451 ISP3X_ISP_GAMMA_B_Y_0 + i * 4);
452 }
453 }
454
455 static void
isp_sdg_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)456 isp_sdg_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
457 {
458 u32 val;
459
460 val = isp3_param_read_cache(params_vdev, ISP3X_ISP_CTRL0);
461 if (en)
462 isp3_param_write(params_vdev, val | CIF_ISP_CTRL_ISP_GAMMA_IN_ENA,
463 ISP3X_ISP_CTRL0);
464 else
465 isp3_param_write(params_vdev, val & ~CIF_ISP_CTRL_ISP_GAMMA_IN_ENA,
466 ISP3X_ISP_CTRL0);
467 }
468
469 static void __maybe_unused
isp_lsc_matrix_cfg_ddr(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_lsc_cfg * pconfig)470 isp_lsc_matrix_cfg_ddr(struct rkisp_isp_params_vdev *params_vdev,
471 const struct isp3x_lsc_cfg *pconfig)
472 {
473 struct rkisp_isp_params_val_v32 *priv_val;
474 u32 data, buf_idx, *vaddr[4], index[4];
475 void *buf_vaddr;
476 int i, j;
477
478 memset(&index[0], 0, sizeof(index));
479 priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val;
480 buf_idx = (priv_val->buf_lsclut_idx++) % ISP32_LSC_LUT_BUF_NUM;
481 buf_vaddr = priv_val->buf_lsclut[buf_idx].vaddr;
482
483 vaddr[0] = buf_vaddr;
484 vaddr[1] = buf_vaddr + ISP32_LSC_LUT_TBL_SIZE;
485 vaddr[2] = buf_vaddr + ISP32_LSC_LUT_TBL_SIZE * 2;
486 vaddr[3] = buf_vaddr + ISP32_LSC_LUT_TBL_SIZE * 3;
487
488 /* program data tables (table size is 9 * 17 = 153) */
489 for (i = 0; i < CIF_ISP_LSC_SECTORS_MAX * CIF_ISP_LSC_SECTORS_MAX;
490 i += CIF_ISP_LSC_SECTORS_MAX) {
491 /*
492 * 17 sectors with 2 values in one DWORD = 9
493 * DWORDs (2nd value of last DWORD unused)
494 */
495 for (j = 0; j < CIF_ISP_LSC_SECTORS_MAX - 1; j += 2) {
496 data = ISP_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i + j],
497 pconfig->r_data_tbl[i + j + 1]);
498 vaddr[0][index[0]++] = data;
499
500 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i + j],
501 pconfig->gr_data_tbl[i + j + 1]);
502 vaddr[1][index[1]++] = data;
503
504 data = ISP_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i + j],
505 pconfig->b_data_tbl[i + j + 1]);
506 vaddr[2][index[2]++] = data;
507
508 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i + j],
509 pconfig->gb_data_tbl[i + j + 1]);
510 vaddr[3][index[3]++] = data;
511 }
512
513 data = ISP_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i + j], 0);
514 vaddr[0][index[0]++] = data;
515
516 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i + j], 0);
517 vaddr[1][index[1]++] = data;
518
519 data = ISP_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i + j], 0);
520 vaddr[2][index[2]++] = data;
521
522 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i + j], 0);
523 vaddr[3][index[3]++] = data;
524 }
525 rkisp_prepare_buffer(params_vdev->dev, &priv_val->buf_lsclut[buf_idx]);
526 data = priv_val->buf_lsclut[buf_idx].dma_addr;
527 isp3_param_write(params_vdev, data, ISP3X_MI_LUT_LSC_RD_BASE);
528 isp3_param_write(params_vdev, ISP32_LSC_LUT_TBL_SIZE, ISP3X_MI_LUT_LSC_RD_WSIZE);
529 }
530
531 static void
isp_lsc_matrix_cfg_sram(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_lsc_cfg * pconfig,bool is_check)532 isp_lsc_matrix_cfg_sram(struct rkisp_isp_params_vdev *params_vdev,
533 const struct isp3x_lsc_cfg *pconfig,
534 bool is_check)
535 {
536 struct rkisp_device *dev = params_vdev->dev;
537 u32 sram_addr, data, table;
538 int i, j;
539
540 if (is_check &&
541 !(isp3_param_read(params_vdev, ISP3X_LSC_CTRL) & ISP_LSC_EN))
542 return;
543
544 table = isp3_param_read_direct(params_vdev, ISP3X_LSC_STATUS);
545 table &= ISP3X_LSC_ACTIVE_TABLE;
546 /* default table 0 for multi device */
547 if (!dev->hw_dev->is_single || dev->isp_ver == ISP_V32_L)
548 table = ISP3X_LSC_ACTIVE_TABLE;
549
550 /* CIF_ISP_LSC_TABLE_ADDRESS_153 = ( 17 * 18 ) >> 1 */
551 sram_addr = table ? ISP3X_LSC_TABLE_ADDRESS_0 : CIF_ISP_LSC_TABLE_ADDRESS_153;
552 isp3_param_write_direct(params_vdev, sram_addr, ISP3X_LSC_R_TABLE_ADDR);
553 isp3_param_write_direct(params_vdev, sram_addr, ISP3X_LSC_GR_TABLE_ADDR);
554 isp3_param_write_direct(params_vdev, sram_addr, ISP3X_LSC_GB_TABLE_ADDR);
555 isp3_param_write_direct(params_vdev, sram_addr, ISP3X_LSC_B_TABLE_ADDR);
556
557 /* program data tables (table size is 9 * 17 = 153) */
558 for (i = 0; i < CIF_ISP_LSC_SECTORS_MAX * CIF_ISP_LSC_SECTORS_MAX;
559 i += CIF_ISP_LSC_SECTORS_MAX) {
560 /*
561 * 17 sectors with 2 values in one DWORD = 9
562 * DWORDs (2nd value of last DWORD unused)
563 */
564 for (j = 0; j < CIF_ISP_LSC_SECTORS_MAX - 1; j += 2) {
565 data = ISP_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i + j],
566 pconfig->r_data_tbl[i + j + 1]);
567 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_R_TABLE_DATA);
568
569 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i + j],
570 pconfig->gr_data_tbl[i + j + 1]);
571 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_GR_TABLE_DATA);
572
573 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i + j],
574 pconfig->gb_data_tbl[i + j + 1]);
575 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_GB_TABLE_DATA);
576
577 data = ISP_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i + j],
578 pconfig->b_data_tbl[i + j + 1]);
579 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_B_TABLE_DATA);
580 }
581
582 data = ISP_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i + j], 0);
583 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_R_TABLE_DATA);
584
585 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i + j], 0);
586 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_GR_TABLE_DATA);
587
588 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i + j], 0);
589 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_GB_TABLE_DATA);
590
591 data = ISP_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i + j], 0);
592 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_B_TABLE_DATA);
593 }
594 isp3_param_write_direct(params_vdev, !table, ISP3X_LSC_TABLE_SEL);
595 }
596
597 static void
isp_lsc_cfg_sram_task(unsigned long data)598 isp_lsc_cfg_sram_task(unsigned long data)
599 {
600 struct rkisp_isp_params_vdev *params_vdev =
601 (struct rkisp_isp_params_vdev *)data;
602 struct isp32_isp_params_cfg *params = params_vdev->isp32_params;
603
604 isp_lsc_matrix_cfg_sram(params_vdev, ¶ms->others.lsc_cfg, true);
605 }
606
607 static void
isp_lsc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_lsc_cfg * arg)608 isp_lsc_config(struct rkisp_isp_params_vdev *params_vdev,
609 const struct isp3x_lsc_cfg *arg)
610 {
611 struct rkisp_isp_params_val_v32 *priv_val =
612 (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val;
613 struct isp32_isp_params_cfg *params_rec = params_vdev->isp32_params;
614 struct rkisp_device *dev = params_vdev->dev;
615 u32 data, lsc_ctrl;
616 int i;
617
618 lsc_ctrl = isp3_param_read(params_vdev, ISP3X_LSC_CTRL);
619 if (dev->isp_ver == ISP_V32_L) {
620 /* one lsc sram table
621 * online mode lsc lut load from ddr quick for some sensor VB short
622 * readback mode lsc lut AHB config to sram, once for single device,
623 * need record to switch for multi-device.
624 */
625 if (!IS_HDR_RDBK(dev->rd_mode))
626 isp_lsc_matrix_cfg_ddr(params_vdev, arg);
627 else if (dev->hw_dev->is_single)
628 isp_lsc_matrix_cfg_sram(params_vdev, arg, false);
629 else
630 params_rec->others.lsc_cfg = *arg;
631 } else {
632 /* two lsc sram table */
633 params_rec->others.lsc_cfg = *arg;
634 if (dev->hw_dev->is_single && (lsc_ctrl & ISP_LSC_EN))
635 tasklet_schedule(&priv_val->lsc_tasklet);
636 }
637 for (i = 0; i < ISP32_LSC_SIZE_TBL_SIZE / 4; i++) {
638 /* program x size tables */
639 data = CIF_ISP_LSC_SECT_SIZE(arg->x_size_tbl[i * 2], arg->x_size_tbl[i * 2 + 1]);
640 isp3_param_write(params_vdev, data, ISP3X_LSC_XSIZE_01 + i * 4);
641 data = CIF_ISP_LSC_SECT_SIZE(arg->x_size_tbl[i * 2 + 8], arg->x_size_tbl[i * 2 + 9]);
642 isp3_param_write(params_vdev, data, ISP3X_LSC_XSIZE_89 + i * 4);
643
644 /* program x grad tables */
645 data = CIF_ISP_LSC_SECT_SIZE(arg->x_grad_tbl[i * 2], arg->x_grad_tbl[i * 2 + 1]);
646 isp3_param_write(params_vdev, data, ISP3X_LSC_XGRAD_01 + i * 4);
647 data = CIF_ISP_LSC_SECT_SIZE(arg->x_grad_tbl[i * 2 + 8], arg->x_grad_tbl[i * 2 + 9]);
648 isp3_param_write(params_vdev, data, ISP3X_LSC_XGRAD_89 + i * 4);
649
650 /* program y size tables */
651 data = CIF_ISP_LSC_SECT_SIZE(arg->y_size_tbl[i * 2], arg->y_size_tbl[i * 2 + 1]);
652 isp3_param_write(params_vdev, data, ISP3X_LSC_YSIZE_01 + i * 4);
653 data = CIF_ISP_LSC_SECT_SIZE(arg->y_size_tbl[i * 2 + 8], arg->y_size_tbl[i * 2 + 9]);
654 isp3_param_write(params_vdev, data, ISP3X_LSC_YSIZE_89 + i * 4);
655
656 /* program y grad tables */
657 data = CIF_ISP_LSC_SECT_SIZE(arg->y_grad_tbl[i * 2], arg->y_grad_tbl[i * 2 + 1]);
658 isp3_param_write(params_vdev, data, ISP3X_LSC_YGRAD_01 + i * 4);
659 data = CIF_ISP_LSC_SECT_SIZE(arg->y_grad_tbl[i * 2 + 8], arg->y_grad_tbl[i * 2 + 9]);
660 isp3_param_write(params_vdev, data, ISP3X_LSC_YGRAD_89 + i * 4);
661 }
662
663 if (arg->sector_16x16)
664 lsc_ctrl |= ISP3X_LSC_SECTOR_16X16;
665 else
666 lsc_ctrl &= ~ISP3X_LSC_SECTOR_16X16;
667 if (dev->isp_ver == ISP_V32_L && !IS_HDR_RDBK(dev->rd_mode))
668 lsc_ctrl |= ISP3X_LSC_LUT_EN;
669 isp3_param_write(params_vdev, lsc_ctrl, ISP3X_LSC_CTRL);
670 }
671
672 static void
isp_lsc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)673 isp_lsc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
674 {
675 struct rkisp_device *dev = params_vdev->dev;
676 struct isp32_isp_params_cfg *params_rec = params_vdev->isp32_params;
677 u32 val = isp3_param_read(params_vdev, ISP3X_LSC_CTRL);
678
679 if (en == !!(val & ISP_LSC_EN))
680 return;
681
682 if (en) {
683 val = ISP_LSC_EN | ISP32_SELF_FORCE_UPD;
684 if (dev->isp_ver == ISP_V32_L && !IS_HDR_RDBK(dev->rd_mode))
685 val |= ISP3X_LSC_LUT_EN;
686 isp3_param_set_bits(params_vdev, ISP3X_LSC_CTRL, val);
687 if (dev->isp_ver == ISP_V32 && params_vdev->dev->hw_dev->is_single)
688 isp_lsc_matrix_cfg_sram(params_vdev,
689 ¶ms_rec->others.lsc_cfg, false);
690 } else {
691 isp3_param_clear_bits(params_vdev, ISP3X_LSC_CTRL, ISP_LSC_EN);
692 isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(8));
693 }
694 }
695
696 static void
isp_debayer_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp32_debayer_cfg * arg)697 isp_debayer_config(struct rkisp_isp_params_vdev *params_vdev,
698 const struct isp32_debayer_cfg *arg)
699 {
700 u32 value;
701
702 value = isp3_param_read(params_vdev, ISP3X_DEBAYER_CONTROL);
703 value &= ISP_DEBAYER_EN;
704
705 value |= !!arg->filter_g_en << 4;
706 if (params_vdev->dev->isp_ver == ISP_V32)
707 value |= !!arg->filter_c_en << 8;
708 isp3_param_write(params_vdev, value, ISP3X_DEBAYER_CONTROL);
709
710 value = (arg->max_ratio & 0x3F) << 24 | arg->select_thed << 16 |
711 (arg->thed1 & 0x0F) << 12 | (arg->thed0 & 0x0F) << 8 |
712 (arg->dist_scale & 0x0F) << 4 | !!arg->clip_en;
713 isp3_param_write(params_vdev, value, ISP3X_DEBAYER_G_INTERP);
714
715 value = (arg->filter1_coe4 & 0x1F) << 24 | (arg->filter1_coe3 & 0x1F) << 16 |
716 (arg->filter1_coe2 & 0x1F) << 8 | (arg->filter1_coe1 & 0x1F);
717 isp3_param_write(params_vdev, value, ISP3X_DEBAYER_G_INTERP_FILTER1);
718
719 value = (arg->filter2_coe4 & 0x1F) << 24 | (arg->filter2_coe3 & 0x1F) << 16 |
720 (arg->filter2_coe2 & 0x1F) << 8 | (arg->filter2_coe1 & 0x1F);
721 isp3_param_write(params_vdev, value, ISP3X_DEBAYER_G_INTERP_FILTER2);
722
723 value = arg->hf_offset << 16 | (arg->gain_offset & 0xFFF);
724 isp3_param_write(params_vdev, value, ISP32_DEBAYER_G_INTERP_OFFSET);
725
726 value = (arg->offset & 0x7FF);
727 isp3_param_write(params_vdev, value, ISP32_DEBAYER_G_FILTER_OFFSET);
728
729 if (params_vdev->dev->isp_ver != ISP_V32)
730 return;
731
732 value = arg->guid_gaus_coe2 << 16 |
733 arg->guid_gaus_coe1 << 8 | arg->guid_gaus_coe0;
734 isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_GUIDE_GAUS);
735
736 value = arg->ce_gaus_coe2 << 16 |
737 arg->ce_gaus_coe1 << 8 | arg->ce_gaus_coe0;
738 isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_CE_GAUS);
739
740 value = arg->alpha_gaus_coe2 << 16 |
741 arg->alpha_gaus_coe1 << 8 | arg->alpha_gaus_coe0;
742 isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_ALPHA_GAUS);
743
744 value = (arg->loggd_offset & 0xfff) << 16 | (arg->loghf_offset & 0x1fff);
745 isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_LOG_OFFSET);
746
747 value = (arg->alpha_scale & 0xfffff) << 12 | (arg->alpha_offset & 0xfff);
748 isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_ALPHA);
749
750 value = (arg->edge_scale & 0xfffff) << 12 | (arg->edge_offset & 0xfff);
751 isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_EDGE);
752
753 value = (arg->wgtslope & 0xfff) << 16 |
754 (arg->exp_shift & 0x3f) << 8 | arg->ce_sgm;
755 isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_IIR_0);
756
757 value = (arg->wet_ghost & 0x3f) << 8 | (arg->wet_clip & 0x7f);
758 isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_IIR_1);
759
760 value = (arg->bf_curwgt & 0x7f) << 24 |
761 (arg->bf_clip & 0x7f) << 16 | arg->bf_sgm;
762 isp3_param_write(params_vdev, value, ISP32_DEBAYER_C_FILTER_BF);
763 }
764
765 static void
isp_debayer_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)766 isp_debayer_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
767 {
768 if (en)
769 isp3_param_set_bits(params_vdev,
770 ISP3X_DEBAYER_CONTROL, ISP32_MODULE_EN);
771 else
772 isp3_param_clear_bits(params_vdev,
773 ISP3X_DEBAYER_CONTROL, ISP32_MODULE_EN);
774 }
775
776 static void
isp_awbgain_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp32_awb_gain_cfg * arg)777 isp_awbgain_config(struct rkisp_isp_params_vdev *params_vdev,
778 const struct isp32_awb_gain_cfg *arg)
779 {
780 struct rkisp_device *dev = params_vdev->dev;
781
782 if (!arg->gain0_red || !arg->gain0_blue ||
783 !arg->gain1_red || !arg->gain1_blue ||
784 !arg->gain2_red || !arg->gain2_blue ||
785 !arg->gain0_green_r || !arg->gain0_green_b ||
786 !arg->gain1_green_r || !arg->gain1_green_b ||
787 !arg->gain2_green_r || !arg->gain2_green_b) {
788 dev_err(dev->dev, "awb gain is zero!\n");
789 return;
790 }
791
792 isp3_param_write(params_vdev,
793 ISP_PACK_2SHORT(arg->gain0_green_b, arg->gain0_green_r),
794 ISP3X_ISP_AWB_GAIN0_G);
795 isp3_param_write(params_vdev,
796 ISP_PACK_2SHORT(arg->gain0_blue, arg->gain0_red),
797 ISP3X_ISP_AWB_GAIN0_RB);
798
799 isp3_param_write(params_vdev,
800 ISP_PACK_2SHORT(arg->gain1_green_b, arg->gain1_green_r),
801 ISP3X_ISP_AWB_GAIN1_G);
802 isp3_param_write(params_vdev,
803 ISP_PACK_2SHORT(arg->gain1_blue, arg->gain1_red),
804 ISP3X_ISP_AWB_GAIN1_RB);
805
806 isp3_param_write(params_vdev,
807 ISP_PACK_2SHORT(arg->gain2_green_b, arg->gain2_green_r),
808 ISP3X_ISP_AWB_GAIN2_G);
809 isp3_param_write(params_vdev,
810 ISP_PACK_2SHORT(arg->gain2_blue, arg->gain2_red),
811 ISP3X_ISP_AWB_GAIN2_RB);
812
813 isp3_param_write(params_vdev,
814 ISP_PACK_2SHORT(arg->awb1_gain_gb, arg->awb1_gain_gr),
815 ISP32_ISP_AWB1_GAIN_G);
816 isp3_param_write(params_vdev,
817 ISP_PACK_2SHORT(arg->awb1_gain_b, arg->awb1_gain_r),
818 ISP32_ISP_AWB1_GAIN_RB);
819 }
820
821 static void
isp_awbgain_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)822 isp_awbgain_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
823 {
824 u32 val;
825
826 val = isp3_param_read_cache(params_vdev, ISP3X_ISP_CTRL0);
827 if (en)
828 isp3_param_write(params_vdev, val | CIF_ISP_CTRL_ISP_AWB_ENA,
829 ISP3X_ISP_CTRL0);
830 else
831 isp3_param_write(params_vdev, val & ~CIF_ISP_CTRL_ISP_AWB_ENA,
832 ISP3X_ISP_CTRL0);
833 }
834
835 static void
isp_ccm_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp32_ccm_cfg * arg)836 isp_ccm_config(struct rkisp_isp_params_vdev *params_vdev,
837 const struct isp32_ccm_cfg *arg)
838 {
839 u32 value;
840 u32 i;
841
842 value = isp3_param_read(params_vdev, ISP3X_CCM_CTRL);
843 value &= ISP_CCM_EN;
844
845 value |= !!arg->asym_adj_en << 3 |
846 !!arg->enh_adj_en << 2 |
847 !!arg->highy_adjust_dis << 1;
848 isp3_param_write(params_vdev, value, ISP3X_CCM_CTRL);
849
850 value = ISP_PACK_2SHORT(arg->coeff0_r, arg->coeff1_r);
851 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_R);
852
853 value = ISP_PACK_2SHORT(arg->coeff2_r, arg->offset_r);
854 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_R);
855
856 value = ISP_PACK_2SHORT(arg->coeff0_g, arg->coeff1_g);
857 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_G);
858
859 value = ISP_PACK_2SHORT(arg->coeff2_g, arg->offset_g);
860 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_G);
861
862 value = ISP_PACK_2SHORT(arg->coeff0_b, arg->coeff1_b);
863 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_B);
864
865 value = ISP_PACK_2SHORT(arg->coeff2_b, arg->offset_b);
866 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_B);
867
868 value = ISP_PACK_2SHORT(arg->coeff0_y, arg->coeff1_y);
869 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_Y);
870
871 value = ISP_PACK_2SHORT(arg->coeff2_y, 0);
872 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_Y);
873
874 for (i = 0; i < ISP32_CCM_CURVE_NUM / 2; i++) {
875 value = ISP_PACK_2SHORT(arg->alp_y[2 * i], arg->alp_y[2 * i + 1]);
876 isp3_param_write(params_vdev, value, ISP3X_CCM_ALP_Y0 + 4 * i);
877 }
878
879 value = (arg->right_bit & 0xf) << 4 | (arg->bound_bit & 0xf);
880 isp3_param_write(params_vdev, value, ISP3X_CCM_BOUND_BIT);
881
882 value = (arg->color_coef1_g2y & 0x7ff) << 16 |
883 (arg->color_coef0_r2y & 0x7ff);
884 isp3_param_write(params_vdev, value, ISP32_CCM_ENHANCE0);
885
886 value = (arg->color_enh_rat_max & 0x3fff) << 16 |
887 (arg->color_coef2_b2y & 0x7ff);
888 isp3_param_write(params_vdev, value, ISP32_CCM_ENHANCE1);
889 }
890
891 static void
isp_ccm_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)892 isp_ccm_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
893 {
894 if (en)
895 isp3_param_set_bits(params_vdev, ISP3X_CCM_CTRL, ISP_CCM_EN);
896 else
897 isp3_param_clear_bits(params_vdev, ISP3X_CCM_CTRL, ISP_CCM_EN);
898 }
899
900 static void
isp_goc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_gammaout_cfg * arg)901 isp_goc_config(struct rkisp_isp_params_vdev *params_vdev,
902 const struct isp3x_gammaout_cfg *arg)
903 {
904 int i;
905 u32 value;
906
907 value = isp3_param_read(params_vdev, ISP3X_GAMMA_OUT_CTRL);
908 value &= ISP3X_GAMMA_OUT_EN;
909 value |= !!arg->equ_segm << 1 | !!arg->finalx4_dense_en << 2;
910 isp3_param_write(params_vdev, value, ISP3X_GAMMA_OUT_CTRL);
911
912 isp3_param_write(params_vdev, arg->offset, ISP3X_GAMMA_OUT_OFFSET);
913 for (i = 0; i < ISP32_GAMMA_OUT_MAX_SAMPLES / 2; i++) {
914 value = ISP_PACK_2SHORT(arg->gamma_y[2 * i],
915 arg->gamma_y[2 * i + 1]);
916 isp3_param_write(params_vdev, value, ISP3X_GAMMA_OUT_Y0 + i * 4);
917 }
918 isp3_param_write(params_vdev, arg->gamma_y[2 * i], ISP3X_GAMMA_OUT_Y0 + i * 4);
919 }
920
921 static void
isp_goc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)922 isp_goc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
923 {
924 if (en)
925 isp3_param_set_bits(params_vdev, ISP3X_GAMMA_OUT_CTRL, ISP3X_GAMMA_OUT_EN);
926 else
927 isp3_param_clear_bits(params_vdev, ISP3X_GAMMA_OUT_CTRL, ISP3X_GAMMA_OUT_EN);
928 }
929
930 static void
isp_cproc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_cproc_cfg * arg)931 isp_cproc_config(struct rkisp_isp_params_vdev *params_vdev,
932 const struct isp2x_cproc_cfg *arg)
933 {
934 u32 quantization = params_vdev->quantization;
935
936 isp3_param_write(params_vdev, arg->contrast, ISP3X_CPROC_CONTRAST);
937 isp3_param_write(params_vdev, arg->hue, ISP3X_CPROC_HUE);
938 isp3_param_write(params_vdev, arg->sat, ISP3X_CPROC_SATURATION);
939 isp3_param_write(params_vdev, arg->brightness, ISP3X_CPROC_BRIGHTNESS);
940
941 if (quantization != V4L2_QUANTIZATION_FULL_RANGE) {
942 isp3_param_clear_bits(params_vdev, ISP3X_CPROC_CTRL,
943 CIF_C_PROC_YOUT_FULL |
944 CIF_C_PROC_YIN_FULL |
945 CIF_C_PROC_COUT_FULL);
946 } else {
947 isp3_param_set_bits(params_vdev, ISP3X_CPROC_CTRL,
948 CIF_C_PROC_YOUT_FULL |
949 CIF_C_PROC_YIN_FULL |
950 CIF_C_PROC_COUT_FULL);
951 }
952 }
953
954 static void
isp_cproc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)955 isp_cproc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
956 {
957 if (en)
958 isp3_param_set_bits(params_vdev, ISP3X_CPROC_CTRL,
959 CIF_C_PROC_CTR_ENABLE);
960 else
961 isp3_param_clear_bits(params_vdev, ISP3X_CPROC_CTRL,
962 CIF_C_PROC_CTR_ENABLE);
963 }
964
965 static void
isp_ie_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_ie_cfg * arg)966 isp_ie_config(struct rkisp_isp_params_vdev *params_vdev,
967 const struct isp2x_ie_cfg *arg)
968 {
969 u32 eff_ctrl;
970
971 eff_ctrl = isp3_param_read(params_vdev, ISP3X_IMG_EFF_CTRL);
972 eff_ctrl &= ~CIF_IMG_EFF_CTRL_MODE_MASK;
973
974 if (params_vdev->quantization == V4L2_QUANTIZATION_FULL_RANGE)
975 eff_ctrl |= CIF_IMG_EFF_CTRL_YCBCR_FULL;
976
977 switch (arg->effect) {
978 case V4L2_COLORFX_SEPIA:
979 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SEPIA;
980 break;
981 case V4L2_COLORFX_SET_CBCR:
982 isp3_param_write(params_vdev, arg->eff_tint, ISP3X_IMG_EFF_TINT);
983 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SEPIA;
984 break;
985 /*
986 * Color selection is similar to water color(AQUA):
987 * grayscale + selected color w threshold
988 */
989 case V4L2_COLORFX_AQUA:
990 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_COLOR_SEL;
991 isp3_param_write(params_vdev, arg->color_sel,
992 ISP3X_IMG_EFF_COLOR_SEL);
993 break;
994 case V4L2_COLORFX_EMBOSS:
995 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_EMBOSS;
996 isp3_param_write(params_vdev, arg->eff_mat_1,
997 CIF_IMG_EFF_MAT_1);
998 isp3_param_write(params_vdev, arg->eff_mat_2,
999 CIF_IMG_EFF_MAT_2);
1000 isp3_param_write(params_vdev, arg->eff_mat_3,
1001 CIF_IMG_EFF_MAT_3);
1002 break;
1003 case V4L2_COLORFX_SKETCH:
1004 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SKETCH;
1005 isp3_param_write(params_vdev, arg->eff_mat_3,
1006 CIF_IMG_EFF_MAT_3);
1007 isp3_param_write(params_vdev, arg->eff_mat_4,
1008 CIF_IMG_EFF_MAT_4);
1009 isp3_param_write(params_vdev, arg->eff_mat_5,
1010 CIF_IMG_EFF_MAT_5);
1011 break;
1012 case V4L2_COLORFX_BW:
1013 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_BLACKWHITE;
1014 break;
1015 case V4L2_COLORFX_NEGATIVE:
1016 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_NEGATIVE;
1017 break;
1018 default:
1019 break;
1020 }
1021
1022 isp3_param_write(params_vdev, eff_ctrl, ISP3X_IMG_EFF_CTRL);
1023 }
1024
1025 static void
isp_ie_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)1026 isp_ie_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
1027 {
1028 if (en) {
1029 isp3_param_set_bits(params_vdev, ISP3X_IMG_EFF_CTRL,
1030 CIF_IMG_EFF_CTRL_CFG_UPD |
1031 CIF_IMG_EFF_CTRL_ENABLE);
1032 } else {
1033 isp3_param_clear_bits(params_vdev, ISP3X_IMG_EFF_CTRL,
1034 CIF_IMG_EFF_CTRL_ENABLE);
1035 }
1036 }
1037
1038 static void
isp_rawae_config_foraf(struct rkisp_isp_params_vdev * params_vdev,const struct isp32_rawaf_meas_cfg * arg)1039 isp_rawae_config_foraf(struct rkisp_isp_params_vdev *params_vdev,
1040 const struct isp32_rawaf_meas_cfg *arg)
1041 {
1042 u32 block_hsize, block_vsize;
1043 u32 addr, value;
1044 u32 wnd_num_idx = 2;
1045 const u32 ae_wnd_num[] = {
1046 1, 5, 15, 15
1047 };
1048
1049 if (params_vdev->dev->isp_ver == ISP_V32_L && !!arg->ae_sel) {
1050 wnd_num_idx = 1;
1051 addr = ISP3X_RAWAE_LITE_BASE;
1052 } else {
1053 addr = ISP3X_RAWAE_BIG1_BASE;
1054 }
1055 value = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL);
1056 value &= ISP3X_RAWAE_BIG_EN;
1057
1058 value |= ISP3X_RAWAE_BIG_WND0_NUM(wnd_num_idx);
1059 isp3_param_write(params_vdev, value, addr + ISP3X_RAWAE_BIG_CTRL);
1060
1061 isp3_param_write(params_vdev,
1062 ISP_PACK_2SHORT(arg->win[0].h_offs, arg->win[0].v_offs),
1063 addr + ISP3X_RAWAE_BIG_OFFSET);
1064
1065 block_hsize = arg->win[0].h_size / ae_wnd_num[wnd_num_idx];
1066 block_vsize = arg->win[0].v_size / ae_wnd_num[wnd_num_idx];
1067 isp3_param_write(params_vdev,
1068 ISP_PACK_2SHORT(block_hsize, block_vsize),
1069 addr + ISP3X_RAWAE_BIG_BLK_SIZE);
1070 }
1071
1072 static void
isp_rawaf_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp32_rawaf_meas_cfg * arg)1073 isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev,
1074 const struct isp32_rawaf_meas_cfg *arg)
1075 {
1076 u32 i, var, ctrl;
1077 u16 h_size, v_size;
1078 u16 h_offs, v_offs;
1079 u8 gaus_en, viir_en, v1_fir_sel;
1080 size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->win),
1081 arg->num_afm_win);
1082
1083 for (i = 0; i < num_of_win; i++) {
1084 h_size = arg->win[i].h_size;
1085 v_size = arg->win[i].v_size;
1086 h_offs = arg->win[i].h_offs < 2 ? 2 : arg->win[i].h_offs;
1087 v_offs = arg->win[i].v_offs < 1 ? 1 : arg->win[i].v_offs;
1088
1089 if (i == 0) {
1090 h_size = h_size / 15 * 15;
1091 v_size = v_size / 15 * 15;
1092 }
1093
1094 /*
1095 * (horizontal left row), value must be greater or equal 2
1096 * (vertical top line), value must be greater or equal 1
1097 */
1098 isp3_param_write(params_vdev,
1099 ISP_PACK_2SHORT(v_offs, h_offs),
1100 ISP3X_RAWAF_OFFSET_WINA + i * 8);
1101
1102 /*
1103 * value must be smaller than [width of picture -2]
1104 * value must be lower than (number of lines -2)
1105 */
1106 isp3_param_write(params_vdev,
1107 ISP_PACK_2SHORT(v_size, h_size),
1108 ISP3X_RAWAF_SIZE_WINA + i * 8);
1109 }
1110
1111 var = 0;
1112 for (i = 0; i < ISP32_RAWAF_LINE_NUM; i++) {
1113 if (arg->line_en[i])
1114 var |= ISP3X_RAWAF_INTLINE0_EN << i;
1115 var |= ISP3X_RAWAF_INELINE0(arg->line_num[i]) << 4 * i;
1116 }
1117 isp3_param_write(params_vdev, var, ISP3X_RAWAF_INT_LINE);
1118
1119 if (params_vdev->dev->isp_ver == ISP_V32_L) {
1120 var = (arg->hldg_dilate_num & 0x7) << 16 |
1121 !!arg->bls_en << 12 | (arg->bls_offset & 0x1FF);
1122 isp3_param_write(params_vdev, var, ISP32L_RAWAF_CTRL1);
1123 }
1124
1125 var = isp3_param_read(params_vdev, ISP3X_RAWAF_THRES);
1126 var &= ~0xFFFF;
1127 var |= arg->afm_thres;
1128 isp3_param_write(params_vdev, var, ISP3X_RAWAF_THRES);
1129
1130 var = (arg->lum_var_shift[1] & 0x7) << 20 | (arg->lum_var_shift[0] & 0x7) << 16 |
1131 (arg->afm_var_shift[1] & 0x7) << 4 | (arg->afm_var_shift[0] & 0x7);
1132 if (params_vdev->dev->isp_ver == ISP_V32_L)
1133 var |= (arg->tnrin_shift & 0xf) << 8;
1134 isp3_param_write(params_vdev, var, ISP3X_RAWAF_VAR_SHIFT);
1135
1136 for (i = 0; i < ISP32_RAWAF_GAMMA_NUM / 2; i++) {
1137 var = ISP_PACK_2SHORT(arg->gamma_y[2 * i], arg->gamma_y[2 * i + 1]);
1138 isp3_param_write(params_vdev, var, ISP3X_RAWAF_GAMMA_Y0 + i * 4);
1139 }
1140 var = ISP_PACK_2SHORT(arg->gamma_y[16], 0);
1141 isp3_param_write(params_vdev, var, ISP3X_RAWAF_GAMMA_Y8);
1142
1143 var = (arg->v1iir_var_shift & 0x7) << 8 | (arg->h1iir_var_shift & 0x7);
1144 if (params_vdev->dev->isp_ver == ISP_V32)
1145 var |= (arg->v2iir_var_shift & 0x7) << 12 | (arg->h2iir_var_shift & 0x7) << 4;
1146 isp3_param_write(params_vdev, var, ISP3X_RAWAF_HVIIR_VAR_SHIFT);
1147
1148 var = ISP_PACK_2SHORT(arg->h_fv_thresh, arg->v_fv_thresh);
1149 isp3_param_write(params_vdev, var, ISP3X_RAWAF_HIIR_THRESH);
1150
1151 for (i = 0; i < ISP32_RAWAF_VFIR_COE_NUM; i++) {
1152 var = ISP_PACK_2SHORT(arg->v1fir_coe[i], arg->v2fir_coe[i]);
1153 isp3_param_write(params_vdev, var, ISP32_RAWAF_V_FIR_COE0 + i * 4);
1154 }
1155
1156 for (i = 0; i < ISP32_RAWAF_GAUS_COE_NUM / 4; i++) {
1157 var = ISP_PACK_4BYTE(arg->gaus_coe[i * 4], arg->gaus_coe[i * 4 + 1],
1158 arg->gaus_coe[i * 4 + 2], arg->gaus_coe[i * 4 + 3]);
1159 isp3_param_write(params_vdev, var, ISP32_RAWAF_GAUS_COE03 + i * 4);
1160 }
1161 var = ISP_PACK_4BYTE(arg->gaus_coe[ISP32_RAWAF_GAUS_COE_NUM - 1], 0, 0, 0);
1162 isp3_param_write(params_vdev, var, ISP32_RAWAF_GAUS_COE8);
1163
1164 isp3_param_write(params_vdev, arg->highlit_thresh, ISP3X_RAWAF_HIGHLIT_THRESH);
1165
1166 if (params_vdev->dev->isp_ver == ISP_V32_L) {
1167 var = ISP_PACK_2SHORT(arg->h_fv_limit, arg->h_fv_slope);
1168 isp3_param_write(params_vdev, var, ISP32L_RAWAF_CORING_H);
1169 var = ISP_PACK_2SHORT(arg->v_fv_limit, arg->v_fv_slope);
1170 isp3_param_write(params_vdev, var, ISP32L_RAWAF_CORING_V);
1171 }
1172
1173 viir_en = arg->viir_en;
1174 gaus_en = arg->gaus_en;
1175 v1_fir_sel = arg->v1_fir_sel;
1176 if (viir_en == 0)
1177 v1_fir_sel = 0;
1178
1179 ctrl = isp3_param_read(params_vdev, ISP3X_RAWAF_CTRL);
1180 ctrl &= ISP3X_RAWAF_EN;
1181 if (arg->hiir_en) {
1182 ctrl |= ISP3X_RAWAF_HIIR_EN;
1183 for (i = 0; i < ISP32_RAWAF_HIIR_COE_NUM / 2; i++) {
1184 var = ISP_PACK_2SHORT(arg->h1iir1_coe[i * 2], arg->h1iir1_coe[i * 2 + 1]);
1185 isp3_param_write(params_vdev, var, ISP3X_RAWAF_H1_IIR1_COE01 + i * 4);
1186 var = ISP_PACK_2SHORT(arg->h1iir2_coe[i * 2], arg->h1iir2_coe[i * 2 + 1]);
1187 isp3_param_write(params_vdev, var, ISP3X_RAWAF_H1_IIR2_COE01 + i * 4);
1188
1189 if (params_vdev->dev->isp_ver == ISP_V32_L)
1190 continue;
1191
1192 var = ISP_PACK_2SHORT(arg->h2iir1_coe[i * 2], arg->h2iir1_coe[i * 2 + 1]);
1193 isp3_param_write(params_vdev, var, ISP3X_RAWAF_H2_IIR1_COE01 + i * 4);
1194 var = ISP_PACK_2SHORT(arg->h2iir2_coe[i * 2], arg->h2iir2_coe[i * 2 + 1]);
1195 isp3_param_write(params_vdev, var, ISP3X_RAWAF_H2_IIR2_COE01 + i * 4);
1196 }
1197 }
1198 if (viir_en) {
1199 ctrl |= ISP3X_RAWAF_VIIR_EN;
1200 for (i = 0; i < ISP32_RAWAF_VIIR_COE_NUM; i++) {
1201 if (params_vdev->dev->isp_ver == ISP_V32)
1202 var = ISP_PACK_2SHORT(arg->v1iir_coe[i], arg->v2iir_coe[i]);
1203 else
1204 var = ISP_PACK_2SHORT(arg->v1iir_coe[i], 0);
1205 isp3_param_write(params_vdev, var, ISP3X_RAWAF_V_IIR_COE0 + i * 4);
1206 }
1207 }
1208 if (arg->ldg_en) {
1209 ctrl |= ISP3X_RAWAF_LDG_EN;
1210 for (i = 0; i < ISP32_RAWAF_CURVE_NUM; i++) {
1211 isp3_param_write(params_vdev,
1212 arg->curve_h[i].ldg_lumth |
1213 arg->curve_h[i].ldg_gain << 8 |
1214 arg->curve_h[i].ldg_gslp << 16,
1215 ISP3X_RAWAF_H_CURVEL + i * 16);
1216 isp3_param_write(params_vdev,
1217 arg->curve_v[i].ldg_lumth |
1218 arg->curve_v[i].ldg_gain << 8 |
1219 arg->curve_v[i].ldg_gslp << 16,
1220 ISP3X_RAWAF_V_CURVEL + i * 16);
1221 }
1222 }
1223
1224 ctrl |= !!arg->ae_config_use << 20 | !!arg->from_ynr << 19 |
1225 !!arg->from_awb << 18 | (arg->v_dnscl_mode & 0x3) << 16 |
1226 !!arg->sobel_sel << 15 | !!arg->vldg_sel << 14 |
1227 !!arg->y_mode << 13 | !!arg->ae_mode << 12 |
1228 !!arg->v1_fv_mode << 10 | !!arg->h1_fv_mode << 8 |
1229 !!arg->accu_8bit_mode << 6 | !!v1_fir_sel << 3 |
1230 !!gaus_en << 2 | !!arg->gamma_en << 1;
1231 if (params_vdev->dev->isp_ver == ISP_V32)
1232 ctrl |= !!arg->v2_fv_mode << 11 | !!arg->h2_fv_mode << 9;
1233 else
1234 ctrl |= !!arg->hiir_left_border_mode << 21 |
1235 !!arg->avg_ds_en << 22 |
1236 !!arg->avg_ds_mode << 23 |
1237 !!arg->h1_acc_mode << 24 |
1238 !!arg->h2_acc_mode << 25 |
1239 !!arg->v1_acc_mode << 26 |
1240 !!arg->v2_acc_mode << 27 |
1241 !!arg->ae_sel << 29;
1242 isp3_param_write(params_vdev, ctrl, ISP3X_RAWAF_CTRL);
1243
1244 ctrl = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH);
1245 if (((ctrl & ISP3X_RAWAF_SEL(3)) != ISP3X_RAWAF_SEL(arg->rawaf_sel)) ||
1246 (((!!(ctrl & ISP32L_BNR2AF_SEL)) != arg->bnr2af_sel) &&
1247 (params_vdev->dev->isp_ver == ISP_V32_L))) {
1248
1249 ctrl &= ~(ISP3X_RAWAF_SEL(3));
1250 ctrl |= ISP3X_RAWAF_SEL(arg->rawaf_sel);
1251 if (params_vdev->dev->isp_ver == ISP_V32_L) {
1252 if (arg->bnr2af_sel)
1253 ctrl |= ISP32L_BNR2AF_SEL;
1254 else
1255 ctrl &= ~ISP32L_BNR2AF_SEL;
1256 }
1257 isp3_param_write(params_vdev, ctrl, ISP3X_VI_ISP_PATH);
1258 }
1259
1260 params_vdev->afaemode_en = arg->ae_mode;
1261 if (params_vdev->afaemode_en)
1262 isp_rawae_config_foraf(params_vdev, arg);
1263 }
1264
1265 static void
isp_rawae_enable_foraf(struct rkisp_isp_params_vdev * params_vdev,bool en)1266 isp_rawae_enable_foraf(struct rkisp_isp_params_vdev *params_vdev, bool en)
1267 {
1268 u32 exp_ctrl;
1269 u32 addr = ISP3X_RAWAE_BIG1_BASE;
1270
1271 if (params_vdev->dev->isp_ver == ISP_V32_L)
1272 addr = ISP3X_RAWAE_LITE_BASE;
1273
1274 exp_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL);
1275 exp_ctrl &= ~ISP32_REG_WR_MASK;
1276 if (en)
1277 exp_ctrl |= ISP32_MODULE_EN;
1278 else
1279 exp_ctrl &= ~ISP32_MODULE_EN;
1280
1281 isp3_param_write(params_vdev, exp_ctrl, addr + ISP3X_RAWAE_BIG_CTRL);
1282 }
1283
1284 static void
isp_rawaf_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)1285 isp_rawaf_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
1286 {
1287 u32 afm_ctrl = isp3_param_read(params_vdev, ISP3X_RAWAF_CTRL);
1288
1289 afm_ctrl &= ~ISP32_REG_WR_MASK;
1290 if (en)
1291 afm_ctrl |= ISP3X_RAWAF_EN;
1292 else
1293 afm_ctrl &= ~ISP3X_RAWAF_EN;
1294
1295 isp3_param_write(params_vdev, afm_ctrl, ISP3X_RAWAF_CTRL);
1296 if (params_vdev->afaemode_en) {
1297 isp_rawae_enable_foraf(params_vdev, en);
1298 if (!en)
1299 params_vdev->afaemode_en = false;
1300 }
1301 }
1302
1303 static void
isp_rawaelite_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaelite_meas_cfg * arg)1304 isp_rawaelite_config(struct rkisp_isp_params_vdev *params_vdev,
1305 const struct isp2x_rawaelite_meas_cfg *arg)
1306 {
1307 struct rkisp_device *ispdev = params_vdev->dev;
1308 struct v4l2_rect *out_crop = &ispdev->isp_sdev.out_crop;
1309 u32 width = out_crop->width;
1310 u32 block_hsize, block_vsize, value;
1311 u32 wnd_num_idx = 0;
1312 const u32 ae_wnd_num[] = {1, 5};
1313
1314 value = isp3_param_read(params_vdev, ISP3X_RAWAE_LITE_CTRL);
1315 value &= ~(ISP3X_RAWAE_LITE_WNDNUM);
1316 if (arg->wnd_num) {
1317 value |= ISP3X_RAWAE_LITE_WNDNUM;
1318 wnd_num_idx = 1;
1319 }
1320 value &= ~ISP32_REG_WR_MASK;
1321 isp3_param_write(params_vdev, value, ISP3X_RAWAE_LITE_CTRL);
1322
1323 isp3_param_write(params_vdev,
1324 ISP_PACK_2SHORT(arg->win.h_offs, arg->win.v_offs),
1325 ISP3X_RAWAE_LITE_OFFSET);
1326
1327 block_hsize = arg->win.h_size / ae_wnd_num[wnd_num_idx];
1328 value = block_hsize * ae_wnd_num[wnd_num_idx] + arg->win.h_offs;
1329 if (ispdev->hw_dev->is_unite)
1330 width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
1331 if (value + 1 > width)
1332 block_hsize -= 1;
1333 block_vsize = arg->win.v_size / ae_wnd_num[wnd_num_idx];
1334 value = block_vsize * ae_wnd_num[wnd_num_idx] + arg->win.v_offs;
1335 if (value + 2 > out_crop->height)
1336 block_vsize -= 1;
1337 if (block_vsize % 2)
1338 block_vsize -= 1;
1339 isp3_param_write(params_vdev,
1340 ISP_PACK_2SHORT(block_hsize, block_vsize),
1341 ISP3X_RAWAE_LITE_BLK_SIZ);
1342
1343 value = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH);
1344 if ((value & ISP3X_RAWAE012_SEL(3)) != ISP3X_RAWAE012_SEL(arg->rawae_sel)) {
1345 value &= ~(ISP3X_RAWAE012_SEL(3));
1346 value |= ISP3X_RAWAE012_SEL(arg->rawae_sel);
1347 isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH);
1348 }
1349 }
1350
1351 static void
isp_rawaelite_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)1352 isp_rawaelite_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
1353 {
1354 u32 exp_ctrl;
1355
1356 exp_ctrl = isp3_param_read(params_vdev, ISP3X_RAWAE_LITE_CTRL);
1357 exp_ctrl &= ~ISP32_REG_WR_MASK;
1358 if (en)
1359 exp_ctrl |= ISP3X_RAWAE_LITE_EN;
1360 else
1361 exp_ctrl &= ~ISP3X_RAWAE_LITE_EN;
1362
1363 isp3_param_write(params_vdev, exp_ctrl, ISP3X_RAWAE_LITE_CTRL);
1364 }
1365
1366 static void
isp_rawaebig_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaebig_meas_cfg * arg,u32 blk_no)1367 isp_rawaebig_config(struct rkisp_isp_params_vdev *params_vdev,
1368 const struct isp2x_rawaebig_meas_cfg *arg,
1369 u32 blk_no)
1370 {
1371 struct rkisp_device *ispdev = params_vdev->dev;
1372 struct v4l2_rect *out_crop = &ispdev->isp_sdev.out_crop;
1373 u32 width = out_crop->width;
1374 u32 block_hsize, block_vsize;
1375 u32 addr, i, value, h_size, v_size;
1376 u32 wnd_num_idx = 0;
1377 const u32 ae_wnd_num[] = {
1378 1, 5, 15, 15
1379 };
1380
1381 switch (blk_no) {
1382 case 1:
1383 addr = ISP3X_RAWAE_BIG2_BASE;
1384 break;
1385 case 2:
1386 addr = ISP3X_RAWAE_BIG3_BASE;
1387 break;
1388 case 0:
1389 default:
1390 addr = ISP3X_RAWAE_BIG1_BASE;
1391 break;
1392 }
1393
1394 /* avoid to override the old enable value */
1395 value = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL);
1396 value &= ISP3X_RAWAE_BIG_EN;
1397
1398 wnd_num_idx = arg->wnd_num;
1399 value |= ISP3X_RAWAE_BIG_WND0_NUM(wnd_num_idx);
1400
1401 if (arg->subwin_en[0])
1402 value |= ISP3X_RAWAE_BIG_WND1_EN;
1403 if (params_vdev->dev->isp_ver == ISP_V32) {
1404 if (arg->subwin_en[1])
1405 value |= ISP3X_RAWAE_BIG_WND2_EN;
1406 if (arg->subwin_en[2])
1407 value |= ISP3X_RAWAE_BIG_WND3_EN;
1408 if (arg->subwin_en[3])
1409 value |= ISP3X_RAWAE_BIG_WND4_EN;
1410 }
1411 isp3_param_write(params_vdev, value, addr + ISP3X_RAWAE_BIG_CTRL);
1412
1413 isp3_param_write(params_vdev,
1414 ISP_PACK_2SHORT(arg->win.h_offs, arg->win.v_offs),
1415 addr + ISP3X_RAWAE_BIG_OFFSET);
1416
1417 block_hsize = arg->win.h_size / ae_wnd_num[wnd_num_idx];
1418 value = block_hsize * ae_wnd_num[wnd_num_idx] + arg->win.h_offs;
1419 if (ispdev->hw_dev->is_unite)
1420 width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
1421 if (value + 1 > width)
1422 block_hsize -= 1;
1423 block_vsize = arg->win.v_size / ae_wnd_num[wnd_num_idx];
1424 value = block_vsize * ae_wnd_num[wnd_num_idx] + arg->win.v_offs;
1425 if (value + 2 > out_crop->height)
1426 block_vsize -= 1;
1427 if (block_vsize % 2)
1428 block_vsize -= 1;
1429 isp3_param_write(params_vdev,
1430 ISP_PACK_2SHORT(block_hsize, block_vsize),
1431 addr + ISP3X_RAWAE_BIG_BLK_SIZE);
1432
1433 for (i = 0; i < ISP32_RAWAEBIG_SUBWIN_NUM; i++) {
1434 isp3_param_write(params_vdev,
1435 ISP_PACK_2SHORT(arg->subwin[i].h_offs, arg->subwin[i].v_offs),
1436 addr + ISP3X_RAWAE_BIG_WND1_OFFSET + 8 * i);
1437
1438 v_size = arg->subwin[i].v_size + arg->subwin[i].v_offs;
1439 h_size = arg->subwin[i].h_size + arg->subwin[i].h_offs;
1440 isp3_param_write(params_vdev,
1441 ISP_PACK_2SHORT(h_size, v_size),
1442 addr + ISP3X_RAWAE_BIG_WND1_SIZE + 8 * i);
1443 }
1444
1445 value = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH);
1446 if (blk_no == 0) {
1447 if ((value & ISP3X_RAWAE3_SEL(3)) != ISP3X_RAWAE3_SEL(arg->rawae_sel)) {
1448 value &= ~(ISP3X_RAWAE3_SEL(3));
1449 value |= ISP3X_RAWAE3_SEL(arg->rawae_sel);
1450 isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH);
1451 }
1452 } else {
1453 if ((value & ISP3X_RAWAE012_SEL(3)) != ISP3X_RAWAE012_SEL(arg->rawae_sel)) {
1454 value &= ~(ISP3X_RAWAE012_SEL(3));
1455 value |= ISP3X_RAWAE012_SEL(arg->rawae_sel);
1456 isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH);
1457 }
1458 }
1459 }
1460
1461 static void
isp_rawaebig_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 blk_no)1462 isp_rawaebig_enable(struct rkisp_isp_params_vdev *params_vdev,
1463 bool en, u32 blk_no)
1464 {
1465 u32 exp_ctrl;
1466 u32 addr;
1467
1468 switch (blk_no) {
1469 case 1:
1470 addr = ISP3X_RAWAE_BIG2_BASE;
1471 break;
1472 case 2:
1473 addr = ISP3X_RAWAE_BIG3_BASE;
1474 break;
1475 case 0:
1476 default:
1477 addr = ISP3X_RAWAE_BIG1_BASE;
1478 break;
1479 }
1480
1481 exp_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL);
1482 exp_ctrl &= ~ISP32_REG_WR_MASK;
1483 if (en)
1484 exp_ctrl |= ISP32_MODULE_EN;
1485 else
1486 exp_ctrl &= ~ISP32_MODULE_EN;
1487
1488 isp3_param_write(params_vdev, exp_ctrl, addr + ISP3X_RAWAE_BIG_CTRL);
1489 }
1490
1491 static void
isp_rawae1_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaebig_meas_cfg * arg)1492 isp_rawae1_config(struct rkisp_isp_params_vdev *params_vdev,
1493 const struct isp2x_rawaebig_meas_cfg *arg)
1494 {
1495 isp_rawaebig_config(params_vdev, arg, 1);
1496 }
1497
1498 static void
isp_rawae1_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)1499 isp_rawae1_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
1500 {
1501 isp_rawaebig_enable(params_vdev, en, 1);
1502 }
1503
1504 static void
isp_rawae2_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaebig_meas_cfg * arg)1505 isp_rawae2_config(struct rkisp_isp_params_vdev *params_vdev,
1506 const struct isp2x_rawaebig_meas_cfg *arg)
1507 {
1508 isp_rawaebig_config(params_vdev, arg, 2);
1509 }
1510
1511 static void
isp_rawae2_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)1512 isp_rawae2_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
1513 {
1514 isp_rawaebig_enable(params_vdev, en, 2);
1515 }
1516
1517 static void
isp_rawae3_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaebig_meas_cfg * arg)1518 isp_rawae3_config(struct rkisp_isp_params_vdev *params_vdev,
1519 const struct isp2x_rawaebig_meas_cfg *arg)
1520 {
1521 isp_rawaebig_config(params_vdev, arg, 0);
1522 }
1523
1524 static void
isp_rawae3_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)1525 isp_rawae3_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
1526 {
1527 isp_rawaebig_enable(params_vdev, en, 0);
1528 }
1529
1530 static void
isp_rawawb_cfg_sram(struct rkisp_isp_params_vdev * params_vdev,const struct isp32_rawawb_meas_cfg * arg,bool is_check)1531 isp_rawawb_cfg_sram(struct rkisp_isp_params_vdev *params_vdev,
1532 const struct isp32_rawawb_meas_cfg *arg, bool is_check)
1533 {
1534 u32 i, val = ISP32_MODULE_EN;
1535
1536 if (params_vdev->dev->isp_ver == ISP_V32 && is_check &&
1537 !(isp3_param_read(params_vdev, ISP3X_RAWAWB_CTRL) & val))
1538 return;
1539
1540 for (i = 0; i < ISP32_RAWAWB_WEIGHT_NUM / 5; i++) {
1541 isp3_param_write(params_vdev,
1542 (arg->wp_blk_wei_w[5 * i] & 0x3f) |
1543 (arg->wp_blk_wei_w[5 * i + 1] & 0x3f) << 6 |
1544 (arg->wp_blk_wei_w[5 * i + 2] & 0x3f) << 12 |
1545 (arg->wp_blk_wei_w[5 * i + 3] & 0x3f) << 18 |
1546 (arg->wp_blk_wei_w[5 * i + 4] & 0x3f) << 24,
1547 ISP3X_RAWAWB_WRAM_DATA_BASE);
1548 }
1549 }
1550
1551 static void
isp_rawawb_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp32_rawawb_meas_cfg * arg)1552 isp_rawawb_config(struct rkisp_isp_params_vdev *params_vdev,
1553 const struct isp32_rawawb_meas_cfg *arg)
1554 {
1555 struct isp32_isp_params_cfg *params_rec = params_vdev->isp32_params;
1556 struct isp32_rawawb_meas_cfg *arg_rec = ¶ms_rec->meas.rawawb;
1557 const struct isp2x_bls_fixed_val *pval = &arg->bls2_val;
1558 u32 value, val, mask, i;
1559
1560 value = isp3_param_read(params_vdev, ISP3X_BLS_CTRL);
1561 value &= ~ISP32_BLS_BLS2_EN;
1562 if (arg->bls2_en) {
1563 switch (params_vdev->raw_type) {
1564 case RAW_BGGR:
1565 isp3_param_write(params_vdev, pval->r, ISP32_BLS2_D_FIXED);
1566 isp3_param_write(params_vdev, pval->gr, ISP32_BLS2_C_FIXED);
1567 isp3_param_write(params_vdev, pval->gb, ISP32_BLS2_B_FIXED);
1568 isp3_param_write(params_vdev, pval->b, ISP32_BLS2_A_FIXED);
1569 break;
1570 case RAW_GBRG:
1571 isp3_param_write(params_vdev, pval->r, ISP32_BLS2_C_FIXED);
1572 isp3_param_write(params_vdev, pval->gr, ISP32_BLS2_D_FIXED);
1573 isp3_param_write(params_vdev, pval->gb, ISP32_BLS2_A_FIXED);
1574 isp3_param_write(params_vdev, pval->b, ISP32_BLS2_B_FIXED);
1575 break;
1576 case RAW_GRBG:
1577 isp3_param_write(params_vdev, pval->r, ISP32_BLS2_B_FIXED);
1578 isp3_param_write(params_vdev, pval->gr, ISP32_BLS2_A_FIXED);
1579 isp3_param_write(params_vdev, pval->gb, ISP32_BLS2_D_FIXED);
1580 isp3_param_write(params_vdev, pval->b, ISP32_BLS2_C_FIXED);
1581 break;
1582 case RAW_RGGB:
1583 default:
1584 isp3_param_write(params_vdev, pval->r, ISP32_BLS2_A_FIXED);
1585 isp3_param_write(params_vdev, pval->gr, ISP32_BLS2_B_FIXED);
1586 isp3_param_write(params_vdev, pval->gb, ISP32_BLS2_C_FIXED);
1587 isp3_param_write(params_vdev, pval->b, ISP32_BLS2_D_FIXED);
1588 }
1589 value |= ISP32_BLS_BLS2_EN;
1590 }
1591 isp3_param_write(params_vdev, value, ISP3X_BLS_CTRL);
1592
1593 value = arg->in_overexposure_threshold << 16 |
1594 !!arg->blk_with_luma_wei_en << 8 |
1595 (arg->blk_measure_illu_idx & 0x7) << 4 |
1596 !!arg->blk_rtdw_measure_en << 3 |
1597 !!arg->blk_measure_xytype << 2 |
1598 !!arg->blk_measure_mode << 1 |
1599 !!arg->blk_measure_enable;
1600 if (params_vdev->dev->isp_ver == ISP_V32_L)
1601 value |= !!arg->ds16x8_mode_en << 7;
1602 isp3_param_write(params_vdev, value, ISP3X_RAWAWB_BLK_CTRL);
1603
1604 isp3_param_write(params_vdev,
1605 ISP_PACK_2SHORT(arg->h_offs, arg->v_offs),
1606 ISP3X_RAWAWB_WIN_OFFS);
1607
1608 isp3_param_write(params_vdev,
1609 ISP_PACK_2SHORT(arg->h_size, arg->v_size),
1610 ISP3X_RAWAWB_WIN_SIZE);
1611
1612 isp3_param_write(params_vdev,
1613 ISP_PACK_2SHORT(arg->r_max, arg->g_max),
1614 ISP3X_RAWAWB_LIMIT_RG_MAX);
1615
1616 isp3_param_write(params_vdev,
1617 ISP_PACK_2SHORT(arg->b_max, arg->y_max),
1618 ISP3X_RAWAWB_LIMIT_BY_MAX);
1619
1620 isp3_param_write(params_vdev,
1621 ISP_PACK_2SHORT(arg->r_min, arg->g_min),
1622 ISP3X_RAWAWB_LIMIT_RG_MIN);
1623
1624 isp3_param_write(params_vdev,
1625 ISP_PACK_2SHORT(arg->b_min, arg->y_min),
1626 ISP3X_RAWAWB_LIMIT_BY_MIN);
1627
1628 value = !!arg->wp_hist_xytype << 4 |
1629 !!arg->wp_blk_wei_en1 << 3 |
1630 !!arg->wp_blk_wei_en0 << 2 |
1631 !!arg->wp_luma_wei_en1 << 1 |
1632 !!arg->wp_luma_wei_en0;
1633 isp3_param_write(params_vdev, value, ISP3X_RAWAWB_WEIGHT_CURVE_CTRL);
1634
1635 isp3_param_write(params_vdev,
1636 ISP_PACK_4BYTE(arg->wp_luma_weicurve_y0,
1637 arg->wp_luma_weicurve_y1,
1638 arg->wp_luma_weicurve_y2,
1639 arg->wp_luma_weicurve_y3),
1640 ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR03);
1641
1642 isp3_param_write(params_vdev,
1643 ISP_PACK_4BYTE(arg->wp_luma_weicurve_y4,
1644 arg->wp_luma_weicurve_y5,
1645 arg->wp_luma_weicurve_y6,
1646 arg->wp_luma_weicurve_y7),
1647 ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR47);
1648
1649 isp3_param_write(params_vdev,
1650 arg->wp_luma_weicurve_y8,
1651 ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR8);
1652
1653 isp3_param_write(params_vdev,
1654 ISP_PACK_4BYTE(arg->wp_luma_weicurve_w0,
1655 arg->wp_luma_weicurve_w1,
1656 arg->wp_luma_weicurve_w2,
1657 arg->wp_luma_weicurve_w3),
1658 ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR03);
1659
1660 isp3_param_write(params_vdev,
1661 ISP_PACK_4BYTE(arg->wp_luma_weicurve_w4,
1662 arg->wp_luma_weicurve_w5,
1663 arg->wp_luma_weicurve_w6,
1664 arg->wp_luma_weicurve_w7),
1665 ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR47);
1666
1667 isp3_param_write(params_vdev,
1668 ISP_PACK_2SHORT(arg->wp_luma_weicurve_w8,
1669 arg->pre_wbgain_inv_r),
1670 ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR8);
1671
1672 isp3_param_write(params_vdev,
1673 ISP_PACK_2SHORT(arg->pre_wbgain_inv_g,
1674 arg->pre_wbgain_inv_b),
1675 ISP3X_RAWAWB_PRE_WBGAIN_INV);
1676
1677 isp3_param_write(params_vdev,
1678 ISP_PACK_2SHORT(arg->vertex0_u_0, arg->vertex0_v_0),
1679 ISP3X_RAWAWB_UV_DETC_VERTEX0_0);
1680
1681 isp3_param_write(params_vdev,
1682 ISP_PACK_2SHORT(arg->vertex1_u_0, arg->vertex1_v_0),
1683 ISP3X_RAWAWB_UV_DETC_VERTEX1_0);
1684
1685 isp3_param_write(params_vdev,
1686 ISP_PACK_2SHORT(arg->vertex2_u_0, arg->vertex2_v_0),
1687 ISP3X_RAWAWB_UV_DETC_VERTEX2_0);
1688
1689 isp3_param_write(params_vdev,
1690 ISP_PACK_2SHORT(arg->vertex3_u_0, arg->vertex3_v_0),
1691 ISP3X_RAWAWB_UV_DETC_VERTEX3_0);
1692
1693 isp3_param_write(params_vdev, arg->islope01_0,
1694 ISP3X_RAWAWB_UV_DETC_ISLOPE01_0);
1695
1696 isp3_param_write(params_vdev, arg->islope12_0,
1697 ISP3X_RAWAWB_UV_DETC_ISLOPE12_0);
1698
1699 isp3_param_write(params_vdev, arg->islope23_0,
1700 ISP3X_RAWAWB_UV_DETC_ISLOPE23_0);
1701
1702 isp3_param_write(params_vdev, arg->islope30_0,
1703 ISP3X_RAWAWB_UV_DETC_ISLOPE30_0);
1704
1705 isp3_param_write(params_vdev,
1706 ISP_PACK_2SHORT(arg->vertex0_u_1,
1707 arg->vertex0_v_1),
1708 ISP3X_RAWAWB_UV_DETC_VERTEX0_1);
1709
1710 isp3_param_write(params_vdev,
1711 ISP_PACK_2SHORT(arg->vertex1_u_1,
1712 arg->vertex1_v_1),
1713 ISP3X_RAWAWB_UV_DETC_VERTEX1_1);
1714
1715 isp3_param_write(params_vdev,
1716 ISP_PACK_2SHORT(arg->vertex2_u_1,
1717 arg->vertex2_v_1),
1718 ISP3X_RAWAWB_UV_DETC_VERTEX2_1);
1719
1720 isp3_param_write(params_vdev,
1721 ISP_PACK_2SHORT(arg->vertex3_u_1,
1722 arg->vertex3_v_1),
1723 ISP3X_RAWAWB_UV_DETC_VERTEX3_1);
1724
1725 isp3_param_write(params_vdev, arg->islope01_1,
1726 ISP3X_RAWAWB_UV_DETC_ISLOPE01_1);
1727
1728 isp3_param_write(params_vdev, arg->islope12_1,
1729 ISP3X_RAWAWB_UV_DETC_ISLOPE12_1);
1730
1731 isp3_param_write(params_vdev, arg->islope23_1,
1732 ISP3X_RAWAWB_UV_DETC_ISLOPE23_1);
1733
1734 isp3_param_write(params_vdev, arg->islope30_1,
1735 ISP3X_RAWAWB_UV_DETC_ISLOPE30_1);
1736
1737 isp3_param_write(params_vdev,
1738 ISP_PACK_2SHORT(arg->vertex0_u_2,
1739 arg->vertex0_v_2),
1740 ISP3X_RAWAWB_UV_DETC_VERTEX0_2);
1741
1742 isp3_param_write(params_vdev,
1743 ISP_PACK_2SHORT(arg->vertex1_u_2,
1744 arg->vertex1_v_2),
1745 ISP3X_RAWAWB_UV_DETC_VERTEX1_2);
1746
1747 isp3_param_write(params_vdev,
1748 ISP_PACK_2SHORT(arg->vertex2_u_2,
1749 arg->vertex2_v_2),
1750 ISP3X_RAWAWB_UV_DETC_VERTEX2_2);
1751
1752 isp3_param_write(params_vdev,
1753 ISP_PACK_2SHORT(arg->vertex3_u_2,
1754 arg->vertex3_v_2),
1755 ISP3X_RAWAWB_UV_DETC_VERTEX3_2);
1756
1757 isp3_param_write(params_vdev, arg->islope01_2,
1758 ISP3X_RAWAWB_UV_DETC_ISLOPE01_2);
1759
1760 isp3_param_write(params_vdev, arg->islope12_2,
1761 ISP3X_RAWAWB_UV_DETC_ISLOPE12_2);
1762
1763 isp3_param_write(params_vdev, arg->islope23_2,
1764 ISP3X_RAWAWB_UV_DETC_ISLOPE23_2);
1765
1766 isp3_param_write(params_vdev, arg->islope30_2,
1767 ISP3X_RAWAWB_UV_DETC_ISLOPE30_2);
1768
1769 isp3_param_write(params_vdev,
1770 ISP_PACK_2SHORT(arg->vertex0_u_3,
1771 arg->vertex0_v_3),
1772 ISP3X_RAWAWB_UV_DETC_VERTEX0_3);
1773
1774 isp3_param_write(params_vdev,
1775 ISP_PACK_2SHORT(arg->vertex1_u_3,
1776 arg->vertex1_v_3),
1777 ISP3X_RAWAWB_UV_DETC_VERTEX1_3);
1778
1779 isp3_param_write(params_vdev,
1780 ISP_PACK_2SHORT(arg->vertex2_u_3,
1781 arg->vertex2_v_3),
1782 ISP3X_RAWAWB_UV_DETC_VERTEX2_3);
1783
1784 isp3_param_write(params_vdev,
1785 ISP_PACK_2SHORT(arg->vertex3_u_3,
1786 arg->vertex3_v_3),
1787 ISP3X_RAWAWB_UV_DETC_VERTEX3_3);
1788
1789 isp3_param_write(params_vdev, arg->islope01_3,
1790 ISP3X_RAWAWB_UV_DETC_ISLOPE01_3);
1791
1792 isp3_param_write(params_vdev, arg->islope12_3,
1793 ISP3X_RAWAWB_UV_DETC_ISLOPE12_3);
1794
1795 isp3_param_write(params_vdev, arg->islope23_3,
1796 ISP3X_RAWAWB_UV_DETC_ISLOPE23_3);
1797
1798 isp3_param_write(params_vdev, arg->islope30_3,
1799 ISP3X_RAWAWB_UV_DETC_ISLOPE30_3);
1800
1801 isp3_param_write(params_vdev,
1802 ISP_PACK_2SHORT(arg->rgb2ryuvmat0_y,
1803 arg->rgb2ryuvmat1_y),
1804 ISP3X_RAWAWB_YUV_RGB2ROTY_0);
1805
1806 isp3_param_write(params_vdev,
1807 ISP_PACK_2SHORT(arg->rgb2ryuvmat2_y,
1808 arg->rgb2ryuvofs_y),
1809 ISP3X_RAWAWB_YUV_RGB2ROTY_1);
1810
1811 isp3_param_write(params_vdev,
1812 ISP_PACK_2SHORT(arg->rgb2ryuvmat0_u,
1813 arg->rgb2ryuvmat1_u),
1814 ISP3X_RAWAWB_YUV_RGB2ROTU_0);
1815
1816
1817 isp3_param_write(params_vdev,
1818 ISP_PACK_2SHORT(arg->rgb2ryuvmat2_u,
1819 arg->rgb2ryuvofs_u),
1820 ISP3X_RAWAWB_YUV_RGB2ROTU_1);
1821
1822 isp3_param_write(params_vdev,
1823 ISP_PACK_2SHORT(arg->rgb2ryuvmat0_v,
1824 arg->rgb2ryuvmat1_v),
1825 ISP3X_RAWAWB_YUV_RGB2ROTV_0);
1826
1827 isp3_param_write(params_vdev,
1828 ISP_PACK_2SHORT(arg->rgb2ryuvmat2_v,
1829 arg->rgb2ryuvofs_v),
1830 ISP3X_RAWAWB_YUV_RGB2ROTV_1);
1831
1832 isp3_param_write(params_vdev,
1833 ISP_PACK_2SHORT(arg->coor_x1_ls0_y,
1834 arg->vec_x21_ls0_y),
1835 ISP3X_RAWAWB_YUV_X_COOR_Y_0);
1836
1837 isp3_param_write(params_vdev,
1838 ISP_PACK_2SHORT(arg->coor_x1_ls0_u,
1839 arg->vec_x21_ls0_u),
1840 ISP3X_RAWAWB_YUV_X_COOR_U_0);
1841
1842 isp3_param_write(params_vdev,
1843 ISP_PACK_2SHORT(arg->coor_x1_ls0_v,
1844 arg->vec_x21_ls0_v),
1845 ISP3X_RAWAWB_YUV_X_COOR_V_0);
1846
1847 isp3_param_write(params_vdev,
1848 ISP_PACK_4BYTE(arg->dis_x1x2_ls0, 0,
1849 arg->rotu0_ls0, arg->rotu1_ls0),
1850 ISP3X_RAWAWB_YUV_X1X2_DIS_0);
1851
1852 isp3_param_write(params_vdev,
1853 ISP_PACK_4BYTE(arg->rotu2_ls0, arg->rotu3_ls0,
1854 arg->rotu4_ls0, arg->rotu5_ls0),
1855 ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_0);
1856
1857 isp3_param_write(params_vdev,
1858 ISP_PACK_2SHORT(arg->th0_ls0, arg->th1_ls0),
1859 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_0);
1860
1861 isp3_param_write(params_vdev,
1862 ISP_PACK_2SHORT(arg->th2_ls0, arg->th3_ls0),
1863 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_0);
1864
1865 isp3_param_write(params_vdev,
1866 ISP_PACK_2SHORT(arg->th4_ls0, arg->th5_ls0),
1867 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_0);
1868
1869 isp3_param_write(params_vdev,
1870 ISP_PACK_2SHORT(arg->coor_x1_ls1_y,
1871 arg->vec_x21_ls1_y),
1872 ISP3X_RAWAWB_YUV_X_COOR_Y_1);
1873
1874 isp3_param_write(params_vdev,
1875 ISP_PACK_2SHORT(arg->coor_x1_ls1_u,
1876 arg->vec_x21_ls1_u),
1877 ISP3X_RAWAWB_YUV_X_COOR_U_1);
1878
1879 isp3_param_write(params_vdev,
1880 ISP_PACK_2SHORT(arg->coor_x1_ls1_v,
1881 arg->vec_x21_ls1_v),
1882 ISP3X_RAWAWB_YUV_X_COOR_V_1);
1883
1884 isp3_param_write(params_vdev,
1885 ISP_PACK_4BYTE(arg->dis_x1x2_ls1, 0,
1886 arg->rotu0_ls1, arg->rotu1_ls1),
1887 ISP3X_RAWAWB_YUV_X1X2_DIS_1);
1888
1889 isp3_param_write(params_vdev,
1890 ISP_PACK_4BYTE(arg->rotu2_ls1, arg->rotu3_ls1,
1891 arg->rotu4_ls1, arg->rotu5_ls1),
1892 ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_1);
1893
1894 isp3_param_write(params_vdev,
1895 ISP_PACK_2SHORT(arg->th0_ls1, arg->th1_ls1),
1896 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_1);
1897
1898 isp3_param_write(params_vdev,
1899 ISP_PACK_2SHORT(arg->th2_ls1, arg->th3_ls1),
1900 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_1);
1901
1902 isp3_param_write(params_vdev,
1903 ISP_PACK_2SHORT(arg->th4_ls1, arg->th5_ls1),
1904 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_1);
1905
1906 isp3_param_write(params_vdev,
1907 ISP_PACK_2SHORT(arg->coor_x1_ls2_y, arg->vec_x21_ls2_y),
1908 ISP3X_RAWAWB_YUV_X_COOR_Y_2);
1909
1910 isp3_param_write(params_vdev,
1911 ISP_PACK_2SHORT(arg->coor_x1_ls2_u, arg->vec_x21_ls2_u),
1912 ISP3X_RAWAWB_YUV_X_COOR_U_2);
1913
1914 isp3_param_write(params_vdev,
1915 ISP_PACK_2SHORT(arg->coor_x1_ls2_v, arg->vec_x21_ls2_v),
1916 ISP3X_RAWAWB_YUV_X_COOR_V_2);
1917
1918 isp3_param_write(params_vdev,
1919 ISP_PACK_4BYTE(arg->dis_x1x2_ls2, 0,
1920 arg->rotu0_ls2, arg->rotu1_ls2),
1921 ISP3X_RAWAWB_YUV_X1X2_DIS_2);
1922
1923 isp3_param_write(params_vdev,
1924 ISP_PACK_4BYTE(arg->rotu2_ls2, arg->rotu3_ls2,
1925 arg->rotu4_ls2, arg->rotu5_ls2),
1926 ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_2);
1927
1928 isp3_param_write(params_vdev,
1929 ISP_PACK_2SHORT(arg->th0_ls2, arg->th1_ls2),
1930 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_2);
1931
1932 isp3_param_write(params_vdev,
1933 ISP_PACK_2SHORT(arg->th2_ls2, arg->th3_ls2),
1934 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_2);
1935
1936 isp3_param_write(params_vdev,
1937 ISP_PACK_2SHORT(arg->th4_ls2, arg->th5_ls2),
1938 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_2);
1939
1940 isp3_param_write(params_vdev,
1941 ISP_PACK_2SHORT(arg->coor_x1_ls3_y,
1942 arg->vec_x21_ls3_y),
1943 ISP3X_RAWAWB_YUV_X_COOR_Y_3);
1944
1945 isp3_param_write(params_vdev,
1946 ISP_PACK_2SHORT(arg->coor_x1_ls3_u,
1947 arg->vec_x21_ls3_u),
1948 ISP3X_RAWAWB_YUV_X_COOR_U_3);
1949
1950 isp3_param_write(params_vdev,
1951 ISP_PACK_2SHORT(arg->coor_x1_ls3_v,
1952 arg->vec_x21_ls3_v),
1953 ISP3X_RAWAWB_YUV_X_COOR_V_3);
1954
1955 isp3_param_write(params_vdev,
1956 ISP_PACK_4BYTE(arg->dis_x1x2_ls3, 0,
1957 arg->rotu0_ls3, arg->rotu1_ls3),
1958 ISP3X_RAWAWB_YUV_X1X2_DIS_3);
1959
1960 isp3_param_write(params_vdev,
1961 ISP_PACK_4BYTE(arg->rotu2_ls3, arg->rotu3_ls3,
1962 arg->rotu4_ls3, arg->rotu5_ls3),
1963 ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_3);
1964
1965 isp3_param_write(params_vdev,
1966 ISP_PACK_2SHORT(arg->th0_ls3, arg->th1_ls3),
1967 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_3);
1968
1969 isp3_param_write(params_vdev,
1970 ISP_PACK_2SHORT(arg->th2_ls3, arg->th3_ls3),
1971 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_3);
1972
1973 isp3_param_write(params_vdev,
1974 ISP_PACK_2SHORT(arg->th4_ls3, arg->th5_ls3),
1975 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_3);
1976
1977 isp3_param_write(params_vdev,
1978 ISP_PACK_2SHORT(arg->wt0, arg->wt1),
1979 ISP3X_RAWAWB_RGB2XY_WT01);
1980
1981 isp3_param_write(params_vdev, arg->wt2,
1982 ISP3X_RAWAWB_RGB2XY_WT2);
1983
1984 isp3_param_write(params_vdev,
1985 ISP_PACK_2SHORT(arg->mat0_x, arg->mat0_y),
1986 ISP3X_RAWAWB_RGB2XY_MAT0_XY);
1987
1988 isp3_param_write(params_vdev,
1989 ISP_PACK_2SHORT(arg->mat1_x, arg->mat1_y),
1990 ISP3X_RAWAWB_RGB2XY_MAT1_XY);
1991
1992 isp3_param_write(params_vdev,
1993 ISP_PACK_2SHORT(arg->mat2_x, arg->mat2_y),
1994 ISP3X_RAWAWB_RGB2XY_MAT2_XY);
1995
1996 isp3_param_write(params_vdev,
1997 ISP_PACK_2SHORT(arg->nor_x0_0, arg->nor_x1_0),
1998 ISP3X_RAWAWB_XY_DETC_NOR_X_0);
1999
2000 isp3_param_write(params_vdev,
2001 ISP_PACK_2SHORT(arg->nor_y0_0, arg->nor_y1_0),
2002 ISP3X_RAWAWB_XY_DETC_NOR_Y_0);
2003
2004 isp3_param_write(params_vdev,
2005 ISP_PACK_2SHORT(arg->big_x0_0, arg->big_x1_0),
2006 ISP3X_RAWAWB_XY_DETC_BIG_X_0);
2007
2008 isp3_param_write(params_vdev,
2009 ISP_PACK_2SHORT(arg->big_y0_0, arg->big_y1_0),
2010 ISP3X_RAWAWB_XY_DETC_BIG_Y_0);
2011
2012 isp3_param_write(params_vdev,
2013 ISP_PACK_2SHORT(arg->nor_x0_1, arg->nor_x1_1),
2014 ISP3X_RAWAWB_XY_DETC_NOR_X_1);
2015
2016 isp3_param_write(params_vdev,
2017 ISP_PACK_2SHORT(arg->nor_y0_1, arg->nor_y1_1),
2018 ISP3X_RAWAWB_XY_DETC_NOR_Y_1);
2019
2020 isp3_param_write(params_vdev,
2021 ISP_PACK_2SHORT(arg->big_x0_1, arg->big_x1_1),
2022 ISP3X_RAWAWB_XY_DETC_BIG_X_1);
2023
2024 isp3_param_write(params_vdev,
2025 ISP_PACK_2SHORT(arg->big_y0_1, arg->big_y1_1),
2026 ISP3X_RAWAWB_XY_DETC_BIG_Y_1);
2027
2028 isp3_param_write(params_vdev,
2029 ISP_PACK_2SHORT(arg->nor_x0_2, arg->nor_x1_2),
2030 ISP3X_RAWAWB_XY_DETC_NOR_X_2);
2031
2032 isp3_param_write(params_vdev,
2033 ISP_PACK_2SHORT(arg->nor_y0_2, arg->nor_y1_2),
2034 ISP3X_RAWAWB_XY_DETC_NOR_Y_2);
2035
2036 isp3_param_write(params_vdev,
2037 ISP_PACK_2SHORT(arg->big_x0_2, arg->big_x1_2),
2038 ISP3X_RAWAWB_XY_DETC_BIG_X_2);
2039
2040 isp3_param_write(params_vdev,
2041 ISP_PACK_2SHORT(arg->big_y0_2, arg->big_y1_2),
2042 ISP3X_RAWAWB_XY_DETC_BIG_Y_2);
2043
2044 isp3_param_write(params_vdev,
2045 ISP_PACK_2SHORT(arg->nor_x0_3, arg->nor_x1_3),
2046 ISP3X_RAWAWB_XY_DETC_NOR_X_3);
2047
2048 isp3_param_write(params_vdev,
2049 ISP_PACK_2SHORT(arg->nor_y0_3, arg->nor_y1_3),
2050 ISP3X_RAWAWB_XY_DETC_NOR_Y_3);
2051
2052 isp3_param_write(params_vdev,
2053 ISP_PACK_2SHORT(arg->big_x0_3, arg->big_x1_3),
2054 ISP3X_RAWAWB_XY_DETC_BIG_X_3);
2055
2056 isp3_param_write(params_vdev,
2057 ISP_PACK_2SHORT(arg->big_y0_3, arg->big_y1_3),
2058 ISP3X_RAWAWB_XY_DETC_BIG_Y_3);
2059
2060 value = (arg->exc_wp_region0_excen & 0x3) |
2061 !!arg->exc_wp_region0_measen << 2 |
2062 !!arg->exc_wp_region0_domain << 3 |
2063 (arg->exc_wp_region1_excen & 0x3) << 4 |
2064 !!arg->exc_wp_region1_measen << 6 |
2065 !!arg->exc_wp_region1_domain << 7 |
2066 (arg->exc_wp_region2_excen & 0x3) << 8 |
2067 !!arg->exc_wp_region2_measen << 10 |
2068 !!arg->exc_wp_region2_domain << 11 |
2069 (arg->exc_wp_region3_excen & 0x3) << 12 |
2070 !!arg->exc_wp_region3_measen << 14 |
2071 !!arg->exc_wp_region3_domain << 15 |
2072 (arg->exc_wp_region4_excen & 0x3) << 16 |
2073 !!arg->exc_wp_region4_domain << 19 |
2074 (arg->exc_wp_region5_excen & 0x3) << 20 |
2075 !!arg->exc_wp_region5_domain << 23 |
2076 (arg->exc_wp_region6_excen & 0x3) << 24 |
2077 !!arg->exc_wp_region6_domain << 27 |
2078 !!arg->multiwindow_en << 31;
2079 isp3_param_write(params_vdev, value, ISP3X_RAWAWB_MULTIWINDOW_EXC_CTRL);
2080
2081 isp3_param_write(params_vdev,
2082 ISP_PACK_2SHORT(arg->multiwindow0_h_offs,
2083 arg->multiwindow0_v_offs),
2084 ISP3X_RAWAWB_MULTIWINDOW0_OFFS);
2085 isp3_param_write(params_vdev,
2086 ISP_PACK_2SHORT(arg->multiwindow0_h_size,
2087 arg->multiwindow0_v_size),
2088 ISP3X_RAWAWB_MULTIWINDOW0_SIZE);
2089 isp3_param_write(params_vdev,
2090 ISP_PACK_2SHORT(arg->multiwindow1_h_offs,
2091 arg->multiwindow1_v_offs),
2092 ISP3X_RAWAWB_MULTIWINDOW1_OFFS);
2093 isp3_param_write(params_vdev,
2094 ISP_PACK_2SHORT(arg->multiwindow1_h_size,
2095 arg->multiwindow1_v_size),
2096 ISP3X_RAWAWB_MULTIWINDOW1_SIZE);
2097 isp3_param_write(params_vdev,
2098 ISP_PACK_2SHORT(arg->multiwindow2_h_offs,
2099 arg->multiwindow2_v_offs),
2100 ISP3X_RAWAWB_MULTIWINDOW2_OFFS);
2101 isp3_param_write(params_vdev,
2102 ISP_PACK_2SHORT(arg->multiwindow2_h_size,
2103 arg->multiwindow2_v_size),
2104 ISP3X_RAWAWB_MULTIWINDOW2_SIZE);
2105 isp3_param_write(params_vdev,
2106 ISP_PACK_2SHORT(arg->multiwindow3_h_offs,
2107 arg->multiwindow3_v_offs),
2108 ISP3X_RAWAWB_MULTIWINDOW3_OFFS);
2109 isp3_param_write(params_vdev,
2110 ISP_PACK_2SHORT(arg->multiwindow3_h_size,
2111 arg->multiwindow3_v_size),
2112 ISP3X_RAWAWB_MULTIWINDOW3_SIZE);
2113
2114 isp3_param_write(params_vdev,
2115 ISP_PACK_2SHORT(arg->exc_wp_region0_xu0,
2116 arg->exc_wp_region0_xu1),
2117 ISP3X_RAWAWB_EXC_WP_REGION0_XU);
2118
2119 isp3_param_write(params_vdev,
2120 ISP_PACK_2SHORT(arg->exc_wp_region0_yv0,
2121 arg->exc_wp_region0_yv1),
2122 ISP3X_RAWAWB_EXC_WP_REGION0_YV);
2123
2124 isp3_param_write(params_vdev,
2125 ISP_PACK_2SHORT(arg->exc_wp_region1_xu0,
2126 arg->exc_wp_region1_xu1),
2127 ISP3X_RAWAWB_EXC_WP_REGION1_XU);
2128
2129 isp3_param_write(params_vdev,
2130 ISP_PACK_2SHORT(arg->exc_wp_region1_yv0,
2131 arg->exc_wp_region1_yv1),
2132 ISP3X_RAWAWB_EXC_WP_REGION1_YV);
2133
2134 isp3_param_write(params_vdev,
2135 ISP_PACK_2SHORT(arg->exc_wp_region2_xu0,
2136 arg->exc_wp_region2_xu1),
2137 ISP3X_RAWAWB_EXC_WP_REGION2_XU);
2138
2139 isp3_param_write(params_vdev,
2140 ISP_PACK_2SHORT(arg->exc_wp_region2_yv0,
2141 arg->exc_wp_region2_yv1),
2142 ISP3X_RAWAWB_EXC_WP_REGION2_YV);
2143
2144 isp3_param_write(params_vdev,
2145 ISP_PACK_2SHORT(arg->exc_wp_region3_xu0,
2146 arg->exc_wp_region3_xu1),
2147 ISP3X_RAWAWB_EXC_WP_REGION3_XU);
2148
2149 isp3_param_write(params_vdev,
2150 ISP_PACK_2SHORT(arg->exc_wp_region3_yv0,
2151 arg->exc_wp_region3_yv1),
2152 ISP3X_RAWAWB_EXC_WP_REGION3_YV);
2153
2154 isp3_param_write(params_vdev,
2155 ISP_PACK_2SHORT(arg->exc_wp_region4_xu0,
2156 arg->exc_wp_region4_xu1),
2157 ISP3X_RAWAWB_EXC_WP_REGION4_XU);
2158
2159 isp3_param_write(params_vdev,
2160 ISP_PACK_2SHORT(arg->exc_wp_region4_yv0,
2161 arg->exc_wp_region4_yv1),
2162 ISP3X_RAWAWB_EXC_WP_REGION4_YV);
2163
2164 isp3_param_write(params_vdev,
2165 ISP_PACK_2SHORT(arg->exc_wp_region5_xu0,
2166 arg->exc_wp_region5_xu1),
2167 ISP3X_RAWAWB_EXC_WP_REGION5_XU);
2168
2169 isp3_param_write(params_vdev,
2170 ISP_PACK_2SHORT(arg->exc_wp_region5_yv0,
2171 arg->exc_wp_region5_yv1),
2172 ISP3X_RAWAWB_EXC_WP_REGION5_YV);
2173
2174 isp3_param_write(params_vdev,
2175 ISP_PACK_2SHORT(arg->exc_wp_region6_xu0,
2176 arg->exc_wp_region6_xu1),
2177 ISP3X_RAWAWB_EXC_WP_REGION6_XU);
2178
2179 isp3_param_write(params_vdev,
2180 ISP_PACK_2SHORT(arg->exc_wp_region6_yv0,
2181 arg->exc_wp_region6_yv1),
2182 ISP3X_RAWAWB_EXC_WP_REGION6_YV);
2183
2184 isp3_param_write(params_vdev,
2185 ISP_PACK_4BYTE(arg->exc_wp_region0_weight,
2186 arg->exc_wp_region1_weight,
2187 arg->exc_wp_region2_weight,
2188 arg->exc_wp_region3_weight),
2189 ISP32_RAWAWB_EXC_WP_WEIGHT0_3);
2190
2191 isp3_param_write(params_vdev,
2192 ISP_PACK_4BYTE(arg->exc_wp_region4_weight,
2193 arg->exc_wp_region5_weight,
2194 arg->exc_wp_region6_weight, 0),
2195 ISP32_RAWAWB_EXC_WP_WEIGHT4_6);
2196
2197 if (params_vdev->dev->isp_ver == ISP_V32) {
2198 if (params_vdev->dev->hw_dev->is_single)
2199 isp_rawawb_cfg_sram(params_vdev, arg, false);
2200 else
2201 memcpy(arg_rec->wp_blk_wei_w, arg->wp_blk_wei_w,
2202 ISP32_RAWAWB_WEIGHT_NUM);
2203 } else {
2204 for (i = 0; i < ISP32L_RAWAWB_WEIGHT_NUM; i++)
2205 isp3_param_write(params_vdev, arg->win_weight[i],
2206 ISP32L_RAWAWB_WIN_WEIGHT_0 + i * 4);
2207 }
2208
2209 /* avoid to override the old enable value */
2210 value = isp3_param_read_cache(params_vdev, ISP3X_RAWAWB_CTRL);
2211 value &= (ISP32_MODULE_EN |
2212 ISP32_RAWAWB_2DDR_PATH_EN |
2213 ISP32_RAWAWB_2DDR_PATH_DS);
2214 value |= !!arg->low12bit_val << 28 |
2215 !!arg->yuv3d_en1 << 26 |
2216 !!arg->xy_en1 << 25 |
2217 !!arg->uv_en1 << 24 |
2218 (arg->light_num & 0x7) << 20 |
2219 !!arg->rawlsc_bypass_en << 19 |
2220 !!arg->wind_size << 18 |
2221 !!arg->in_overexposure_check_en << 17 |
2222 !!arg->in_rshift_to_12bit_en << 16 |
2223 (arg->yuv3d_ls_idx3 & 0x7) << 13 |
2224 (arg->yuv3d_ls_idx2 & 0x7) << 10 |
2225 (arg->yuv3d_ls_idx1 & 0x7) << 7 |
2226 (arg->yuv3d_ls_idx0 & 0x7) << 4 |
2227 !!arg->yuv3d_en0 << 3 |
2228 !!arg->xy_en0 << 2 |
2229 !!arg->uv_en0 << 1;
2230 isp3_param_write(params_vdev, value, ISP3X_RAWAWB_CTRL);
2231
2232 mask = ISP32_DRC2AWB_SEL | ISP32_BNR2AWB_SEL | ISP3X_RAWAWB_SEL(3);
2233 val = ISP3X_RAWAWB_SEL(arg->rawawb_sel) |
2234 (arg->bnr2awb_sel & 0x1) << 26 | (arg->drc2awb_sel & 0x1) << 27;
2235 value = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH);
2236 if ((value & mask) != val) {
2237 value &= ~mask;
2238 value |= val;
2239 isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH);
2240 }
2241 }
2242
2243 static void
isp_rawawb_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2244 isp_rawawb_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
2245 {
2246 u32 awb_ctrl;
2247
2248 awb_ctrl = isp3_param_read_cache(params_vdev, ISP3X_RAWAWB_CTRL);
2249 awb_ctrl &= ~ISP32_REG_WR_MASK;
2250 if (en)
2251 awb_ctrl |= ISP32_MODULE_EN;
2252 else
2253 awb_ctrl &= ~ISP32_MODULE_EN;
2254
2255 isp3_param_write(params_vdev, awb_ctrl, ISP3X_RAWAWB_CTRL);
2256 }
2257
2258 static void
isp_rawhstlite_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistlite_cfg * arg)2259 isp_rawhstlite_config(struct rkisp_isp_params_vdev *params_vdev,
2260 const struct isp2x_rawhistlite_cfg *arg)
2261 {
2262 u32 i;
2263 u32 value;
2264 u32 hist_ctrl;
2265 u32 block_hsize, block_vsize;
2266
2267 /* avoid to override the old enable value */
2268 hist_ctrl = isp3_param_read(params_vdev, ISP3X_RAWHIST_LITE_CTRL);
2269 hist_ctrl &= ISP3X_RAWHIST_EN;
2270 hist_ctrl = hist_ctrl |
2271 ISP3X_RAWHIST_MODE(arg->mode) |
2272 ISP3X_RAWHIST_STEPSIZE(arg->stepsize);
2273 if (params_vdev->dev->isp_ver == ISP_V32)
2274 hist_ctrl |= ISP3X_RAWHIST_DATASEL(arg->data_sel) |
2275 ISP3X_RAWHIST_WATERLINE(arg->waterline);
2276 isp3_param_write(params_vdev, hist_ctrl, ISP3X_RAWHIST_LITE_CTRL);
2277
2278 isp3_param_write(params_vdev,
2279 ISP_PACK_2SHORT(arg->win.h_offs, arg->win.v_offs),
2280 ISP3X_RAWHIST_LITE_OFFS);
2281
2282 block_hsize = arg->win.h_size / ISP32_RAWHISTLITE_ROW_NUM - 1;
2283 block_vsize = arg->win.v_size / ISP32_RAWHISTLITE_COLUMN_NUM - 1;
2284 block_hsize &= 0xFFFE;
2285 block_vsize &= 0xFFFE;
2286 isp3_param_write(params_vdev,
2287 ISP_PACK_2SHORT(block_hsize, block_vsize),
2288 ISP3X_RAWHIST_LITE_SIZE);
2289
2290 isp3_param_write(params_vdev,
2291 ISP_PACK_4BYTE(arg->rcc, arg->gcc, arg->bcc, arg->off),
2292 ISP3X_RAWHIST_LITE_RAW2Y_CC);
2293
2294 for (i = 0; i < (ISP32_RAWHISTLITE_WEIGHT_REG_SIZE / 4); i++) {
2295 value = ISP_PACK_4BYTE(arg->weight[4 * i + 0],
2296 arg->weight[4 * i + 1],
2297 arg->weight[4 * i + 2],
2298 arg->weight[4 * i + 3]);
2299 isp3_param_write(params_vdev, value,
2300 ISP3X_RAWHIST_LITE_WEIGHT + 4 * i);
2301 }
2302
2303 value = ISP_PACK_4BYTE(arg->weight[4 * i + 0], 0, 0, 0);
2304 isp3_param_write(params_vdev, value,
2305 ISP3X_RAWHIST_LITE_WEIGHT + 4 * i);
2306 }
2307
2308 static void
isp_rawhstlite_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2309 isp_rawhstlite_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
2310 {
2311 u32 hist_ctrl;
2312
2313 hist_ctrl = isp3_param_read(params_vdev, ISP3X_RAWHIST_LITE_CTRL);
2314 hist_ctrl &= ~(ISP32_MODULE_EN | ISP32_REG_WR_MASK);
2315
2316 if (en)
2317 hist_ctrl |= ISP32_MODULE_EN;
2318
2319 isp3_param_write(params_vdev, hist_ctrl, ISP3X_RAWHIST_LITE_CTRL);
2320 }
2321
2322 static void
isp_rawhstbig_cfg_sram(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg,u32 blk_no,bool is_check)2323 isp_rawhstbig_cfg_sram(struct rkisp_isp_params_vdev *params_vdev,
2324 const struct isp2x_rawhistbig_cfg *arg,
2325 u32 blk_no, bool is_check)
2326 {
2327 u32 i, j, wnd_num_idx, value;
2328 u8 weight15x15[ISP32_RAWHISTBIG_WEIGHT_REG_SIZE];
2329 const u32 hist_wnd_num[] = {5, 5, 15, 15};
2330 u32 addr;
2331
2332 switch (blk_no) {
2333 case 1:
2334 addr = ISP3X_RAWHIST_BIG2_BASE;
2335 break;
2336 case 2:
2337 addr = ISP3X_RAWHIST_BIG3_BASE;
2338 break;
2339 case 0:
2340 default:
2341 addr = ISP3X_RAWHIST_BIG1_BASE;
2342 break;
2343 }
2344
2345 value = ISP3X_RAWHIST_EN;
2346 if (is_check &&
2347 !(isp3_param_read(params_vdev, addr + ISP3X_RAWHIST_BIG_CTRL) & value))
2348 return;
2349
2350 wnd_num_idx = arg->wnd_num;
2351 memset(weight15x15, 0, sizeof(weight15x15));
2352 for (i = 0; i < hist_wnd_num[wnd_num_idx]; i++) {
2353 for (j = 0; j < hist_wnd_num[wnd_num_idx]; j++) {
2354 weight15x15[i * ISP32_RAWHISTBIG_ROW_NUM + j] =
2355 arg->weight[i * hist_wnd_num[wnd_num_idx] + j];
2356 }
2357 }
2358
2359 for (i = 0; i < (ISP32_RAWHISTBIG_WEIGHT_REG_SIZE / 5); i++) {
2360 value = (weight15x15[5 * i + 0] & 0x3f) |
2361 (weight15x15[5 * i + 1] & 0x3f) << 6 |
2362 (weight15x15[5 * i + 2] & 0x3f) << 12 |
2363 (weight15x15[5 * i + 3] & 0x3f) << 18 |
2364 (weight15x15[5 * i + 4] & 0x3f) << 24;
2365 isp3_param_write_direct(params_vdev, value,
2366 addr + ISP3X_RAWHIST_BIG_WEIGHT_BASE);
2367 }
2368 }
2369
2370 static void
isp_rawhstbig_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg,u32 blk_no)2371 isp_rawhstbig_config(struct rkisp_isp_params_vdev *params_vdev,
2372 const struct isp2x_rawhistbig_cfg *arg, u32 blk_no)
2373 {
2374 struct isp32_isp_params_cfg *params_rec = params_vdev->isp32_params;
2375 struct rkisp_device *dev = params_vdev->dev;
2376 struct isp2x_rawhistbig_cfg *arg_rec;
2377 u32 hist_ctrl, block_hsize, block_vsize, wnd_num_idx;
2378 const u32 hist_wnd_num[] = {5, 5, 15, 15};
2379 u32 addr;
2380
2381 switch (blk_no) {
2382 case 1:
2383 addr = ISP3X_RAWHIST_BIG2_BASE;
2384 arg_rec = ¶ms_rec->meas.rawhist1;
2385 break;
2386 case 2:
2387 addr = ISP3X_RAWHIST_BIG3_BASE;
2388 arg_rec = ¶ms_rec->meas.rawhist2;
2389 break;
2390 case 0:
2391 default:
2392 addr = ISP3X_RAWHIST_BIG1_BASE;
2393 arg_rec = ¶ms_rec->meas.rawhist3;
2394 break;
2395 }
2396
2397 wnd_num_idx = arg->wnd_num;
2398 /* avoid to override the old enable value */
2399 hist_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWHIST_BIG_CTRL);
2400 hist_ctrl &= ISP3X_RAWHIST_EN;
2401 hist_ctrl = hist_ctrl |
2402 ISP3X_RAWHIST_MODE(arg->mode) |
2403 ISP3X_RAWHIST_WND_NUM(arg->wnd_num) |
2404 ISP3X_RAWHIST_STEPSIZE(arg->stepsize);
2405 if (params_vdev->dev->isp_ver == ISP_V32)
2406 hist_ctrl |= ISP3X_RAWHIST_DATASEL(arg->data_sel) |
2407 ISP3X_RAWHIST_WATERLINE(arg->waterline);
2408 isp3_param_write(params_vdev, hist_ctrl, addr + ISP3X_RAWHIST_BIG_CTRL);
2409
2410 isp3_param_write(params_vdev,
2411 ISP_PACK_2SHORT(arg->win.h_offs, arg->win.v_offs),
2412 addr + ISP3X_RAWHIST_BIG_OFFS);
2413
2414 block_hsize = arg->win.h_size / hist_wnd_num[wnd_num_idx] - 1;
2415 block_vsize = arg->win.v_size / hist_wnd_num[wnd_num_idx] - 1;
2416 block_hsize &= 0xFFFE;
2417 block_vsize &= 0xFFFE;
2418 isp3_param_write(params_vdev,
2419 ISP_PACK_2SHORT(block_hsize, block_vsize),
2420 addr + ISP3X_RAWHIST_BIG_SIZE);
2421
2422 isp3_param_write(params_vdev,
2423 ISP_PACK_4BYTE(arg->rcc, arg->gcc, arg->bcc, arg->off),
2424 addr + ISP3X_RAWHIST_BIG_RAW2Y_CC);
2425
2426 if (dev->hw_dev->is_single)
2427 isp_rawhstbig_cfg_sram(params_vdev, arg, blk_no, false);
2428 else
2429 *arg_rec = *arg;
2430 }
2431
2432 static void
isp_rawhstbig_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 blk_no)2433 isp_rawhstbig_enable(struct rkisp_isp_params_vdev *params_vdev,
2434 bool en, u32 blk_no)
2435 {
2436 u32 hist_ctrl;
2437 u32 addr;
2438
2439 switch (blk_no) {
2440 case 1:
2441 addr = ISP3X_RAWHIST_BIG2_BASE;
2442 break;
2443 case 2:
2444 addr = ISP3X_RAWHIST_BIG3_BASE;
2445 break;
2446 case 0:
2447 default:
2448 addr = ISP3X_RAWHIST_BIG1_BASE;
2449 break;
2450 }
2451
2452 hist_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWHIST_BIG_CTRL);
2453 hist_ctrl &= ~(ISP3X_RAWHIST_EN | ISP32_REG_WR_MASK);
2454 if (en)
2455 hist_ctrl |= ISP3X_RAWHIST_EN;
2456
2457 isp3_param_write(params_vdev, hist_ctrl, addr + ISP3X_RAWHIST_BIG_CTRL);
2458 }
2459
2460 static void
isp_rawhst1_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg)2461 isp_rawhst1_config(struct rkisp_isp_params_vdev *params_vdev,
2462 const struct isp2x_rawhistbig_cfg *arg)
2463 {
2464 isp_rawhstbig_config(params_vdev, arg, 1);
2465 }
2466
2467 static void
isp_rawhst1_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2468 isp_rawhst1_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
2469 {
2470 isp_rawhstbig_enable(params_vdev, en, 1);
2471 }
2472
2473 static void
isp_rawhst2_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg)2474 isp_rawhst2_config(struct rkisp_isp_params_vdev *params_vdev,
2475 const struct isp2x_rawhistbig_cfg *arg)
2476 {
2477 isp_rawhstbig_config(params_vdev, arg, 2);
2478 }
2479
2480 static void
isp_rawhst2_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2481 isp_rawhst2_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
2482 {
2483 isp_rawhstbig_enable(params_vdev, en, 2);
2484 }
2485
2486 static void
isp_rawhst3_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg)2487 isp_rawhst3_config(struct rkisp_isp_params_vdev *params_vdev,
2488 const struct isp2x_rawhistbig_cfg *arg)
2489 {
2490 isp_rawhstbig_config(params_vdev, arg, 0);
2491 }
2492
2493 static void
isp_rawhst3_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2494 isp_rawhst3_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
2495 {
2496 isp_rawhstbig_enable(params_vdev, en, 0);
2497 }
2498
2499 static void
isp_hdrmge_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp32_hdrmge_cfg * arg,enum rkisp_params_type type)2500 isp_hdrmge_config(struct rkisp_isp_params_vdev *params_vdev,
2501 const struct isp32_hdrmge_cfg *arg,
2502 enum rkisp_params_type type)
2503 {
2504 u32 value;
2505 int i;
2506
2507 if (type == RKISP_PARAMS_SHD || type == RKISP_PARAMS_ALL) {
2508 value = ISP_PACK_2SHORT(arg->gain0, arg->gain0_inv);
2509 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_GAIN0);
2510
2511 value = ISP_PACK_2SHORT(arg->gain1, arg->gain1_inv);
2512 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_GAIN1);
2513
2514 value = arg->gain2;
2515 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_GAIN2);
2516
2517 value = isp3_param_read_cache(params_vdev, ISP3X_HDRMGE_CTRL);
2518 if (arg->s_base)
2519 value |= BIT(1);
2520 else
2521 value &= ~BIT(1);
2522 if (arg->each_raw_en)
2523 value |= BIT(6);
2524 else
2525 value &= ~BIT(6);
2526 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_CTRL);
2527 }
2528
2529 if (type == RKISP_PARAMS_IMD || type == RKISP_PARAMS_ALL) {
2530 value = ISP_PACK_4BYTE(arg->ms_dif_0p8, arg->ms_diff_0p15,
2531 arg->lm_dif_0p9, arg->lm_dif_0p15);
2532 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_LIGHTZ);
2533 value = (arg->ms_scl & 0x7ff) |
2534 (arg->ms_thd0 & 0x3ff) << 12 |
2535 (arg->ms_thd1 & 0x3ff) << 22;
2536 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_MS_DIFF);
2537 value = (arg->lm_scl & 0x7ff) |
2538 (arg->lm_thd0 & 0x3ff) << 12 |
2539 (arg->lm_thd1 & 0x3ff) << 22;
2540 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_LM_DIFF);
2541
2542 for (i = 0; i < ISP32_HDRMGE_L_CURVE_NUM; i++) {
2543 value = ISP_PACK_2SHORT(arg->curve.curve_0[i], arg->curve.curve_1[i]);
2544 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_DIFF_Y0 + 4 * i);
2545 }
2546
2547 for (i = 0; i < ISP32_HDRMGE_E_CURVE_NUM; i++) {
2548 value = (arg->l_raw1[i] & 0x3ff) << 20 |
2549 (arg->l_raw0[i] & 0x3ff) << 10 |
2550 (arg->e_y[i] & 0x3ff);
2551 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_OVER_Y0 + 4 * i);
2552 }
2553
2554 value = ISP_PACK_2SHORT(arg->each_raw_gain0, arg->each_raw_gain1);
2555 isp3_param_write(params_vdev, value, ISP32_HDRMGE_EACH_GAIN);
2556 }
2557 }
2558
2559 static void
isp_hdrmge_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2560 isp_hdrmge_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
2561 {
2562 }
2563
2564 static void
isp_hdrdrc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp32_drc_cfg * arg,enum rkisp_params_type type)2565 isp_hdrdrc_config(struct rkisp_isp_params_vdev *params_vdev,
2566 const struct isp32_drc_cfg *arg,
2567 enum rkisp_params_type type)
2568 {
2569 u32 i, value;
2570
2571 if (type == RKISP_PARAMS_IMD)
2572 return;
2573
2574 value = (arg->offset_pow2 & 0x0F) << 28 |
2575 (arg->compres_scl & 0x1FFF) << 14 |
2576 (arg->position & 0x03FFF);
2577 isp3_param_write(params_vdev, value, ISP3X_DRC_CTRL1);
2578
2579 value = arg->delta_scalein << 24 |
2580 (arg->hpdetail_ratio & 0xFFF) << 12 |
2581 (arg->lpdetail_ratio & 0xFFF);
2582 isp3_param_write(params_vdev, value, ISP3X_DRC_LPRATIO);
2583
2584 value = ISP_PACK_4BYTE(arg->bilat_wt_off, 0, arg->weipre_frame, arg->weicur_pix);
2585 isp3_param_write(params_vdev, value, ISP3X_DRC_EXPLRATIO);
2586
2587 value = (arg->force_sgm_inv0 & 0xFFFF) << 16 |
2588 arg->motion_scl << 8 | arg->edge_scl;
2589 isp3_param_write(params_vdev, value, ISP3X_DRC_SIGMA);
2590
2591 value = ISP_PACK_2SHORT(arg->space_sgm_inv0, arg->space_sgm_inv1);
2592 isp3_param_write(params_vdev, value, ISP3X_DRC_SPACESGM);
2593
2594 value = ISP_PACK_2SHORT(arg->range_sgm_inv0, arg->range_sgm_inv1);
2595 isp3_param_write(params_vdev, value, ISP3X_DRC_RANESGM);
2596
2597 value = (arg->weig_bilat & 0x1f) | (arg->weig_maxl & 0x1f) << 8 |
2598 (arg->bilat_soft_thd & 0x3fff) << 16;
2599 if (arg->enable_soft_thd)
2600 value |= BIT(31);
2601 isp3_param_write(params_vdev, value, ISP3X_DRC_BILAT);
2602
2603 for (i = 0; i < ISP32_DRC_Y_NUM / 2; i++) {
2604 value = ISP_PACK_2SHORT(arg->gain_y[2 * i],
2605 arg->gain_y[2 * i + 1]);
2606 isp3_param_write(params_vdev, value, ISP3X_DRC_GAIN_Y0 + 4 * i);
2607 }
2608 value = ISP_PACK_2SHORT(arg->gain_y[2 * i], 0);
2609 isp3_param_write(params_vdev, value, ISP3X_DRC_GAIN_Y0 + 4 * i);
2610
2611 for (i = 0; i < ISP32_DRC_Y_NUM / 2; i++) {
2612 value = ISP_PACK_2SHORT(arg->compres_y[2 * i],
2613 arg->compres_y[2 * i + 1]);
2614 isp3_param_write(params_vdev, value, ISP3X_DRC_COMPRES_Y0 + 4 * i);
2615 }
2616 value = ISP_PACK_2SHORT(arg->compres_y[2 * i], 0);
2617 isp3_param_write(params_vdev, value, ISP3X_DRC_COMPRES_Y0 + 4 * i);
2618
2619 for (i = 0; i < ISP32_DRC_Y_NUM / 2; i++) {
2620 value = ISP_PACK_2SHORT(arg->scale_y[2 * i],
2621 arg->scale_y[2 * i + 1]);
2622 isp3_param_write(params_vdev, value, ISP3X_DRC_SCALE_Y0 + 4 * i);
2623 }
2624 value = ISP_PACK_2SHORT(arg->scale_y[2 * i], 0);
2625 isp3_param_write(params_vdev, value, ISP3X_DRC_SCALE_Y0 + 4 * i);
2626
2627 if (params_vdev->dev->isp_ver == ISP_V32)
2628 value = ISP_PACK_2SHORT(arg->min_ogain, arg->iir_weight);
2629 else
2630 value = ISP_PACK_2SHORT(arg->min_ogain, 0);
2631 isp3_param_write(params_vdev, value, ISP3X_DRC_IIRWG_GAIN);
2632
2633 value = arg->gas_t & 0x1fff;
2634 isp3_param_write(params_vdev, value, ISP32_DRC_LUM3X2_CTRL);
2635
2636 value = ISP_PACK_4BYTE(arg->gas_l0, arg->gas_l1, arg->gas_l2, arg->gas_l3);
2637 isp3_param_write(params_vdev, value, ISP32_DRC_LUM3X2_GAS);
2638 }
2639
2640 static void
isp_hdrdrc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2641 isp_hdrdrc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
2642 {
2643 u32 value;
2644 bool real_en;
2645
2646 value = isp3_param_read(params_vdev, ISP3X_DRC_CTRL0);
2647 real_en = !!(value & ISP32_MODULE_EN);
2648 if ((en && real_en) || (!en && !real_en))
2649 return;
2650
2651 if (en) {
2652 value |= ISP32_MODULE_EN;
2653 isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1,
2654 ISP3X_ADRC_FST_FRAME);
2655 } else {
2656 value = 0;
2657 isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(12));
2658 }
2659 isp3_param_write(params_vdev, value, ISP3X_DRC_CTRL0);
2660 }
2661
2662 static void
isp_gic_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_gic_cfg * arg)2663 isp_gic_config(struct rkisp_isp_params_vdev *params_vdev,
2664 const struct isp21_gic_cfg *arg)
2665 {
2666 u32 value;
2667 s32 i;
2668
2669 value = (arg->regmingradthrdark2 & 0x03FF) << 20 |
2670 (arg->regmingradthrdark1 & 0x03FF) << 10 |
2671 (arg->regminbusythre & 0x03FF);
2672 isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA1);
2673
2674 value = (arg->regdarkthre & 0x07FF) << 21 |
2675 (arg->regmaxcorvboth & 0x03FF) << 11 |
2676 (arg->regdarktthrehi & 0x07FF);
2677 isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA2);
2678
2679 value = (arg->regkgrad2dark & 0x0F) << 28 |
2680 (arg->regkgrad1dark & 0x0F) << 24 |
2681 (arg->regstrengthglobal_fix & 0xFF) << 16 |
2682 (arg->regdarkthrestep & 0x0F) << 12 |
2683 (arg->regkgrad2 & 0x0F) << 8 |
2684 (arg->regkgrad1 & 0x0F) << 4 |
2685 (arg->reggbthre & 0x0F);
2686 isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA3);
2687
2688 value = (arg->regmaxcorv & 0x03FF) << 20 |
2689 (arg->regmingradthr2 & 0x03FF) << 10 |
2690 (arg->regmingradthr1 & 0x03FF);
2691 isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA4);
2692
2693 value = (arg->gr_ratio & 0x03) << 28 |
2694 (arg->noise_scale & 0x7F) << 12 |
2695 (arg->noise_base & 0xFFF);
2696 isp3_param_write(params_vdev, value, ISP3X_GIC_NOISE_PARA1);
2697
2698 value = arg->diff_clip & 0x7fff;
2699 isp3_param_write(params_vdev, value, ISP3X_GIC_NOISE_PARA2);
2700
2701 for (i = 0; i < ISP32_GIC_SIGMA_Y_NUM / 2; i++) {
2702 value = ISP_PACK_2SHORT(arg->sigma_y[2 * i], arg->sigma_y[2 * i + 1]);
2703 isp3_param_write(params_vdev, value, ISP3X_GIC_SIGMA_VALUE0 + 4 * i);
2704 }
2705 value = ISP_PACK_2SHORT(arg->sigma_y[2 * i], 0);
2706 isp3_param_write(params_vdev, value, ISP3X_GIC_SIGMA_VALUE0 + 4 * i);
2707 }
2708
2709 static void
isp_gic_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2710 isp_gic_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
2711 {
2712 u32 value = 0;
2713
2714 if (en)
2715 value |= ISP32_MODULE_EN;
2716 isp3_param_write(params_vdev, value, ISP3X_GIC_CONTROL);
2717 }
2718
2719 static void
isp_dhaz_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp32_dhaz_cfg * arg)2720 isp_dhaz_config(struct rkisp_isp_params_vdev *params_vdev,
2721 const struct isp32_dhaz_cfg *arg)
2722 {
2723 u32 i, value, ctrl;
2724
2725 ctrl = isp3_param_read(params_vdev, ISP3X_DHAZ_CTRL);
2726 ctrl &= ISP3X_DHAZ_ENMUX;
2727
2728 ctrl |= !!arg->enh_luma_en << 28 | !!arg->color_deviate_en << 27 |
2729 !!arg->round_en << 26 | !!arg->soft_wr_en << 25 |
2730 !!arg->enhance_en << 20 | !!arg->air_lc_en << 16 |
2731 !!arg->hpara_en << 12 | !!arg->hist_en << 8 |
2732 !!arg->dc_en << 4;
2733 /* merge dual unite isp params at frame end */
2734 if (arg->soft_wr_en) {
2735 for (i = 0; i < ISP32_DHAZ_HIST_WR_NUM / 3; i++) {
2736 value = (arg->hist_wr[i * 3] & 0x3ff) |
2737 (arg->hist_wr[i * 3 + 1] & 0x3ff) << 10 |
2738 (arg->hist_wr[i * 3 + 2] & 0x3ff) << 20;
2739 isp3_param_write(params_vdev, value, ISP3X_DHAZ_HIST_WR0 + i * 4);
2740 }
2741 value = arg->hist_wr[i * 3] & 0x3ff;
2742 isp3_param_write(params_vdev, value, ISP3X_DHAZ_HIST_WR0 + i * 4);
2743 }
2744 isp3_param_write(params_vdev, ctrl, ISP3X_DHAZ_CTRL);
2745
2746 value = ISP_PACK_4BYTE(arg->dc_min_th, arg->dc_max_th,
2747 arg->yhist_th, arg->yblk_th);
2748 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP0);
2749
2750 value = ISP_PACK_4BYTE(arg->bright_min, arg->bright_max,
2751 arg->wt_max, 0);
2752 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP1);
2753
2754 value = ISP_PACK_4BYTE(arg->air_min, arg->air_max,
2755 arg->dark_th, arg->tmax_base);
2756 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP2);
2757
2758 value = ISP_PACK_2SHORT(arg->tmax_off, arg->tmax_max);
2759 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP_TMAX);
2760
2761 value = (arg->hist_min & 0xFFFF) << 16 |
2762 (arg->hist_th_off & 0xFF) << 8 |
2763 (arg->hist_k & 0x1F);
2764 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP_HIST0);
2765
2766 value = ISP_PACK_2SHORT(arg->hist_scale, arg->hist_gratio);
2767 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP_HIST1);
2768
2769 value = ISP_PACK_2SHORT(arg->enhance_chroma, arg->enhance_value);
2770 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ENHANCE);
2771
2772 value = (arg->iir_wt_sigma & 0x07FF) << 16 |
2773 (arg->iir_sigma & 0xFF) << 8 |
2774 (arg->stab_fnum & 0x1F);
2775 isp3_param_write(params_vdev, value, ISP3X_DHAZ_IIR0);
2776
2777 value = (arg->iir_pre_wet & 0x0F) << 24 |
2778 (arg->iir_tmax_sigma & 0x7FF) << 8 |
2779 (arg->iir_air_sigma & 0xFF);
2780 isp3_param_write(params_vdev, value, ISP3X_DHAZ_IIR1);
2781
2782 value = (arg->cfg_wt & 0x01FF) << 16 |
2783 (arg->cfg_air & 0xFF) << 8 |
2784 (arg->cfg_alpha & 0xFF);
2785 isp3_param_write(params_vdev, value, ISP3X_DHAZ_SOFT_CFG0);
2786
2787 value = ISP_PACK_2SHORT(arg->cfg_tmax, arg->cfg_gratio);
2788 isp3_param_write(params_vdev, value, ISP3X_DHAZ_SOFT_CFG1);
2789
2790 value = (arg->range_sima & 0x01FF) << 16 |
2791 (arg->space_sigma_pre & 0xFF) << 8 |
2792 (arg->space_sigma_cur & 0xFF);
2793 isp3_param_write(params_vdev, value, ISP3X_DHAZ_BF_SIGMA);
2794
2795 value = ISP_PACK_2SHORT(arg->bf_weight, arg->dc_weitcur);
2796 isp3_param_write(params_vdev, value, ISP3X_DHAZ_BF_WET);
2797
2798 for (i = 0; i < ISP32_DHAZ_ENH_CURVE_NUM / 2; i++) {
2799 value = ISP_PACK_2SHORT(arg->enh_curve[2 * i], arg->enh_curve[2 * i + 1]);
2800 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ENH_CURVE0 + 4 * i);
2801 }
2802 value = ISP_PACK_2SHORT(arg->enh_curve[2 * i], 0);
2803 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ENH_CURVE0 + 4 * i);
2804
2805 value = ISP_PACK_4BYTE(arg->gaus_h0, arg->gaus_h1, arg->gaus_h2, 0);
2806 isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAUS);
2807
2808 for (i = 0; i < ISP32_DHAZ_SIGMA_IDX_NUM / 4; i++) {
2809 value = ISP_PACK_4BYTE(arg->sigma_idx[i * 4], arg->sigma_idx[i * 4 + 1],
2810 arg->sigma_idx[i * 4 + 2], arg->sigma_idx[i * 4 + 3]);
2811 isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_IDX0 + i * 4);
2812 }
2813 value = ISP_PACK_4BYTE(arg->sigma_idx[i * 4], arg->sigma_idx[i * 4 + 1],
2814 arg->sigma_idx[i * 4 + 2], 0);
2815 isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_IDX0 + i * 4);
2816
2817 for (i = 0; i < ISP32_DHAZ_SIGMA_LUT_NUM / 2; i++) {
2818 value = ISP_PACK_2SHORT(arg->sigma_lut[i * 2], arg->sigma_lut[i * 2 + 1]);
2819 isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_LUT0 + i * 4);
2820 }
2821 value = ISP_PACK_2SHORT(arg->sigma_lut[i * 2], 0);
2822 isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_LUT0 + i * 4);
2823
2824 for (i = 0; i < ISP32_DHAZ_ENH_LUMA_NUM / 3; i++) {
2825 value = (arg->enh_luma[i * 3 + 2] & 0x3ff) << 20 |
2826 (arg->enh_luma[i * 3 + 1] & 0x3ff) << 10 |
2827 (arg->enh_luma[i * 3] & 0x3ff);
2828 isp3_param_write(params_vdev, value, ISP32_DHAZ_ENH_LUMA0 + i * 4);
2829 }
2830 value = (arg->enh_luma[i * 3 + 1] & 0x3ff) << 10 |
2831 (arg->enh_luma[i * 3] & 0x3ff);
2832 isp3_param_write(params_vdev, value, ISP32_DHAZ_ENH_LUMA0 + i * 4);
2833 }
2834
2835 static void
isp_dhaz_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2836 isp_dhaz_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
2837 {
2838 u32 value;
2839 bool real_en;
2840
2841 value = isp3_param_read(params_vdev, ISP3X_DHAZ_CTRL);
2842 real_en = !!(value & ISP3X_DHAZ_ENMUX);
2843 if ((en && real_en) || (!en && !real_en))
2844 return;
2845
2846 if (en) {
2847 value |= ISP32_SELF_FORCE_UPD | ISP3X_DHAZ_ENMUX;
2848 isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1,
2849 ISP3X_DHAZ_FST_FRAME);
2850 } else {
2851 value &= ~ISP3X_DHAZ_ENMUX;
2852 isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(16));
2853 }
2854 isp3_param_write(params_vdev, value, ISP3X_DHAZ_CTRL);
2855 }
2856
2857 static void
isp_3dlut_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_3dlut_cfg * arg)2858 isp_3dlut_config(struct rkisp_isp_params_vdev *params_vdev,
2859 const struct isp2x_3dlut_cfg *arg)
2860 {
2861 struct rkisp_device *dev = params_vdev->dev;
2862 struct rkisp_isp_params_val_v32 *priv_val;
2863 u32 value, buf_idx, i;
2864 u32 *data;
2865
2866 priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val;
2867 buf_idx = (priv_val->buf_3dlut_idx++) % ISP32_3DLUT_BUF_NUM;
2868
2869 if (!priv_val->buf_3dlut[buf_idx].vaddr) {
2870 dev_err(dev->dev, "no find 3dlut buf\n");
2871 return;
2872 }
2873 data = (u32 *)priv_val->buf_3dlut[buf_idx].vaddr;
2874 for (i = 0; i < arg->actual_size; i++)
2875 data[i] = (arg->lut_b[i] & 0x3FF) |
2876 (arg->lut_g[i] & 0xFFF) << 10 |
2877 (arg->lut_r[i] & 0x3FF) << 22;
2878 rkisp_prepare_buffer(params_vdev->dev, &priv_val->buf_3dlut[buf_idx]);
2879 value = priv_val->buf_3dlut[buf_idx].dma_addr;
2880 isp3_param_write(params_vdev, value, ISP3X_MI_LUT_3D_RD_BASE);
2881 isp3_param_write(params_vdev, arg->actual_size, ISP3X_MI_LUT_3D_RD_WSIZE);
2882
2883 value = isp3_param_read(params_vdev, ISP3X_3DLUT_CTRL);
2884 value &= ISP3X_3DLUT_EN;
2885
2886 if (value)
2887 isp3_param_set_bits(params_vdev, ISP3X_3DLUT_UPDATE, 0x01);
2888
2889 isp3_param_write(params_vdev, value, ISP3X_3DLUT_CTRL);
2890 }
2891
2892 static void
isp_3dlut_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2893 isp_3dlut_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
2894 {
2895 u32 value;
2896 bool en_state;
2897 struct rkisp_isp_params_val_v32 *priv_val;
2898
2899 value = isp3_param_read(params_vdev, ISP3X_3DLUT_CTRL);
2900 en_state = (value & ISP3X_3DLUT_EN) ? true : false;
2901
2902 if (en == en_state)
2903 return;
2904
2905 priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val;
2906 if (en && priv_val->buf_3dlut[0].vaddr) {
2907 isp3_param_set_bits(params_vdev, ISP3X_3DLUT_CTRL, 0x01);
2908 isp3_param_set_bits(params_vdev, ISP3X_3DLUT_UPDATE, 0x01);
2909 } else {
2910 isp3_param_clear_bits(params_vdev, ISP3X_3DLUT_CTRL, 0x01);
2911 isp3_param_clear_bits(params_vdev, ISP3X_3DLUT_UPDATE, 0x01);
2912 isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(20));
2913 }
2914 }
2915
2916 static void
isp_ldch_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp32_ldch_cfg * arg)2917 isp_ldch_config(struct rkisp_isp_params_vdev *params_vdev,
2918 const struct isp32_ldch_cfg *arg)
2919 {
2920 struct rkisp_device *dev = params_vdev->dev;
2921 struct rkisp_isp_params_val_v32 *priv_val;
2922 struct isp2x_mesh_head *head;
2923 int buf_idx, i;
2924 u32 value;
2925
2926 value = isp3_param_read(params_vdev, ISP3X_LDCH_STS);
2927 value &= ISP32_MODULE_EN;
2928 value |= !!arg->map13p3_en << 7 |
2929 !!arg->force_map_en << 6 |
2930 !!arg->bic_mode_en << 4 |
2931 !!arg->sample_avr_en << 3 |
2932 !!arg->zero_interp_en << 2 |
2933 !!arg->frm_end_dis << 1;
2934 isp3_param_write(params_vdev, value, ISP3X_LDCH_STS);
2935 if (arg->bic_mode_en) {
2936 for (i = 0; i < ISP32_LDCH_BIC_NUM / 4; i++) {
2937 value = ISP_PACK_4BYTE(arg->bicubic[i * 4], arg->bicubic[i * 4 + 1],
2938 arg->bicubic[i * 4 + 2], arg->bicubic[i * 4 + 3]);
2939 isp3_param_write(params_vdev, value, ISP32_LDCH_BIC_TABLE0 + i * 4);
2940 }
2941 }
2942
2943 priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val;
2944 for (i = 0; i < ISP32_MESH_BUF_NUM; i++) {
2945 if (!priv_val->buf_ldch[i].mem_priv)
2946 continue;
2947 if (arg->buf_fd == priv_val->buf_ldch[i].dma_fd)
2948 break;
2949 }
2950 if (i == ISP32_MESH_BUF_NUM) {
2951 dev_err(dev->dev, "cannot find ldch buf fd(%d)\n", arg->buf_fd);
2952 return;
2953 }
2954
2955 if (!priv_val->buf_ldch[i].vaddr) {
2956 dev_err(dev->dev, "no ldch buffer allocated\n");
2957 return;
2958 }
2959
2960 buf_idx = priv_val->buf_ldch_idx;
2961 head = (struct isp2x_mesh_head *)priv_val->buf_ldch[buf_idx].vaddr;
2962 head->stat = MESH_BUF_INIT;
2963
2964 buf_idx = i;
2965 head = (struct isp2x_mesh_head *)priv_val->buf_ldch[buf_idx].vaddr;
2966 head->stat = MESH_BUF_CHIPINUSE;
2967 priv_val->buf_ldch_idx = buf_idx;
2968 rkisp_prepare_buffer(dev, &priv_val->buf_ldch[buf_idx]);
2969 value = priv_val->buf_ldch[buf_idx].dma_addr + head->data_oft;
2970 isp3_param_write(params_vdev, value, ISP3X_MI_LUT_LDCH_RD_BASE);
2971 isp3_param_write(params_vdev, arg->hsize, ISP3X_MI_LUT_LDCH_RD_H_WSIZE);
2972 isp3_param_write(params_vdev, arg->vsize, ISP3X_MI_LUT_LDCH_RD_V_SIZE);
2973 }
2974
2975 static void
isp_ldch_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2976 isp_ldch_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
2977 {
2978 struct rkisp_device *dev = params_vdev->dev;
2979 struct rkisp_isp_params_val_v32 *priv_val;
2980 u32 buf_idx;
2981
2982 priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val;
2983 if (en) {
2984 buf_idx = priv_val->buf_ldch_idx;
2985 if (!priv_val->buf_ldch[buf_idx].vaddr) {
2986 dev_err(dev->dev, "no ldch buffer allocated\n");
2987 return;
2988 }
2989 isp3_param_set_bits(params_vdev, ISP3X_LDCH_STS, 0x01);
2990 } else {
2991 isp3_param_clear_bits(params_vdev, ISP3X_LDCH_STS, 0x01);
2992 }
2993 }
2994
2995 static void
isp_ynr_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp32_ynr_cfg * arg)2996 isp_ynr_config(struct rkisp_isp_params_vdev *params_vdev,
2997 const struct isp32_ynr_cfg *arg)
2998 {
2999 u32 i, value;
3000
3001 value = isp3_param_read(params_vdev, ISP3X_YNR_GLOBAL_CTRL);
3002 value &= ISP32_MODULE_EN;
3003
3004 value |= !!arg->rnr_en << 26 |
3005 !!arg->thumb_mix_cur_en << 24 |
3006 (arg->global_gain_alpha & 0xF) << 20 |
3007 (arg->global_gain & 0x3FF) << 8 |
3008 (arg->flt1x1_bypass_sel & 0x3) << 6 |
3009 !!arg->nlm11x11_bypass << 5 |
3010 !!arg->flt1x1_bypass << 4 |
3011 !!arg->lgft3x3_bypass << 3 |
3012 !!arg->lbft5x5_bypass << 2 |
3013 !!arg->bft3x3_bypass << 1;
3014 isp3_param_write(params_vdev, value, ISP3X_YNR_GLOBAL_CTRL);
3015
3016 value = ISP_PACK_2SHORT(arg->rnr_max_r, arg->local_gainscale);
3017 isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_MAX_R);
3018
3019 value = ISP_PACK_2SHORT(arg->rnr_center_coorh, arg->rnr_center_coorv);
3020 isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_CENTER_COOR);
3021
3022 value = ISP_PACK_2SHORT(arg->loclagain_adj_thresh, arg->localgain_adj);
3023 isp3_param_write(params_vdev, value, ISP3X_YNR_LOCAL_GAIN_CTRL);
3024
3025 value = ISP_PACK_2SHORT(arg->low_bf_inv0, arg->low_bf_inv1);
3026 isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL0);
3027
3028 value = ISP_PACK_2SHORT(arg->low_thred_adj, arg->low_peak_supress);
3029 isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL1);
3030
3031 value = ISP_PACK_2SHORT(arg->low_edge_adj_thresh, arg->low_dist_adj);
3032 isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL2);
3033
3034 value = (arg->low_bi_weight & 0xFF) << 24 |
3035 (arg->low_weight & 0xFF) << 16 |
3036 (arg->low_center_weight & 0xFFFF);
3037 isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL3);
3038
3039 value = ISP_PACK_2SHORT(arg->lbf_weight_thres, arg->frame_full_size);
3040 if (params_vdev->dev->isp_ver == ISP_V32_L)
3041 value |= (arg->frame_add4line & 0xf) << 12;
3042 isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL4);
3043
3044 value = (arg->low_gauss1_coeff2 & 0xFFFF) << 16 |
3045 (arg->low_gauss1_coeff1 & 0xFF) << 8 |
3046 (arg->low_gauss1_coeff0 & 0xFF);
3047 isp3_param_write(params_vdev, value, ISP3X_YNR_GAUSS1_COEFF);
3048
3049 value = (arg->low_gauss2_coeff2 & 0xFFFF) << 16 |
3050 (arg->low_gauss2_coeff1 & 0xFF) << 8 |
3051 (arg->low_gauss2_coeff0 & 0xFF);
3052 isp3_param_write(params_vdev, value, ISP3X_YNR_GAUSS2_COEFF);
3053
3054 for (i = 0; i < ISP32_YNR_XY_NUM / 2; i++) {
3055 value = ISP_PACK_2SHORT(arg->luma_points_x[2 * i],
3056 arg->luma_points_x[2 * i + 1]);
3057 isp3_param_write(params_vdev, value, ISP3X_YNR_SGM_DX_0_1 + 4 * i);
3058 }
3059 value = ISP_PACK_2SHORT(arg->luma_points_x[2 * i], 0);
3060 isp3_param_write(params_vdev, value, ISP3X_YNR_SGM_DX_0_1 + 4 * i);
3061
3062 for (i = 0; i < ISP32_YNR_XY_NUM / 2; i++) {
3063 value = ISP_PACK_2SHORT(arg->lsgm_y[2 * i],
3064 arg->lsgm_y[2 * i + 1]);
3065 isp3_param_write(params_vdev, value, ISP3X_YNR_LSGM_Y_0_1 + 4 * i);
3066 }
3067 value = ISP_PACK_2SHORT(arg->lsgm_y[2 * i], 0);
3068 isp3_param_write(params_vdev, value, ISP3X_YNR_LSGM_Y_0_1 + 4 * i);
3069
3070 for (i = 0; i < ISP32_YNR_XY_NUM / 4; i++) {
3071 value = ISP_PACK_4BYTE(arg->rnr_strength3[4 * i],
3072 arg->rnr_strength3[4 * i + 1],
3073 arg->rnr_strength3[4 * i + 2],
3074 arg->rnr_strength3[4 * i + 3]);
3075 isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_STRENGTH03 + 4 * i);
3076 }
3077 value = ISP_PACK_4BYTE(arg->rnr_strength3[4 * i], 0, 0, 0);
3078 isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_STRENGTH03 + 4 * i);
3079
3080 value = (arg->nlm_hi_bf_scale & 0x3ff) << 16 |
3081 (arg->nlm_hi_gain_alpha & 0x1f) << 11 |
3082 (arg->nlm_min_sigma & 0x7ff);
3083 isp3_param_write(params_vdev, value, ISP32_YNR_NLM_SIGMA_GAIN);
3084
3085 value = (arg->nlm_coe[5] & 0xf) << 20 | (arg->nlm_coe[4] & 0xf) << 16 |
3086 (arg->nlm_coe[3] & 0xf) << 12 | (arg->nlm_coe[2] & 0xf) << 8 |
3087 (arg->nlm_coe[1] & 0xf) << 4 | (arg->nlm_coe[0] & 0xf);
3088 isp3_param_write(params_vdev, value, ISP32_YNR_NLM_COE);
3089
3090 value = (arg->nlm_center_weight & 0x3ffff) << 10 | (arg->nlm_weight_offset & 0x3ff);
3091 isp3_param_write(params_vdev, value, ISP32_YNR_NLM_WEIGHT);
3092
3093 value = arg->nlm_nr_weight & 0x7ff;
3094 isp3_param_write(params_vdev, value, ISP32_YNR_NLM_NR_WEIGHT);
3095 }
3096
3097 static void
isp_ynr_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)3098 isp_ynr_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
3099 {
3100 u32 ynr_ctrl;
3101 bool real_en;
3102
3103 ynr_ctrl = isp3_param_read_cache(params_vdev, ISP3X_YNR_GLOBAL_CTRL);
3104 real_en = !!(ynr_ctrl & ISP32_MODULE_EN);
3105 if ((en && real_en) || (!en && !real_en))
3106 return;
3107
3108 if (en) {
3109 ynr_ctrl |= ISP32_MODULE_EN;
3110 isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1,
3111 ISP3X_YNR_FST_FRAME);
3112 } else {
3113 ynr_ctrl &= ~ISP32_MODULE_EN;
3114 }
3115
3116 isp3_param_write(params_vdev, ynr_ctrl, ISP3X_YNR_GLOBAL_CTRL);
3117 }
3118
3119 static void
isp_cnr_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp32_cnr_cfg * arg)3120 isp_cnr_config(struct rkisp_isp_params_vdev *params_vdev,
3121 const struct isp32_cnr_cfg *arg)
3122 {
3123 u32 i, value, ctrl, gain_ctrl;
3124
3125 gain_ctrl = isp3_param_read(params_vdev, ISP3X_GAIN_CTRL);
3126 ctrl = isp3_param_read(params_vdev, ISP3X_CNR_CTRL);
3127 ctrl &= ISP32_MODULE_EN;
3128
3129 ctrl |= !!arg->bf3x3_wgt0_sel << 8 |
3130 (arg->thumb_mode & 0x3) << 4 |
3131 !!arg->yuv422_mode << 2 |
3132 !!arg->exgain_bypass << 1;
3133 value = (arg->global_gain & 0x3ff) |
3134 (arg->global_gain_alpha & 0xf) << 12 |
3135 arg->gain_iso << 16;
3136 /* gain disable, using global gain for cnr */
3137 if (ctrl & ISP32_MODULE_EN && !(gain_ctrl & ISP32_MODULE_EN)) {
3138 ctrl |= BIT(1);
3139 value &= ~ISP3X_CNR_GLOBAL_GAIN_ALPHA_MAX;
3140 value |= BIT(15);
3141 }
3142 isp3_param_write(params_vdev, ctrl, ISP3X_CNR_CTRL);
3143 isp3_param_write(params_vdev, value, ISP3X_CNR_EXGAIN);
3144
3145 value = ISP_PACK_2SHORT(arg->thumb_sigma_c, arg->thumb_sigma_y);
3146 isp3_param_write(params_vdev, value, ISP32_CNR_THUMB1);
3147
3148 value = arg->thumb_bf_ratio & 0x7ff;
3149 isp3_param_write(params_vdev, value, ISP32_CNR_THUMB_BF_RATIO);
3150
3151 value = ISP_PACK_4BYTE(arg->lbf1x7_weit_d0, arg->lbf1x7_weit_d1,
3152 arg->lbf1x7_weit_d2, arg->lbf1x7_weit_d3);
3153 isp3_param_write(params_vdev, value, ISP32_CNR_LBF_WEITD);
3154
3155 value = (arg->wgt_slope & 0x3ff) << 20 | (arg->exp_shift & 0x3f) << 12 |
3156 arg->iir_strength << 4 | (arg->iir_uvgain & 0xf);
3157 isp3_param_write(params_vdev, value, ISP32_CNR_IIR_PARA1);
3158
3159 value = ISP_PACK_4BYTE(arg->chroma_ghost, arg->iir_uv_clip, 0, 0);
3160 isp3_param_write(params_vdev, value, ISP32_CNR_IIR_PARA2);
3161
3162 value = ISP_PACK_4BYTE(arg->gaus_coe[0], arg->gaus_coe[1],
3163 arg->gaus_coe[2], arg->gaus_coe[3]);
3164 isp3_param_write(params_vdev, value, ISP32_CNR_GAUS_COE1);
3165
3166 value = ISP_PACK_4BYTE(arg->gaus_coe[4], arg->gaus_coe[5], 0, 0);
3167 isp3_param_write(params_vdev, value, ISP32_CNR_GAUS_COE2);
3168
3169 value = (arg->global_alpha & 0x7ff) << 20 | arg->bf_wgt_clip << 12 |
3170 (arg->gaus_ratio & 0x7ff);
3171 isp3_param_write(params_vdev, value, ISP32_CNR_GAUS_RATIO);
3172
3173 value = arg->bf_ratio << 24 | (arg->sigma_r & 0x3fff) << 8 |
3174 (arg->uv_gain & 0x7f);
3175 isp3_param_write(params_vdev, value, ISP32_CNR_BF_PARA1);
3176
3177 value = (arg->adj_ratio & 0x7fff) << 16 | (arg->adj_offset & 0x1ff);
3178 isp3_param_write(params_vdev, value, ISP32_CNR_BF_PARA2);
3179
3180 for (i = 0; i < ISP32_CNR_SIGMA_Y_NUM / 4; i++) {
3181 value = ISP_PACK_4BYTE(arg->sigma_y[i * 4], arg->sigma_y[i * 4 + 1],
3182 arg->sigma_y[i * 4 + 2], arg->sigma_y[i * 4 + 3]);
3183 isp3_param_write(params_vdev, value, ISP32_CNR_SIGMA0 + i * 4);
3184 }
3185 value = arg->sigma_y[i * 4];
3186 isp3_param_write(params_vdev, value, ISP32_CNR_SIGMA0 + i * 4);
3187
3188 value = (arg->iir_gain_alpha & 0xf) << 8 | arg->iir_global_gain;
3189 isp3_param_write(params_vdev, value, ISP32_CNR_IIR_GLOBAL_GAIN);
3190 }
3191
3192 static void
isp_cnr_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)3193 isp_cnr_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
3194 {
3195 u32 cnr_ctrl;
3196 bool real_en;
3197
3198 cnr_ctrl = isp3_param_read_cache(params_vdev, ISP3X_CNR_CTRL);
3199 real_en = !!(cnr_ctrl & ISP32_MODULE_EN);
3200 if ((en && real_en) || (!en && !real_en))
3201 return;
3202
3203 if (en) {
3204 cnr_ctrl |= ISP32_MODULE_EN;
3205 isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1,
3206 ISP3X_CNR_FST_FRAME);
3207 } else {
3208 cnr_ctrl &= ~ISP32_MODULE_EN;
3209 }
3210
3211 isp3_param_write(params_vdev, cnr_ctrl, ISP3X_CNR_CTRL);
3212 }
3213
3214 static void
isp_sharp_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp32_sharp_cfg * arg)3215 isp_sharp_config(struct rkisp_isp_params_vdev *params_vdev,
3216 const struct isp32_sharp_cfg *arg)
3217 {
3218 u32 i, value;
3219
3220 value = isp3_param_read(params_vdev, ISP3X_SHARP_EN);
3221 value &= ISP32_MODULE_EN;
3222
3223 value |= !!arg->bypass << 1 |
3224 !!arg->center_mode << 2 |
3225 !!arg->exgain_bypass << 3 |
3226 !!arg->radius_ds_mode << 4;
3227 if (params_vdev->dev->isp_ver == ISP_V32)
3228 value |= !!arg->noiseclip_mode << 5;
3229 else
3230 value |= !!arg->clip_hf_mode << 6 |
3231 !!arg->add_mode << 7;
3232 isp3_param_write(params_vdev, value, ISP3X_SHARP_EN);
3233
3234 value = ISP_PACK_4BYTE(arg->pbf_ratio, arg->gaus_ratio,
3235 arg->bf_ratio, arg->sharp_ratio);
3236 isp3_param_write(params_vdev, value, ISP3X_SHARP_RATIO);
3237
3238 value = (arg->luma_dx[6] & 0x0F) << 24 |
3239 (arg->luma_dx[5] & 0x0F) << 20 |
3240 (arg->luma_dx[4] & 0x0F) << 16 |
3241 (arg->luma_dx[3] & 0x0F) << 12 |
3242 (arg->luma_dx[2] & 0x0F) << 8 |
3243 (arg->luma_dx[1] & 0x0F) << 4 |
3244 (arg->luma_dx[0] & 0x0F);
3245 isp3_param_write(params_vdev, value, ISP3X_SHARP_LUMA_DX);
3246
3247 value = (arg->pbf_sigma_inv[2] & 0x3FF) << 20 |
3248 (arg->pbf_sigma_inv[1] & 0x3FF) << 10 |
3249 (arg->pbf_sigma_inv[0] & 0x3FF);
3250 isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_SIGMA_INV_0);
3251
3252 value = (arg->pbf_sigma_inv[5] & 0x3FF) << 20 |
3253 (arg->pbf_sigma_inv[4] & 0x3FF) << 10 |
3254 (arg->pbf_sigma_inv[3] & 0x3FF);
3255 isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_SIGMA_INV_1);
3256
3257 value = (arg->pbf_sigma_inv[7] & 0x3FF) << 10 |
3258 (arg->pbf_sigma_inv[6] & 0x3FF);
3259 isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_SIGMA_INV_2);
3260
3261 value = (arg->bf_sigma_inv[2] & 0x3FF) << 20 |
3262 (arg->bf_sigma_inv[1] & 0x3FF) << 10 |
3263 (arg->bf_sigma_inv[0] & 0x3FF);
3264 isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_SIGMA_INV_0);
3265
3266 value = (arg->bf_sigma_inv[5] & 0x3FF) << 20 |
3267 (arg->bf_sigma_inv[4] & 0x3FF) << 10 |
3268 (arg->bf_sigma_inv[3] & 0x3FF);
3269 isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_SIGMA_INV_1);
3270
3271 value = (arg->bf_sigma_inv[7] & 0x3FF) << 10 |
3272 (arg->bf_sigma_inv[6] & 0x3FF);
3273 isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_SIGMA_INV_2);
3274
3275 value = (arg->bf_sigma_shift & 0x0F) << 4 |
3276 (arg->pbf_sigma_shift & 0x0F);
3277 isp3_param_write(params_vdev, value, ISP3X_SHARP_SIGMA_SHIFT);
3278
3279 value = (arg->clip_hf[2] & 0x3FF) << 20 |
3280 (arg->clip_hf[1] & 0x3FF) << 10 |
3281 (arg->clip_hf[0] & 0x3FF);
3282 isp3_param_write(params_vdev, value, ISP3X_SHARP_CLIP_HF_0);
3283
3284 value = (arg->clip_hf[5] & 0x3FF) << 20 |
3285 (arg->clip_hf[4] & 0x3FF) << 10 |
3286 (arg->clip_hf[3] & 0x3FF);
3287 isp3_param_write(params_vdev, value, ISP3X_SHARP_CLIP_HF_1);
3288
3289 value = (arg->clip_hf[7] & 0x3FF) << 10 |
3290 (arg->clip_hf[6] & 0x3FF);
3291 isp3_param_write(params_vdev, value, ISP3X_SHARP_CLIP_HF_2);
3292
3293 value = ISP_PACK_4BYTE(arg->pbf_coef0, arg->pbf_coef1, arg->pbf_coef2, 0);
3294 isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_COEF);
3295
3296 value = ISP_PACK_4BYTE(arg->bf_coef0, arg->bf_coef1, arg->bf_coef2, 0);
3297 isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_COEF);
3298
3299 value = ISP_PACK_4BYTE(arg->gaus_coef[0], arg->gaus_coef[1], arg->gaus_coef[2], 0);
3300 isp3_param_write(params_vdev, value, ISP3X_SHARP_GAUS_COEF0);
3301
3302 value = ISP_PACK_4BYTE(arg->gaus_coef[3], arg->gaus_coef[4], arg->gaus_coef[5], 0);
3303 isp3_param_write(params_vdev, value, ISP3X_SHARP_GAUS_COEF1);
3304
3305 value = arg->local_gainscale << 24 | (arg->global_gain_alpha & 0xf) << 16 |
3306 (arg->global_gain & 0x3ff);
3307 isp3_param_write(params_vdev, value, ISP32_SHARP_GAIN);
3308
3309 for (i = 0; i < ISP32_SHARP_GAIN_ADJ_NUM / 2; i++) {
3310 value = ISP_PACK_2SHORT(arg->gain_adj[i * 2], arg->gain_adj[i * 2 + 1]);
3311 isp3_param_write(params_vdev, value, ISP32_SHARP_GAIN_ADJUST0 + i * 4);
3312 }
3313
3314 value = ISP_PACK_2SHORT(arg->center_wid, arg->center_het);
3315 isp3_param_write(params_vdev, value, ISP32_SHARP_CENTER);
3316
3317 for (i = 0; i < ISP32_SHARP_STRENGTH_NUM / 4; i++) {
3318 value = ISP_PACK_4BYTE(arg->strength[i * 4], arg->strength[i * 4 + 1],
3319 arg->strength[i * 4 + 2], arg->strength[i * 4 + 3]);
3320 isp3_param_write(params_vdev, value, ISP32_SHARP_GAIN_DIS_STRENGTH0 + i * 4);
3321 }
3322 value = ISP_PACK_4BYTE(arg->strength[i * 4], arg->strength[i * 4 + 1], 0, 0);
3323 isp3_param_write(params_vdev, value, ISP32_SHARP_GAIN_DIS_STRENGTH0 + i * 4);
3324
3325 if (params_vdev->dev->isp_ver == ISP_V32) {
3326 value = (arg->noise_strength & 0x3fff) << 16 | (arg->enhance_bit & 0xf) << 12 |
3327 (arg->noise_sigma & 0x3ff);
3328 isp3_param_write(params_vdev, value, ISP32_SHARP_TEXTURE);
3329 } else {
3330 value = (arg->ehf_th[2] & 0x3FF) << 20 |
3331 (arg->ehf_th[1] & 0x3FF) << 10 |
3332 (arg->ehf_th[0] & 0x3FF);
3333 isp3_param_write(params_vdev, value, ISP3X_SHARP_EHF_TH_0);
3334 value = (arg->ehf_th[5] & 0x3FF) << 20 |
3335 (arg->ehf_th[4] & 0x3FF) << 10 |
3336 (arg->ehf_th[3] & 0x3FF);
3337 isp3_param_write(params_vdev, value, ISP3X_SHARP_EHF_TH_1);
3338 value = (arg->ehf_th[7] & 0x3FF) << 10 |
3339 (arg->ehf_th[6] & 0x3FF);
3340 isp3_param_write(params_vdev, value, ISP3X_SHARP_EHF_TH_2);
3341
3342 value = (arg->clip_neg[2] & 0x3FF) << 20 |
3343 (arg->clip_neg[1] & 0x3FF) << 10 |
3344 (arg->clip_neg[0] & 0x3FF);
3345 isp3_param_write(params_vdev, value, ISP32L_SHARP_CLIP_NEG_0);
3346 value = (arg->clip_neg[5] & 0x3FF) << 20 |
3347 (arg->clip_neg[4] & 0x3FF) << 10 |
3348 (arg->clip_neg[3] & 0x3FF);
3349 isp3_param_write(params_vdev, value, ISP32L_SHARP_CLIP_NEG_1);
3350 value = (arg->clip_neg[7] & 0x3FF) << 10 |
3351 (arg->clip_neg[6] & 0x3FF);
3352 isp3_param_write(params_vdev, value, ISP32L_SHARP_CLIP_NEG_2);
3353 }
3354 }
3355
3356 static void
isp_sharp_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)3357 isp_sharp_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
3358 {
3359 u32 value;
3360
3361 value = isp3_param_read_cache(params_vdev, ISP3X_SHARP_EN);
3362 value &= ~ISP32_MODULE_EN;
3363
3364 if (en)
3365 value |= ISP32_MODULE_EN;
3366
3367 isp3_param_write(params_vdev, value, ISP3X_SHARP_EN);
3368 }
3369
3370 static void
isp_baynr_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp32_baynr_cfg * arg)3371 isp_baynr_config(struct rkisp_isp_params_vdev *params_vdev,
3372 const struct isp32_baynr_cfg *arg)
3373 {
3374 u32 i, value;
3375
3376 value = isp3_param_read(params_vdev, ISP3X_BAYNR_CTRL);
3377 value &= ISP32_MODULE_EN;
3378
3379 value |= !!arg->bay3d_gain_en << 16 |
3380 (arg->lg2_mode & 0x3) << 12 |
3381 !!arg->gauss_en << 8 |
3382 !!arg->log_bypass << 4;
3383 isp3_param_write(params_vdev, value, ISP3X_BAYNR_CTRL);
3384
3385 value = ISP_PACK_2SHORT(arg->dgain0, arg->dgain1);
3386 isp3_param_write(params_vdev, value, ISP3X_BAYNR_DGAIN0);
3387
3388 isp3_param_write(params_vdev, arg->dgain2, ISP3X_BAYNR_DGAIN1);
3389 isp3_param_write(params_vdev, arg->pix_diff, ISP3X_BAYNR_PIXDIFF);
3390
3391 value = ISP_PACK_2SHORT(arg->softthld, arg->diff_thld);
3392 isp3_param_write(params_vdev, value, ISP3X_BAYNR_THLD);
3393
3394 value = ISP_PACK_2SHORT(arg->reg_w1, arg->bltflt_streng);
3395 isp3_param_write(params_vdev, value, ISP3X_BAYNR_W1_STRENG);
3396
3397 for (i = 0; i < ISP32_BAYNR_XY_NUM / 2; i++) {
3398 value = ISP_PACK_2SHORT(arg->sigma_x[2 * i], arg->sigma_x[2 * i + 1]);
3399 isp3_param_write(params_vdev, value, ISP3X_BAYNR_SIGMAX01 + 4 * i);
3400 }
3401
3402 for (i = 0; i < ISP32_BAYNR_XY_NUM / 2; i++) {
3403 value = ISP_PACK_2SHORT(arg->sigma_y[2 * i], arg->sigma_y[2 * i + 1]);
3404 isp3_param_write(params_vdev, value, ISP3X_BAYNR_SIGMAY01 + 4 * i);
3405 }
3406
3407 value = (arg->weit_d2 & 0x3FF) << 20 |
3408 (arg->weit_d1 & 0x3FF) << 10 |
3409 (arg->weit_d0 & 0x3FF);
3410 isp3_param_write(params_vdev, value, ISP3X_BAYNR_WRIT_D);
3411
3412 value = ISP_PACK_2SHORT(arg->lg2_off, arg->lg2_lgoff);
3413 isp3_param_write(params_vdev, value, ISP3X_BAYNR_LG_OFF);
3414
3415 value = arg->dat_max & 0xfffff;
3416 isp3_param_write(params_vdev, value, ISP3X_BAYNR_DAT_MAX);
3417
3418 value = ISP_PACK_2SHORT(arg->rgain_off, arg->bgain_off);
3419 isp3_param_write(params_vdev, value, ISP32_BAYNR_SIGOFF);
3420
3421 for (i = 0; i < ISP32_BAYNR_GAIN_NUM / 4; i++) {
3422 value = ISP_PACK_4BYTE(arg->gain_x[i * 4], arg->gain_x[i * 4 + 1],
3423 arg->gain_x[i * 4 + 2], arg->gain_x[i * 4 + 3]);
3424 isp3_param_write(params_vdev, value, ISP32_BAYNR_GAINX03 + i * 4);
3425 }
3426
3427 for (i = 0; i < ISP32_BAYNR_GAIN_NUM / 2; i++) {
3428 value = ISP_PACK_2SHORT(arg->gain_y[i * 2], arg->gain_y[i * 2 + 1]);
3429 isp3_param_write(params_vdev, value, ISP32_BAYNR_GAINY01 + i * 4);
3430 }
3431 }
3432
3433 static void
isp_baynr_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)3434 isp_baynr_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
3435 {
3436 u32 value;
3437
3438 value = isp3_param_read_cache(params_vdev, ISP3X_BAYNR_CTRL);
3439 value &= ~ISP32_MODULE_EN;
3440
3441 if (en)
3442 value |= ISP32_MODULE_EN;
3443
3444 isp3_param_write(params_vdev, value, ISP3X_BAYNR_CTRL);
3445 }
3446
3447 static void
isp_bay3d_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp32_bay3d_cfg * arg)3448 isp_bay3d_config(struct rkisp_isp_params_vdev *params_vdev,
3449 const struct isp32_bay3d_cfg *arg)
3450 {
3451 struct rkisp_isp_params_val_v32 *priv_val;
3452 u32 i, value;
3453
3454 priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val;
3455 value = isp3_param_read(params_vdev, ISP3X_BAY3D_CTRL);
3456 value &= (ISP32_MODULE_EN | ISP32_BAY3D_BWSAVING(1));
3457
3458 value |= !!arg->loswitch_protect << 12 |
3459 !!arg->glbpk_en << 11 |
3460 !!arg->logaus3_bypass_en << 10 |
3461 !!arg->logaus5_bypass_en << 9 |
3462 !!arg->lomed_bypass_en << 8 |
3463 !!arg->hiabs_possel << 6 |
3464 !!arg->higaus_bypass_en << 5 |
3465 //!!arg->lobypass_en << 3 |
3466 !!arg->hibypass_en << 2 |
3467 !!arg->bypass_en << 1;
3468 if (params_vdev->dev->isp_ver == ISP_V32)
3469 value |= !!arg->hichnsplit_en << 7 |
3470 !!arg->himed_bypass_en << 4;
3471 if (!(value & ISP32_MODULE_EN)) {
3472 value &= ~ISP32_BAY3D_BWSAVING(1);
3473 if (arg->bwsaving_en)
3474 value |= ISP32_BAY3D_BWSAVING(1);
3475 } else if ((value & ISP32_BAY3D_BWSAVING(1)) !=
3476 ISP32_BAY3D_BWSAVING(!!arg->bwsaving_en)) {
3477 v4l2_warn(¶ms_vdev->dev->v4l2_dev,
3478 "bwsaving to %d no support change for bay3d en\n",
3479 arg->bwsaving_en);
3480 }
3481 isp3_param_write(params_vdev, value, ISP3X_BAY3D_CTRL);
3482
3483 value = !!arg->wgtmix_opt_en << 12 |
3484 !!arg->curds_high_en << 8 |
3485 !!arg->iirwr_rnd_en << 7 |
3486 !!arg->lo4x4_en << 4 |
3487 !!arg->lo4x8_en << 3 |
3488 !!arg->bwopt_gain_dis << 2 |
3489 !!arg->hiwgt_opt_en;
3490 if (params_vdev->dev->isp_ver == ISP_V32)
3491 value |= !!arg->higaus5x5_en << 11 |
3492 (arg->higaus3_mode & 0x3) << 9 |
3493 !!arg->pksig_ind_sel << 6 |
3494 !!arg->hisig_ind_sel << 5 |
3495 !!arg->hichncor_en << 1;
3496 else
3497 value |= !!arg->wgtmm_sel_en << 14 |
3498 !!arg->wgtmm_opt_en << 13;
3499 if (priv_val->is_lo8x8)
3500 value &= ~(BIT(3) | BIT(4));
3501 else if (!(value & (BIT(3) | BIT(4))))
3502 value |= BIT(3);
3503 isp3_param_write(params_vdev, value, ISP32_BAY3D_CTRL1);
3504
3505 value = ISP_PACK_2SHORT(arg->softwgt, arg->hidif_th);
3506 isp3_param_write(params_vdev, value, ISP3X_BAY3D_KALRATIO);
3507
3508 isp3_param_write(params_vdev, arg->glbpk2, ISP3X_BAY3D_GLBPK2);
3509
3510 value = ISP_PACK_2SHORT(arg->wgtlmt, arg->wgtratio);
3511 isp3_param_write(params_vdev, value, ISP3X_BAY3D_WGTLMT);
3512
3513 for (i = 0; i < ISP32_BAY3D_XY_NUM / 2; i++) {
3514 value = ISP_PACK_2SHORT(arg->sig0_x[2 * i],
3515 arg->sig0_x[2 * i + 1]);
3516 isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG0_X0 + 4 * i);
3517
3518 value = ISP_PACK_2SHORT(arg->sig1_x[2 * i],
3519 arg->sig1_x[2 * i + 1]);
3520 isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG1_X0 + 4 * i);
3521 }
3522
3523 for (i = 0; i < ISP32_BAY3D_XY_NUM / 2; i++) {
3524 value = ISP_PACK_2SHORT(arg->sig0_y[2 * i],
3525 arg->sig0_y[2 * i + 1]);
3526 isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG0_Y0 + 4 * i);
3527
3528 value = ISP_PACK_2SHORT(arg->sig1_y[2 * i],
3529 arg->sig1_y[2 * i + 1]);
3530 isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG1_Y0 + 4 * i);
3531
3532 value = ISP_PACK_2SHORT(arg->sig2_y[2 * i],
3533 arg->sig2_y[2 * i + 1]);
3534 isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG2_Y0 + 4 * i);
3535 }
3536
3537 if (params_vdev->dev->isp_ver == ISP_V32_L) {
3538 value = ISP_PACK_2SHORT(0, arg->wgtmin);
3539 isp3_param_write(params_vdev, value, ISP3X_BAY3D_LODIF_STAT1);
3540 }
3541
3542 value = ISP_PACK_2SHORT(arg->hisigrat0, arg->hisigrat1);
3543 isp3_param_write(params_vdev, value, ISP32_BAY3D_HISIGRAT);
3544
3545 value = ISP_PACK_2SHORT(arg->hisigoff0, arg->hisigoff1);
3546 isp3_param_write(params_vdev, value, ISP32_BAY3D_HISIGOFF);
3547
3548 value = ISP_PACK_2SHORT(arg->losigoff, arg->losigrat);
3549 isp3_param_write(params_vdev, value, ISP32_BAY3D_LOSIG);
3550
3551 value = ISP_PACK_2SHORT(arg->rgain_off, arg->bgain_off);
3552 isp3_param_write(params_vdev, value, ISP32_BAY3D_SIGPK);
3553
3554 value = ISP_PACK_4BYTE(arg->siggaus0, arg->siggaus1, arg->siggaus2, 0);
3555 if (params_vdev->dev->isp_ver == ISP_V32)
3556 value |= (arg->siggaus3 << 24);
3557 isp3_param_write(params_vdev, value, ISP32_BAY3D_SIGGAUS);
3558 }
3559
3560 static void
isp_bay3d_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)3561 isp_bay3d_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
3562 {
3563 struct rkisp_device *ispdev = params_vdev->dev;
3564 struct rkisp_isp_params_val_v32 *priv_val;
3565 u32 value, bay3d_ctrl;
3566
3567 priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val;
3568 bay3d_ctrl = isp3_param_read_cache(params_vdev, ISP3X_BAY3D_CTRL);
3569 if ((en && (bay3d_ctrl & ISP32_MODULE_EN)) ||
3570 (!en && !(bay3d_ctrl & ISP32_MODULE_EN)))
3571 return;
3572
3573 if (en) {
3574 if (!priv_val->buf_3dnr_iir.mem_priv) {
3575 dev_err(ispdev->dev, "no bay3d buffer available\n");
3576 return;
3577 }
3578
3579 value = priv_val->buf_3dnr_iir.size;
3580 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_WR_SIZE);
3581 value = priv_val->buf_3dnr_iir.dma_addr;
3582 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_WR_BASE);
3583 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_RD_BASE);
3584
3585 value = priv_val->buf_3dnr_ds.size;
3586 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_DS_WR_SIZE);
3587 value = priv_val->buf_3dnr_ds.dma_addr;
3588 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_DS_WR_BASE);
3589 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_DS_RD_BASE);
3590
3591 value = priv_val->is_sram ?
3592 ispdev->hw_dev->sram.dma_addr : priv_val->buf_3dnr_cur.dma_addr;
3593 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_WR_BASE);
3594 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_RD_BASE);
3595 value = priv_val->bay3d_cur_size;
3596 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_WR_SIZE);
3597 isp3_param_write(params_vdev, value, ISP32_MI_BAY3D_CUR_RD_SIZE);
3598 value = priv_val->bay3d_cur_wsize;
3599 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_WR_LENGTH);
3600 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_RD_LENGTH);
3601 value = priv_val->bay3d_cur_wrap_line << 16 |
3602 (ispdev->isp_ver == ISP_V32 ? 28 : 20);
3603 isp3_param_write(params_vdev, value, ISP3X_BAY3D_MI_ST);
3604
3605 /* mibuf_size for fifo_cur_full, set to max: (3072 - 2) / 2, 2 align */
3606 if (ispdev->isp_ver == ISP_V32) {
3607 value = 0x5fe << 16;
3608 isp3_param_set_bits(params_vdev, ISP3X_BAY3D_IN_IRQ_LINECNT, value);
3609 }
3610
3611 value = isp3_param_read_cache(params_vdev, ISP32_BAY3D_CTRL1);
3612 if (priv_val->is_lo8x8) {
3613 if (value & (BIT(3) | BIT(4))) {
3614 value &= ~(BIT(3) | BIT(4));
3615 isp3_param_write(params_vdev, value, ISP32_BAY3D_CTRL1);
3616 }
3617 } else if (!(value & (BIT(3) | BIT(4)))) {
3618 value |= BIT(3);
3619 isp3_param_write(params_vdev, value, ISP32_BAY3D_CTRL1);
3620 }
3621 bay3d_ctrl |= ISP32_MODULE_EN;
3622 isp3_param_write(params_vdev, bay3d_ctrl, ISP3X_BAY3D_CTRL);
3623
3624 value = ISP3X_BAY3D_IIR_WR_AUTO_UPD | ISP3X_BAY3D_CUR_WR_AUTO_UPD |
3625 ISP3X_BAY3D_DS_WR_AUTO_UPD | ISP3X_BAY3D_IIRSELF_UPD |
3626 ISP3X_BAY3D_CURSELF_UPD | ISP3X_BAY3D_DSSELF_UPD |
3627 ISP3X_BAY3D_RDSELF_UPD;
3628 isp3_param_set_bits(params_vdev, MI_WR_CTRL2, value);
3629
3630 isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1, ISP3X_RAW3D_FST_FRAME);
3631 } else {
3632 bay3d_ctrl &= ~ISP32_MODULE_EN;
3633 isp3_param_write(params_vdev, bay3d_ctrl, ISP3X_BAY3D_CTRL);
3634 isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(4));
3635 }
3636 }
3637
3638 static void
isp_gain_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_gain_cfg * arg)3639 isp_gain_config(struct rkisp_isp_params_vdev *params_vdev,
3640 const struct isp3x_gain_cfg *arg)
3641 {
3642 u32 val;
3643
3644 val = arg->g0 & 0x3ffff;
3645 isp3_param_write(params_vdev, val, ISP3X_GAIN_G0);
3646 val = ISP_PACK_2SHORT(arg->g1, arg->g2);
3647 isp3_param_write(params_vdev, val, ISP3X_GAIN_G1_G2);
3648 }
3649
3650 static void
isp_gain_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)3651 isp_gain_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
3652 {
3653 struct rkisp_isp_params_val_v32 *priv_val =
3654 (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val;
3655 u32 val = 0;
3656
3657 val = isp3_param_read_cache(params_vdev, ISP3X_GAIN_CTRL);
3658 if (en) {
3659 if (params_vdev->dev->isp_ver == ISP_V32) {
3660 val |= priv_val->lut3d_en << 20 |
3661 priv_val->dhaz_en << 16 |
3662 priv_val->drc_en << 12 |
3663 priv_val->lsc_en << 8 |
3664 priv_val->bay3d_en << 4;
3665 if (isp3_param_read(params_vdev, ISP3X_HDRMGE_CTRL) & BIT(0))
3666 val |= BIT(1);
3667 if (val)
3668 val |= ISP32_MODULE_EN;
3669 } else {
3670 val |= ISP32_MODULE_EN;
3671 }
3672 }
3673 isp3_param_write(params_vdev, val, ISP3X_GAIN_CTRL);
3674 }
3675
3676 static void
isp_cac_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp32_cac_cfg * arg)3677 isp_cac_config(struct rkisp_isp_params_vdev *params_vdev,
3678 const struct isp32_cac_cfg *arg)
3679 {
3680 struct rkisp_device *dev = params_vdev->dev;
3681 struct rkisp_isp_params_val_v32 *priv_val;
3682 struct isp2x_mesh_head *head;
3683 u32 i, val, ctrl;
3684
3685 priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val;
3686
3687 ctrl = isp3_param_read(params_vdev, ISP3X_CAC_CTRL);
3688 ctrl &= ISP3X_CAC_EN;
3689 ctrl |= !!arg->bypass_en << 1 | !!arg->center_en << 3 |
3690 (arg->clip_g_mode & 0x3) << 5 | !!arg->edge_detect_en << 7 |
3691 !!arg->neg_clip0_en << 9;
3692
3693 val = (arg->psf_sft_bit & 0xff) |
3694 (arg->cfg_num & 0x7ff) << 8;
3695 isp3_param_write(params_vdev, val, ISP3X_CAC_PSF_PARA);
3696
3697 val = ISP_PACK_2SHORT(arg->center_width, arg->center_height);
3698 isp3_param_write(params_vdev, val, ISP3X_CAC_STRENGTH_CENTER);
3699
3700 for (i = 0; i < ISP32_CAC_STRENGTH_NUM / 2; i++) {
3701 val = ISP_PACK_2SHORT(arg->strength[2 * i], arg->strength[2 * i + 1]);
3702 isp3_param_write(params_vdev, val, ISP3X_CAC_STRENGTH0 + i * 4);
3703 }
3704
3705 val = (arg->flat_thed_r & 0x1f) << 8 | (arg->flat_thed_b & 0x1f);
3706 isp3_param_write(params_vdev, val, ISP32_CAC_FLAT_THED);
3707
3708 val = ISP_PACK_2SHORT(arg->offset_b, arg->offset_r);
3709 isp3_param_write(params_vdev, val, ISP32_CAC_OFFSET);
3710
3711 val = arg->expo_thed_b & 0x1fffff;
3712 isp3_param_write(params_vdev, val, ISP32_CAC_EXPO_THED_B);
3713
3714 val = arg->expo_thed_r & 0x1fffff;
3715 isp3_param_write(params_vdev, val, ISP32_CAC_EXPO_THED_R);
3716
3717 val = arg->expo_adj_b & 0xfffff;
3718 isp3_param_write(params_vdev, val, ISP32_CAC_EXPO_ADJ_B);
3719
3720 val = arg->expo_adj_r & 0xfffff;
3721 isp3_param_write(params_vdev, val, ISP32_CAC_EXPO_ADJ_R);
3722
3723 for (i = 0; i < ISP32_MESH_BUF_NUM; i++) {
3724 if (!priv_val->buf_cac[i].mem_priv)
3725 continue;
3726 if (arg->buf_fd == priv_val->buf_cac[i].dma_fd)
3727 break;
3728 }
3729
3730 if (i == ISP32_MESH_BUF_NUM) {
3731 dev_err(dev->dev, "cannot find cac buf fd(%d)\n", arg->buf_fd);
3732 return;
3733 }
3734
3735 if (!priv_val->buf_cac[i].vaddr) {
3736 dev_err(dev->dev, "no cac buffer allocated\n");
3737 return;
3738 }
3739
3740 val = priv_val->buf_cac_idx;
3741 head = (struct isp2x_mesh_head *)priv_val->buf_cac[val].vaddr;
3742 head->stat = MESH_BUF_INIT;
3743
3744 head = (struct isp2x_mesh_head *)priv_val->buf_cac[i].vaddr;
3745 head->stat = MESH_BUF_CHIPINUSE;
3746 priv_val->buf_cac_idx = i;
3747 rkisp_prepare_buffer(dev, &priv_val->buf_cac[i]);
3748 val = priv_val->buf_cac[i].dma_addr + head->data_oft;
3749 isp3_param_write(params_vdev, val, ISP3X_MI_LUT_CAC_RD_BASE);
3750 isp3_param_write(params_vdev, arg->hsize, ISP3X_MI_LUT_CAC_RD_H_WSIZE);
3751 isp3_param_write(params_vdev, arg->vsize, ISP3X_MI_LUT_CAC_RD_V_SIZE);
3752 if (ctrl & ISP3X_CAC_EN)
3753 ctrl |= ISP3X_CAC_LUT_EN | ISP32_SELF_FORCE_UPD | ISP3X_CAC_LUT_MODE(3);
3754 isp3_param_write(params_vdev, ctrl, ISP3X_CAC_CTRL);
3755 }
3756
3757 static void
isp_cac_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)3758 isp_cac_enable(struct rkisp_isp_params_vdev *params_vdev, bool en)
3759 {
3760 u32 val;
3761
3762 val = isp3_param_read(params_vdev, ISP3X_CAC_CTRL);
3763 val &= ~(ISP3X_CAC_EN | ISP3X_CAC_LUT_EN | ISP32_SELF_FORCE_UPD);
3764 if (en)
3765 val |= ISP3X_CAC_EN | ISP3X_CAC_LUT_EN |
3766 ISP32_SELF_FORCE_UPD | ISP3X_CAC_LUT_MODE(3);
3767 isp3_param_write(params_vdev, val, ISP3X_CAC_CTRL);
3768 }
3769
3770 static void
isp_csm_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_csm_cfg * arg)3771 isp_csm_config(struct rkisp_isp_params_vdev *params_vdev,
3772 const struct isp21_csm_cfg *arg)
3773 {
3774 u32 i, val;
3775
3776 for (i = 0; i < ISP32_CSM_COEFF_NUM; i++) {
3777 if (i == 0)
3778 val = (arg->csm_y_offset & 0x3f) << 24 |
3779 (arg->csm_c_offset & 0xff) << 16 |
3780 (arg->csm_coeff[i] & 0x1ff);
3781 else
3782 val = arg->csm_coeff[i] & 0x1ff;
3783 isp3_param_write(params_vdev, val, ISP3X_ISP_CC_COEFF_0 + i * 4);
3784 }
3785
3786 val = isp3_param_read_cache(params_vdev, ISP3X_ISP_CTRL0);
3787 val |= CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA | CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA;
3788 isp3_param_write(params_vdev, val, ISP3X_ISP_CTRL0);
3789 }
3790
3791 static void
isp_cgc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_cgc_cfg * arg)3792 isp_cgc_config(struct rkisp_isp_params_vdev *params_vdev,
3793 const struct isp21_cgc_cfg *arg)
3794 {
3795 u32 val = isp3_param_read_cache(params_vdev, ISP3X_ISP_CTRL0);
3796 u32 eff_ctrl, cproc_ctrl;
3797
3798 params_vdev->quantization = V4L2_QUANTIZATION_FULL_RANGE;
3799 val &= ~(ISP3X_SW_CGC_YUV_LIMIT | ISP3X_SW_CGC_RATIO_EN);
3800 if (arg->yuv_limit) {
3801 val |= ISP3X_SW_CGC_YUV_LIMIT;
3802 params_vdev->quantization = V4L2_QUANTIZATION_LIM_RANGE;
3803 }
3804 if (arg->ratio_en)
3805 val |= ISP3X_SW_CGC_RATIO_EN;
3806 isp3_param_write(params_vdev, val, ISP3X_ISP_CTRL0);
3807
3808 cproc_ctrl = isp3_param_read(params_vdev, ISP3X_CPROC_CTRL);
3809 if (cproc_ctrl & CIF_C_PROC_CTR_ENABLE) {
3810 val = CIF_C_PROC_YOUT_FULL | CIF_C_PROC_YIN_FULL | CIF_C_PROC_COUT_FULL;
3811 if (arg->yuv_limit)
3812 cproc_ctrl &= ~val;
3813 else
3814 cproc_ctrl |= val;
3815 isp3_param_write(params_vdev, cproc_ctrl, ISP3X_CPROC_CTRL);
3816 }
3817
3818 eff_ctrl = isp3_param_read(params_vdev, ISP3X_IMG_EFF_CTRL);
3819 if (eff_ctrl & CIF_IMG_EFF_CTRL_ENABLE) {
3820 if (arg->yuv_limit)
3821 eff_ctrl &= ~CIF_IMG_EFF_CTRL_YCBCR_FULL;
3822 else
3823 eff_ctrl |= CIF_IMG_EFF_CTRL_YCBCR_FULL;
3824 isp3_param_write(params_vdev, eff_ctrl, ISP3X_IMG_EFF_CTRL);
3825 }
3826 }
3827
3828 static void
isp_vsm_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp32_vsm_cfg * arg)3829 isp_vsm_config(struct rkisp_isp_params_vdev *params_vdev,
3830 const struct isp32_vsm_cfg *arg)
3831 {
3832 struct rkisp_device *ispdev = params_vdev->dev;
3833 struct v4l2_rect *out_crop = &ispdev->isp_sdev.out_crop;
3834 u32 width = out_crop->width;
3835 u32 height = out_crop->height;
3836 u32 val, h, v;
3837
3838 val = arg->h_offs;
3839 isp3_param_write(params_vdev, val, ISP32_VSM_H_OFFS);
3840 val = arg->v_offs;
3841 isp3_param_write(params_vdev, val, ISP32_VSM_V_OFFS);
3842
3843 h = arg->h_size;
3844 if (h > width - arg->h_offs)
3845 h = width - arg->h_offs;
3846 h &= ~1;
3847 isp3_param_write(params_vdev, h, ISP32_VSM_H_SIZE);
3848
3849 v = arg->v_size;
3850 if (v > height - arg->v_offs)
3851 v = height - arg->v_offs;
3852 v &= ~1;
3853 isp3_param_write(params_vdev, v, ISP32_VSM_V_SIZE);
3854
3855 val = arg->h_segments;
3856 if (val > (h - 48) / 16)
3857 val = (h - 48) / 16;
3858 isp3_param_write(params_vdev, val, ISP32_VSM_H_SEGMENTS);
3859
3860 val = arg->v_segments;
3861 if (val > (v - 48) / 16)
3862 val = (v - 48) / 16;
3863 isp3_param_write(params_vdev, val, ISP32_VSM_V_SEGMENTS);
3864 }
3865
3866 static void
isp_vsm_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)3867 isp_vsm_enable(struct rkisp_isp_params_vdev *params_vdev,
3868 bool en)
3869 {
3870 isp3_param_write(params_vdev, en, ISP32_VSM_MODE);
3871 }
3872
3873 struct rkisp_isp_params_ops_v32 isp_params_ops_v32 = {
3874 .dpcc_config = isp_dpcc_config,
3875 .dpcc_enable = isp_dpcc_enable,
3876 .bls_config = isp_bls_config,
3877 .bls_enable = isp_bls_enable,
3878 .sdg_config = isp_sdg_config,
3879 .sdg_enable = isp_sdg_enable,
3880 .lsc_config = isp_lsc_config,
3881 .lsc_enable = isp_lsc_enable,
3882 .awbgain_config = isp_awbgain_config,
3883 .awbgain_enable = isp_awbgain_enable,
3884 .debayer_config = isp_debayer_config,
3885 .debayer_enable = isp_debayer_enable,
3886 .ccm_config = isp_ccm_config,
3887 .ccm_enable = isp_ccm_enable,
3888 .goc_config = isp_goc_config,
3889 .goc_enable = isp_goc_enable,
3890 .csm_config = isp_csm_config,
3891 .cproc_config = isp_cproc_config,
3892 .cproc_enable = isp_cproc_enable,
3893 .ie_config = isp_ie_config,
3894 .ie_enable = isp_ie_enable,
3895 .rawaf_config = isp_rawaf_config,
3896 .rawaf_enable = isp_rawaf_enable,
3897 .rawae0_config = isp_rawaelite_config,
3898 .rawae0_enable = isp_rawaelite_enable,
3899 .rawae1_config = isp_rawae1_config,
3900 .rawae1_enable = isp_rawae1_enable,
3901 .rawae2_config = isp_rawae2_config,
3902 .rawae2_enable = isp_rawae2_enable,
3903 .rawae3_config = isp_rawae3_config,
3904 .rawae3_enable = isp_rawae3_enable,
3905 .rawawb_config = isp_rawawb_config,
3906 .rawawb_enable = isp_rawawb_enable,
3907 .rawhst0_config = isp_rawhstlite_config,
3908 .rawhst0_enable = isp_rawhstlite_enable,
3909 .rawhst1_config = isp_rawhst1_config,
3910 .rawhst1_enable = isp_rawhst1_enable,
3911 .rawhst2_config = isp_rawhst2_config,
3912 .rawhst2_enable = isp_rawhst2_enable,
3913 .rawhst3_config = isp_rawhst3_config,
3914 .rawhst3_enable = isp_rawhst3_enable,
3915 .hdrmge_config = isp_hdrmge_config,
3916 .hdrmge_enable = isp_hdrmge_enable,
3917 .hdrdrc_config = isp_hdrdrc_config,
3918 .hdrdrc_enable = isp_hdrdrc_enable,
3919 .gic_config = isp_gic_config,
3920 .gic_enable = isp_gic_enable,
3921 .dhaz_config = isp_dhaz_config,
3922 .dhaz_enable = isp_dhaz_enable,
3923 .isp3dlut_config = isp_3dlut_config,
3924 .isp3dlut_enable = isp_3dlut_enable,
3925 .ldch_config = isp_ldch_config,
3926 .ldch_enable = isp_ldch_enable,
3927 .ynr_config = isp_ynr_config,
3928 .ynr_enable = isp_ynr_enable,
3929 .cnr_config = isp_cnr_config,
3930 .cnr_enable = isp_cnr_enable,
3931 .sharp_config = isp_sharp_config,
3932 .sharp_enable = isp_sharp_enable,
3933 .baynr_config = isp_baynr_config,
3934 .baynr_enable = isp_baynr_enable,
3935 .bay3d_config = isp_bay3d_config,
3936 .bay3d_enable = isp_bay3d_enable,
3937 .gain_config = isp_gain_config,
3938 .gain_enable = isp_gain_enable,
3939 .cac_config = isp_cac_config,
3940 .cac_enable = isp_cac_enable,
3941 .cgc_config = isp_cgc_config,
3942 .vsm_config = isp_vsm_config,
3943 .vsm_enable = isp_vsm_enable,
3944 };
3945
3946 static __maybe_unused
__isp_isr_other_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp32_isp_params_cfg * new_params,enum rkisp_params_type type)3947 void __isp_isr_other_config(struct rkisp_isp_params_vdev *params_vdev,
3948 const struct isp32_isp_params_cfg *new_params,
3949 enum rkisp_params_type type)
3950 {
3951 struct rkisp_isp_params_ops_v32 *ops =
3952 (struct rkisp_isp_params_ops_v32 *)params_vdev->priv_ops;
3953 u64 module_cfg_update = new_params->module_cfg_update;
3954
3955 if (params_vdev->dev->isp_ver == ISP_V32_L)
3956 module_cfg_update &= ~(ISP32_MODULE_GIC | ISP32_MODULE_BAYNR |
3957 ISP32_MODULE_VSM | ISP32_MODULE_CAC);
3958
3959 if (type == RKISP_PARAMS_SHD) {
3960 if ((module_cfg_update & ISP32_MODULE_HDRMGE))
3961 ops->hdrmge_config(params_vdev, &new_params->others.hdrmge_cfg, type);
3962
3963 if ((module_cfg_update & ISP32_MODULE_DRC))
3964 ops->hdrdrc_config(params_vdev, &new_params->others.drc_cfg, type);
3965 return;
3966 }
3967
3968 v4l2_dbg(4, rkisp_debug, ¶ms_vdev->dev->v4l2_dev,
3969 "%s seq:%d module_cfg_update:0x%llx\n",
3970 __func__, new_params->frame_id, module_cfg_update);
3971
3972 if (module_cfg_update & ISP32_MODULE_LSC)
3973 ops->lsc_config(params_vdev, &new_params->others.lsc_cfg);
3974
3975 if (module_cfg_update & ISP32_MODULE_DPCC)
3976 ops->dpcc_config(params_vdev, &new_params->others.dpcc_cfg);
3977
3978 if (module_cfg_update & ISP32_MODULE_BLS)
3979 ops->bls_config(params_vdev, &new_params->others.bls_cfg);
3980
3981 if (module_cfg_update & ISP32_MODULE_SDG)
3982 ops->sdg_config(params_vdev, &new_params->others.sdg_cfg);
3983
3984 if (module_cfg_update & ISP32_MODULE_AWB_GAIN)
3985 ops->awbgain_config(params_vdev, &new_params->others.awb_gain_cfg);
3986
3987 if (module_cfg_update & ISP32_MODULE_DEBAYER)
3988 ops->debayer_config(params_vdev, &new_params->others.debayer_cfg);
3989
3990 if (module_cfg_update & ISP32_MODULE_CCM)
3991 ops->ccm_config(params_vdev, &new_params->others.ccm_cfg);
3992
3993 if (module_cfg_update & ISP32_MODULE_GOC)
3994 ops->goc_config(params_vdev, &new_params->others.gammaout_cfg);
3995
3996 /* range csm->cgc->cproc->ie */
3997 if (module_cfg_update & ISP3X_MODULE_CSM)
3998 ops->csm_config(params_vdev, &new_params->others.csm_cfg);
3999
4000 if (module_cfg_update & ISP3X_MODULE_CGC)
4001 ops->cgc_config(params_vdev, &new_params->others.cgc_cfg);
4002
4003 if (module_cfg_update & ISP32_MODULE_CPROC)
4004 ops->cproc_config(params_vdev, &new_params->others.cproc_cfg);
4005
4006 if (module_cfg_update & ISP32_MODULE_IE)
4007 ops->ie_config(params_vdev, &new_params->others.ie_cfg);
4008
4009 if (module_cfg_update & ISP32_MODULE_HDRMGE)
4010 ops->hdrmge_config(params_vdev, &new_params->others.hdrmge_cfg, type);
4011
4012 if (module_cfg_update & ISP32_MODULE_DRC)
4013 ops->hdrdrc_config(params_vdev, &new_params->others.drc_cfg, type);
4014
4015 if (module_cfg_update & ISP32_MODULE_GIC)
4016 ops->gic_config(params_vdev, &new_params->others.gic_cfg);
4017
4018 if (module_cfg_update & ISP32_MODULE_DHAZ)
4019 ops->dhaz_config(params_vdev, &new_params->others.dhaz_cfg);
4020
4021 if (module_cfg_update & ISP32_MODULE_3DLUT)
4022 ops->isp3dlut_config(params_vdev, &new_params->others.isp3dlut_cfg);
4023
4024 if (module_cfg_update & ISP32_MODULE_LDCH)
4025 ops->ldch_config(params_vdev, &new_params->others.ldch_cfg);
4026
4027 if (module_cfg_update & ISP32_MODULE_YNR)
4028 ops->ynr_config(params_vdev, &new_params->others.ynr_cfg);
4029
4030 if (module_cfg_update & ISP32_MODULE_CNR)
4031 ops->cnr_config(params_vdev, &new_params->others.cnr_cfg);
4032
4033 if (module_cfg_update & ISP32_MODULE_SHARP)
4034 ops->sharp_config(params_vdev, &new_params->others.sharp_cfg);
4035
4036 if (module_cfg_update & ISP32_MODULE_BAYNR)
4037 ops->baynr_config(params_vdev, &new_params->others.baynr_cfg);
4038
4039 if (module_cfg_update & ISP32_MODULE_BAY3D)
4040 ops->bay3d_config(params_vdev, &new_params->others.bay3d_cfg);
4041
4042 if (module_cfg_update & ISP32_MODULE_CAC)
4043 ops->cac_config(params_vdev, &new_params->others.cac_cfg);
4044
4045 if (module_cfg_update & ISP32_MODULE_GAIN)
4046 ops->gain_config(params_vdev, &new_params->others.gain_cfg);
4047
4048 if (module_cfg_update & ISP32_MODULE_VSM)
4049 ops->vsm_config(params_vdev, &new_params->others.vsm_cfg);
4050 }
4051
4052 static __maybe_unused
__isp_isr_other_en(struct rkisp_isp_params_vdev * params_vdev,const struct isp32_isp_params_cfg * new_params,enum rkisp_params_type type)4053 void __isp_isr_other_en(struct rkisp_isp_params_vdev *params_vdev,
4054 const struct isp32_isp_params_cfg *new_params,
4055 enum rkisp_params_type type)
4056 {
4057 struct rkisp_isp_params_ops_v32 *ops =
4058 (struct rkisp_isp_params_ops_v32 *)params_vdev->priv_ops;
4059 struct rkisp_isp_params_val_v32 *priv_val =
4060 (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val;
4061 u64 module_en_update = new_params->module_en_update;
4062 u64 module_ens = new_params->module_ens;
4063 u32 gain_ctrl, cnr_ctrl, val;
4064
4065 if (params_vdev->dev->isp_ver == ISP_V32_L)
4066 module_en_update &= ~(ISP32_MODULE_GIC | ISP32_MODULE_BAYNR |
4067 ISP32_MODULE_VSM | ISP32_MODULE_CAC);
4068
4069 if (type == RKISP_PARAMS_SHD)
4070 return;
4071
4072 v4l2_dbg(4, rkisp_debug, ¶ms_vdev->dev->v4l2_dev,
4073 "%s seq:%d module_en_update:0x%llx module_ens:0x%llx\n",
4074 __func__, new_params->frame_id, module_en_update, module_ens);
4075
4076 if (module_en_update & ISP32_MODULE_DPCC)
4077 ops->dpcc_enable(params_vdev, !!(module_ens & ISP32_MODULE_DPCC));
4078
4079 if (module_en_update & ISP32_MODULE_BLS)
4080 ops->bls_enable(params_vdev, !!(module_ens & ISP32_MODULE_BLS));
4081
4082 if (module_en_update & ISP32_MODULE_SDG)
4083 ops->sdg_enable(params_vdev, !!(module_ens & ISP32_MODULE_SDG));
4084
4085 if (module_en_update & ISP32_MODULE_LSC) {
4086 ops->lsc_enable(params_vdev, !!(module_ens & ISP32_MODULE_LSC));
4087 priv_val->lsc_en = !!(module_ens & ISP32_MODULE_LSC);
4088 }
4089
4090 if (module_en_update & ISP32_MODULE_AWB_GAIN)
4091 ops->awbgain_enable(params_vdev, !!(module_ens & ISP32_MODULE_AWB_GAIN));
4092
4093 if (module_en_update & ISP32_MODULE_DEBAYER)
4094 ops->debayer_enable(params_vdev, !!(module_ens & ISP32_MODULE_DEBAYER));
4095
4096 if (module_en_update & ISP32_MODULE_CCM)
4097 ops->ccm_enable(params_vdev, !!(module_ens & ISP32_MODULE_CCM));
4098
4099 if (module_en_update & ISP32_MODULE_GOC)
4100 ops->goc_enable(params_vdev, !!(module_ens & ISP32_MODULE_GOC));
4101
4102 if (module_en_update & ISP32_MODULE_CPROC)
4103 ops->cproc_enable(params_vdev, !!(module_ens & ISP32_MODULE_CPROC));
4104
4105 if (module_en_update & ISP32_MODULE_IE)
4106 ops->ie_enable(params_vdev, !!(module_ens & ISP32_MODULE_IE));
4107
4108 if (module_en_update & ISP32_MODULE_HDRMGE) {
4109 ops->hdrmge_enable(params_vdev, !!(module_ens & ISP32_MODULE_HDRMGE));
4110 priv_val->mge_en = !!(module_ens & ISP32_MODULE_HDRMGE);
4111 }
4112
4113 if (module_en_update & ISP32_MODULE_DRC) {
4114 ops->hdrdrc_enable(params_vdev, !!(module_ens & ISP32_MODULE_DRC));
4115 priv_val->drc_en = !!(module_ens & ISP32_MODULE_DRC);
4116 }
4117
4118 if (module_en_update & ISP32_MODULE_GIC)
4119 ops->gic_enable(params_vdev, !!(module_ens & ISP32_MODULE_GIC));
4120
4121 if (module_en_update & ISP32_MODULE_DHAZ) {
4122 ops->dhaz_enable(params_vdev, !!(module_ens & ISP32_MODULE_DHAZ));
4123 priv_val->dhaz_en = !!(module_ens & ISP32_MODULE_DHAZ);
4124 }
4125
4126 if (module_en_update & ISP32_MODULE_3DLUT) {
4127 ops->isp3dlut_enable(params_vdev, !!(module_ens & ISP32_MODULE_3DLUT));
4128 priv_val->lut3d_en = !!(module_ens & ISP32_MODULE_3DLUT);
4129 }
4130
4131 if (module_en_update & ISP32_MODULE_LDCH)
4132 ops->ldch_enable(params_vdev, !!(module_ens & ISP32_MODULE_LDCH));
4133
4134 if (module_en_update & ISP32_MODULE_YNR)
4135 ops->ynr_enable(params_vdev, !!(module_ens & ISP32_MODULE_YNR));
4136
4137 if (module_en_update & ISP32_MODULE_CNR)
4138 ops->cnr_enable(params_vdev, !!(module_ens & ISP32_MODULE_CNR));
4139
4140 if (module_en_update & ISP32_MODULE_SHARP)
4141 ops->sharp_enable(params_vdev, !!(module_ens & ISP32_MODULE_SHARP));
4142
4143 if (module_en_update & ISP32_MODULE_BAYNR)
4144 ops->baynr_enable(params_vdev, !!(module_ens & ISP32_MODULE_BAYNR));
4145
4146 if (module_en_update & ISP32_MODULE_BAY3D) {
4147 ops->bay3d_enable(params_vdev, !!(module_ens & ISP32_MODULE_BAY3D));
4148 priv_val->bay3d_en = !!(module_ens & ISP32_MODULE_BAY3D);
4149 }
4150
4151 if (module_en_update & ISP32_MODULE_CAC)
4152 ops->cac_enable(params_vdev, !!(module_ens & ISP32_MODULE_CAC));
4153
4154 if (module_en_update & ISP32_MODULE_GAIN ||
4155 ((priv_val->buf_info_owner == RKISP_INFO2DRR_OWNER_GAIN) &&
4156 !(isp3_param_read(params_vdev, ISP3X_GAIN_CTRL) & ISP3X_GAIN_2DDR_EN)))
4157 ops->gain_enable(params_vdev, !!(module_ens & ISP32_MODULE_GAIN));
4158
4159 if (module_en_update & ISP32_MODULE_VSM)
4160 ops->vsm_enable(params_vdev, !!(module_ens & ISP32_MODULE_VSM));
4161
4162 /* gain disable, using global gain for cnr */
4163 gain_ctrl = isp3_param_read_cache(params_vdev, ISP3X_GAIN_CTRL);
4164 cnr_ctrl = isp3_param_read_cache(params_vdev, ISP3X_CNR_CTRL);
4165 if (!(gain_ctrl & ISP32_MODULE_EN) && cnr_ctrl & ISP32_MODULE_EN) {
4166 cnr_ctrl |= BIT(1);
4167 isp3_param_write(params_vdev, cnr_ctrl, ISP3X_CNR_CTRL);
4168 val = isp3_param_read(params_vdev, ISP3X_CNR_EXGAIN) & 0x3ff;
4169 isp3_param_write(params_vdev, val | 0x8000, ISP3X_CNR_EXGAIN);
4170 }
4171 }
4172
4173 static __maybe_unused
__isp_isr_meas_config(struct rkisp_isp_params_vdev * params_vdev,struct isp32_isp_params_cfg * new_params,enum rkisp_params_type type)4174 void __isp_isr_meas_config(struct rkisp_isp_params_vdev *params_vdev,
4175 struct isp32_isp_params_cfg *new_params,
4176 enum rkisp_params_type type)
4177 {
4178 struct rkisp_isp_params_ops_v32 *ops =
4179 (struct rkisp_isp_params_ops_v32 *)params_vdev->priv_ops;
4180 struct rkisp_isp_params_val_v32 *priv_val =
4181 (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val;
4182 u64 module_cfg_update = new_params->module_cfg_update;
4183
4184 params_vdev->cur_frame_id = new_params->frame_id;
4185 if (params_vdev->dev->isp_ver == ISP_V32_L)
4186 module_cfg_update &= ~(ISP32_MODULE_RAWAE1 | ISP32_MODULE_RAWAE2 |
4187 ISP32_MODULE_RAWHIST1 | ISP32_MODULE_RAWHIST2);
4188
4189 if (type == RKISP_PARAMS_SHD)
4190 return;
4191
4192 v4l2_dbg(4, rkisp_debug, ¶ms_vdev->dev->v4l2_dev,
4193 "%s seq:%d module_cfg_update:0x%llx\n",
4194 __func__, new_params->frame_id, module_cfg_update);
4195
4196 if ((module_cfg_update & ISP32_MODULE_RAWAF))
4197 ops->rawaf_config(params_vdev, &new_params->meas.rawaf);
4198
4199 if ((module_cfg_update & ISP32_MODULE_RAWAE0) &&
4200 !(params_vdev->afaemode_en && params_vdev->dev->isp_ver == ISP_V32_L))
4201 ops->rawae0_config(params_vdev, &new_params->meas.rawae0);
4202
4203 if ((module_cfg_update & ISP32_MODULE_RAWAE1))
4204 ops->rawae1_config(params_vdev, &new_params->meas.rawae1);
4205
4206 if ((module_cfg_update & ISP32_MODULE_RAWAE2))
4207 ops->rawae2_config(params_vdev, &new_params->meas.rawae2);
4208
4209 if ((module_cfg_update & ISP32_MODULE_RAWAE3) &&
4210 !(params_vdev->afaemode_en && params_vdev->dev->isp_ver == ISP_V32))
4211 ops->rawae3_config(params_vdev, &new_params->meas.rawae3);
4212
4213 if ((module_cfg_update & ISP32_MODULE_RAWHIST0))
4214 ops->rawhst0_config(params_vdev, &new_params->meas.rawhist0);
4215
4216 if ((module_cfg_update & ISP32_MODULE_RAWHIST1))
4217 ops->rawhst1_config(params_vdev, &new_params->meas.rawhist1);
4218
4219 if ((module_cfg_update & ISP32_MODULE_RAWHIST2))
4220 ops->rawhst2_config(params_vdev, &new_params->meas.rawhist2);
4221
4222 if ((module_cfg_update & ISP32_MODULE_RAWHIST3))
4223 ops->rawhst3_config(params_vdev, &new_params->meas.rawhist3);
4224
4225 if ((module_cfg_update & ISP32_MODULE_RAWAWB) ||
4226 ((priv_val->buf_info_owner == RKISP_INFO2DRR_OWNER_AWB) &&
4227 !(isp3_param_read(params_vdev, ISP3X_RAWAWB_CTRL) & ISP32_RAWAWB_2DDR_PATH_EN)))
4228 ops->rawawb_config(params_vdev, &new_params->meas.rawawb);
4229 }
4230
4231 static __maybe_unused
__isp_isr_meas_en(struct rkisp_isp_params_vdev * params_vdev,struct isp32_isp_params_cfg * new_params,enum rkisp_params_type type)4232 void __isp_isr_meas_en(struct rkisp_isp_params_vdev *params_vdev,
4233 struct isp32_isp_params_cfg *new_params,
4234 enum rkisp_params_type type)
4235 {
4236 struct rkisp_isp_params_ops_v32 *ops =
4237 (struct rkisp_isp_params_ops_v32 *)params_vdev->priv_ops;
4238 u64 module_en_update = new_params->module_en_update;
4239 u64 module_ens = new_params->module_ens;
4240
4241 if (params_vdev->dev->isp_ver == ISP_V32_L)
4242 module_en_update &= ~(ISP32_MODULE_RAWAE1 | ISP32_MODULE_RAWAE2 |
4243 ISP32_MODULE_RAWHIST1 | ISP32_MODULE_RAWHIST2);
4244 if (type == RKISP_PARAMS_SHD)
4245 return;
4246
4247 v4l2_dbg(4, rkisp_debug, ¶ms_vdev->dev->v4l2_dev,
4248 "%s seq:%d module_en_update:0x%llx module_ens:0x%llx\n",
4249 __func__, new_params->frame_id, module_en_update, module_ens);
4250
4251 if (module_en_update & ISP32_MODULE_RAWAF)
4252 ops->rawaf_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAF));
4253
4254 if ((module_en_update & ISP32_MODULE_RAWAE0) &&
4255 !(params_vdev->afaemode_en && params_vdev->dev->isp_ver == ISP_V32_L))
4256 ops->rawae0_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAE0));
4257
4258 if (module_en_update & ISP32_MODULE_RAWAE1)
4259 ops->rawae1_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAE1));
4260
4261 if (module_en_update & ISP32_MODULE_RAWAE2)
4262 ops->rawae2_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAE2));
4263
4264 if ((module_en_update & ISP32_MODULE_RAWAE3) &&
4265 !(params_vdev->afaemode_en && params_vdev->dev->isp_ver == ISP_V32))
4266 ops->rawae3_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAE3));
4267
4268 if (module_en_update & ISP32_MODULE_RAWHIST0)
4269 ops->rawhst0_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWHIST0));
4270
4271 if (module_en_update & ISP32_MODULE_RAWHIST1)
4272 ops->rawhst1_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWHIST1));
4273
4274 if (module_en_update & ISP32_MODULE_RAWHIST2)
4275 ops->rawhst2_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWHIST2));
4276
4277 if (module_en_update & ISP32_MODULE_RAWHIST3)
4278 ops->rawhst3_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWHIST3));
4279
4280 if (module_en_update & ISP32_MODULE_RAWAWB)
4281 ops->rawawb_enable(params_vdev, !!(module_ens & ISP32_MODULE_RAWAWB));
4282 }
4283
4284 static __maybe_unused
__isp_config_hdrshd(struct rkisp_isp_params_vdev * params_vdev)4285 void __isp_config_hdrshd(struct rkisp_isp_params_vdev *params_vdev)
4286 {
4287 struct rkisp_isp_params_ops_v32 *ops =
4288 (struct rkisp_isp_params_ops_v32 *)params_vdev->priv_ops;
4289 struct rkisp_isp_params_val_v32 *priv_val =
4290 (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val;
4291
4292 ops->hdrmge_config(params_vdev, &priv_val->last_hdrmge, RKISP_PARAMS_SHD);
4293 ops->hdrdrc_config(params_vdev, &priv_val->last_hdrdrc, RKISP_PARAMS_SHD);
4294 }
4295
4296 static
rkisp_params_cfgsram_v32(struct rkisp_isp_params_vdev * params_vdev)4297 void rkisp_params_cfgsram_v32(struct rkisp_isp_params_vdev *params_vdev)
4298 {
4299 struct isp32_isp_params_cfg *params = params_vdev->isp32_params;
4300
4301 isp_lsc_matrix_cfg_sram(params_vdev, ¶ms->others.lsc_cfg, true);
4302 isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist1, 1, true);
4303 isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist2, 2, true);
4304 isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist3, 0, true);
4305 isp_rawawb_cfg_sram(params_vdev, ¶ms->meas.rawawb, true);
4306 }
4307
4308 static int
rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev * params_vdev,const struct isp32_isp_params_cfg * new_params)4309 rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev,
4310 const struct isp32_isp_params_cfg *new_params)
4311 {
4312 struct rkisp_device *dev = params_vdev->dev;
4313 struct rkisp_isp_subdev *isp_sdev = &dev->isp_sdev;
4314 struct rkisp_isp_params_val_v32 *priv_val;
4315 u64 module_en_update, module_ens;
4316 int ret, i;
4317
4318 priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val;
4319 module_en_update = new_params->module_en_update;
4320 module_ens = new_params->module_ens;
4321
4322 priv_val->buf_3dlut_idx = 0;
4323 for (i = 0; i < ISP32_3DLUT_BUF_NUM; i++) {
4324 if (priv_val->buf_3dlut[i].mem_priv)
4325 continue;
4326 priv_val->buf_3dlut[i].is_need_vaddr = true;
4327 priv_val->buf_3dlut[i].size = ISP32_3DLUT_BUF_SIZE;
4328 ret = rkisp_alloc_buffer(dev, &priv_val->buf_3dlut[i]);
4329 if (ret) {
4330 dev_err(dev->dev, "alloc 3dlut buf fail:%d\n", ret);
4331 goto err_3dlut;
4332 }
4333 }
4334
4335 if ((module_en_update & ISP32_MODULE_BAY3D) &&
4336 (module_ens & ISP32_MODULE_BAY3D)) {
4337 bool is_hdr = !(dev->rd_mode == HDR_NORMAL || dev->rd_mode == HDR_RDBK_FRAME1);
4338 bool is_bwsaving = !!new_params->others.bay3d_cfg.bwsaving_en;
4339 bool is_glbpk = !!new_params->others.bay3d_cfg.glbpk_en;
4340 bool is_bwopt_dis = !!new_params->others.bay3d_cfg.bwopt_gain_dis;
4341 bool is_predgain = !!new_params->others.bls_cfg.isp_ob_predgain;
4342 u32 w = ALIGN(isp_sdev->in_crop.width, 16);
4343 u32 h = ALIGN(isp_sdev->in_crop.height, 16);
4344 u32 val, wrap_line, wsize, div;
4345 bool is_alloc;
4346
4347 priv_val->is_lo8x8 = (!new_params->others.bay3d_cfg.lo4x8_en &&
4348 !new_params->others.bay3d_cfg.lo4x4_en);
4349
4350 /*
4351 * bwopt_dis one line image with one line pk gain
4352 * other two line image with one line pk gain
4353 */
4354 wsize = is_bwopt_dis ? w : w * 2;
4355 if (is_bwsaving)
4356 wsize = wsize * 3 / 4;
4357 /* pk gain to ddr */
4358 if (!is_glbpk)
4359 wsize += w / 8;
4360 /* pixel to Byte */
4361 wsize *= 2;
4362 div = is_bwopt_dis ? 1 : 2;
4363 val = ALIGN(wsize * h / div, 16);
4364 is_alloc = true;
4365 if (priv_val->buf_3dnr_iir.mem_priv) {
4366 if (val > priv_val->buf_3dnr_iir.size)
4367 rkisp_free_buffer(dev, &priv_val->buf_3dnr_iir);
4368 else
4369 is_alloc = false;
4370 }
4371 if (is_alloc) {
4372 priv_val->buf_3dnr_iir.size = val;
4373 ret = rkisp_alloc_buffer(dev, &priv_val->buf_3dnr_iir);
4374 if (ret) {
4375 dev_err(dev->dev, "alloc bay3d iir buf fail:%d\n", ret);
4376 goto err_3dnr;
4377 }
4378 }
4379
4380 div = priv_val->is_lo8x8 ? 64 : 16;
4381 val = w * h / div;
4382 /* pixel to Byte and align */
4383 val = ALIGN(val * 2, 16);
4384 is_alloc = true;
4385 if (priv_val->buf_3dnr_ds.mem_priv) {
4386 if (val > priv_val->buf_3dnr_ds.size)
4387 rkisp_free_buffer(dev, &priv_val->buf_3dnr_ds);
4388 else
4389 is_alloc = false;
4390 }
4391 if (is_alloc) {
4392 priv_val->buf_3dnr_ds.size = val;
4393 ret = rkisp_alloc_buffer(dev, &priv_val->buf_3dnr_ds);
4394 if (ret) {
4395 rkisp_free_buffer(dev, &priv_val->buf_3dnr_iir);
4396 dev_err(dev->dev, "alloc bay3d ds buf fail:%d\n", ret);
4397 goto err_3dnr;
4398 }
4399 }
4400
4401 if (dev->isp_ver == ISP_V32)
4402 wrap_line = priv_val->is_lo8x8 ? 76 : 36;
4403 else
4404 wrap_line = priv_val->is_lo8x8 ? 64 : 32;
4405 wsize = is_bwopt_dis ? w : w * 2;
4406 if (is_bwsaving)
4407 wsize = wsize * 3 / 4;
4408 if (is_hdr || is_predgain)
4409 wsize += w / 8;
4410 /* pixel to Byte and align */
4411 wsize = ALIGN(wsize * 2, 16);
4412 div = is_bwopt_dis ? 1 : 2;
4413 val = ALIGN(wsize * wrap_line / div, 16);
4414 is_alloc = true;
4415 if (priv_val->buf_3dnr_cur.mem_priv) {
4416 if (val > priv_val->buf_3dnr_cur.size ||
4417 val < dev->hw_dev->sram.size)
4418 rkisp_free_buffer(dev, &priv_val->buf_3dnr_cur);
4419 else
4420 is_alloc = false;
4421 }
4422 if (val > dev->hw_dev->sram.size && is_alloc) {
4423 priv_val->buf_3dnr_cur.size = val;
4424 ret = rkisp_alloc_buffer(dev, &priv_val->buf_3dnr_cur);
4425 if (ret) {
4426 rkisp_free_buffer(dev, &priv_val->buf_3dnr_iir);
4427 rkisp_free_buffer(dev, &priv_val->buf_3dnr_ds);
4428 dev_err(dev->dev, "alloc bay3d cur buf fail:%d\n", ret);
4429 goto err_3dnr;
4430 }
4431 priv_val->is_sram = false;
4432 } else if (val <= dev->hw_dev->sram.size) {
4433 priv_val->is_sram = true;
4434 }
4435 priv_val->bay3d_cur_size = val;
4436 priv_val->bay3d_cur_wsize = wsize;
4437 priv_val->bay3d_cur_wrap_line = wrap_line;
4438 }
4439
4440 if (dev->isp_ver == ISP_V32_L) {
4441 if (dev->hw_dev->is_frm_buf && !priv_val->buf_frm.mem_priv) {
4442 priv_val->buf_frm.size = ISP32_LITE_FRM_BUF_SIZE;
4443 ret = rkisp_alloc_buffer(dev, &priv_val->buf_frm);
4444 if (ret) {
4445 dev_err(dev->dev, "alloc frm buf fail:%d\n", ret);
4446 goto free_3dnr;
4447 }
4448 }
4449
4450 priv_val->buf_lsclut_idx = 0;
4451 for (i = 0; i < ISP32_LSC_LUT_BUF_NUM; i++) {
4452 priv_val->buf_lsclut[i].is_need_vaddr = true;
4453 priv_val->buf_lsclut[i].size = ISP32_LSC_LUT_BUF_SIZE;
4454 ret = rkisp_alloc_buffer(dev, &priv_val->buf_lsclut[i]);
4455 if (ret) {
4456 dev_err(dev->dev, "alloc lsc buf fail:%d\n", ret);
4457 goto err_lsc;
4458 }
4459 }
4460 }
4461 return 0;
4462 err_lsc:
4463 if (priv_val->buf_frm.mem_priv)
4464 rkisp_free_buffer(dev, &priv_val->buf_frm);
4465 for (i -= 1; i >= 0; i--)
4466 rkisp_free_buffer(dev, &priv_val->buf_lsclut[i]);
4467 free_3dnr:
4468 rkisp_free_buffer(dev, &priv_val->buf_3dnr_cur);
4469 rkisp_free_buffer(dev, &priv_val->buf_3dnr_iir);
4470 rkisp_free_buffer(dev, &priv_val->buf_3dnr_ds);
4471 err_3dnr:
4472 i = ISP32_3DLUT_BUF_NUM;
4473 err_3dlut:
4474 for (i -= 1; i >= 0; i--)
4475 rkisp_free_buffer(dev, &priv_val->buf_3dlut[i]);
4476 return ret;
4477 }
4478
4479 static bool
rkisp_params_check_bigmode_v32_lite(struct rkisp_isp_params_vdev * params_vdev)4480 rkisp_params_check_bigmode_v32_lite(struct rkisp_isp_params_vdev *params_vdev)
4481 {
4482 struct rkisp_device *ispdev = params_vdev->dev;
4483 struct device *dev = params_vdev->dev->dev;
4484 struct rkisp_hw_dev *hw = params_vdev->dev->hw_dev;
4485 struct v4l2_rect *crop = ¶ms_vdev->dev->isp_sdev.in_crop;
4486 u32 width = hw->max_in.w, height = hw->max_in.h, size = width * height;
4487 u32 bigmode_max_w, bigmode_max_size;
4488 int k = 0, idx1[DEV_MAX] = { 0 };
4489 int n = 0, idx2[DEV_MAX] = { 0 };
4490 int i = 0, j = 0;
4491 bool is_bigmode = false;
4492
4493 using_frm_buf:
4494 if (hw->is_frm_buf) {
4495 ispdev->multi_index = 0;
4496 ispdev->multi_mode = 0;
4497 bigmode_max_w = ISP32_LITE_AUTO_BIGMODE_WIDTH;
4498 bigmode_max_size = ISP32_LITE_NOBIG_OVERFLOW_SIZE;
4499 dev_info(dev, "virtual isp%d %dx%d using frm buf\n",
4500 ispdev->dev_id, crop->width, crop->height);
4501 goto end;
4502 }
4503
4504 switch (hw->dev_link_num) {
4505 case 4:
4506 bigmode_max_w = ISP32_LITE_VIR4_AUTO_BIGMODE_WIDTH;
4507 bigmode_max_size = ISP32_LITE_VIR4_NOBIG_OVERFLOW_SIZE;
4508 ispdev->multi_index = ispdev->dev_id;
4509 ispdev->multi_mode = 2;
4510 /* internal buf of hw divided to four parts
4511 * bigmode nobigmode
4512 * _________ max width:2688 max width:1280
4513 * |_sensor0_| max size:2688*1536 max size:1280*800
4514 * |_sensor1_| max size:2688*1536 max size:1280*800
4515 * |_sensor2_| max size:2688*1536 max size:1280*800
4516 * |_sensor3_| max size:2688*1536 max size:1280*800
4517 */
4518 for (i = 0; i < hw->dev_num; i++) {
4519 if (hw->isp_size[i].w <= ISP32_LITE_VIR4_MAX_WIDTH &&
4520 hw->isp_size[i].size <= ISP32_LITE_VIR4_MAX_SIZE)
4521 continue;
4522 hw->is_frm_buf = true;
4523 goto using_frm_buf;
4524 }
4525 break;
4526 case 3:
4527 bigmode_max_w = ISP32_LITE_VIR4_AUTO_BIGMODE_WIDTH;
4528 bigmode_max_size = ISP32_LITE_VIR4_NOBIG_OVERFLOW_SIZE;
4529 ispdev->multi_index = ispdev->dev_id;
4530 ispdev->multi_mode = 2;
4531 /* case0: bigmode nobigmode
4532 * _________ max width:2688 max width:1280
4533 * |_sensor0_| max size:2688*1536 max size:1280*800
4534 * |_sensor1_| max size:2688*1536 max size:1280*800
4535 * |_sensor2_| max size:2688*1536 max size:1280*800
4536 * |_________|
4537 *
4538 * case1: bigmode special reg cfg
4539 * _________ max width:3840
4540 * | sensor0 | max size:3840*2160 mode=0 index=0
4541 * |_________|
4542 * |_sensor1_| max size:2688*1536 mode=2 index=2
4543 * |_sensor2_| max size:2688*1536 mode=2 index=3
4544 * max width:2688
4545 */
4546 for (i = 0; i < hw->dev_num; i++) {
4547 if (!hw->isp_size[i].size) {
4548 if (i < hw->dev_link_num)
4549 idx2[n++] = i;
4550 continue;
4551 }
4552 if (hw->isp_size[i].w <= ISP32_LITE_VIR4_MAX_WIDTH &&
4553 hw->isp_size[i].size <= ISP32_LITE_VIR4_MAX_SIZE)
4554 continue;
4555 idx1[k++] = i;
4556 }
4557 if (k) {
4558 is_bigmode = true;
4559 if (k != 1 ||
4560 (hw->isp_size[idx1[0]].size > ISP32_LITE_VIR2_MAX_SIZE)) {
4561 hw->is_frm_buf = true;
4562 goto using_frm_buf;
4563 } else {
4564 if (idx1[0] == ispdev->dev_id) {
4565 ispdev->multi_mode = 0;
4566 ispdev->multi_index = 0;
4567 } else {
4568 ispdev->multi_mode = 2;
4569 if (ispdev->multi_index == 0 ||
4570 ispdev->multi_index == 1)
4571 ispdev->multi_index = 3;
4572 }
4573 }
4574 } else if (ispdev->multi_index >= hw->dev_link_num) {
4575 ispdev->multi_index = idx2[ispdev->multi_index - hw->dev_link_num];
4576 }
4577 break;
4578 case 2:
4579 bigmode_max_w = ISP32_LITE_VIR2_AUTO_BIGMODE_WIDTH;
4580 bigmode_max_size = ISP32_LITE_VIR2_NOBIG_OVERFLOW_SIZE;
4581 ispdev->multi_index = ispdev->dev_id;
4582 ispdev->multi_mode = 1;
4583 /* case0: bigmode nobigmode
4584 * _________ max width:3840 max width:1920
4585 * | sensor0 | max size:3840*2160 max size:1920*1080
4586 * |_________|
4587 * | sensor1 | max size:3840*2160 max size:1920*1080
4588 * |_________|
4589 *
4590 * case1: bigmode special reg cfg
4591 * _________ max width:4224
4592 * | sensor0 | max size: mode=0 index=0
4593 * | | 3840*2160+2688*1536
4594 * |_________|
4595 * |_sensor1_| max size:2688*1536 mode=2 index=3
4596 * max width:2688
4597 */
4598 for (i = 0; i < hw->dev_num; i++) {
4599 if (!hw->isp_size[i].size) {
4600 if (i < hw->dev_link_num)
4601 idx2[n++] = i;
4602 continue;
4603 }
4604 if (hw->isp_size[i].w <= ISP32_LITE_VIR2_MAX_WIDTH &&
4605 hw->isp_size[i].size <= ISP32_LITE_VIR2_MAX_SIZE) {
4606 if (hw->isp_size[i].w > ISP32_LITE_VIR4_MAX_WIDTH ||
4607 hw->isp_size[i].size > ISP32_LITE_VIR4_MAX_SIZE)
4608 j++;
4609 continue;
4610 }
4611 idx1[k++] = i;
4612 }
4613 if (k) {
4614 is_bigmode = true;
4615 if (k == 2 || j ||
4616 hw->isp_size[idx1[k - 1]].size > (ISP32_LITE_VIR4_MAX_SIZE + ISP32_LITE_VIR2_MAX_SIZE)) {
4617 hw->is_frm_buf = true;
4618 goto using_frm_buf;
4619 } else {
4620 if (idx1[0] == ispdev->dev_id) {
4621 ispdev->multi_mode = 0;
4622 ispdev->multi_index = 0;
4623 } else {
4624 ispdev->multi_mode = 2;
4625 ispdev->multi_index = 3;
4626 }
4627 }
4628 } else if (ispdev->multi_index >= hw->dev_link_num) {
4629 ispdev->multi_index = idx2[ispdev->multi_index - hw->dev_link_num];
4630 }
4631 break;
4632 default:
4633 bigmode_max_w = ISP32_LITE_AUTO_BIGMODE_WIDTH;
4634 bigmode_max_size = ISP32_LITE_NOBIG_OVERFLOW_SIZE;
4635 ispdev->multi_mode = 0;
4636 ispdev->multi_index = 0;
4637 width = crop->width;
4638 height = crop->height;
4639 size = width * height;
4640 break;
4641 }
4642
4643 end:
4644 if (!is_bigmode &&
4645 (width > bigmode_max_w || size > bigmode_max_size))
4646 is_bigmode = true;
4647 return ispdev->is_bigmode = is_bigmode;
4648 }
4649
4650 static bool
rkisp_params_check_bigmode_v32(struct rkisp_isp_params_vdev * params_vdev)4651 rkisp_params_check_bigmode_v32(struct rkisp_isp_params_vdev *params_vdev)
4652 {
4653 struct rkisp_device *ispdev = params_vdev->dev;
4654 struct device *dev = params_vdev->dev->dev;
4655 struct rkisp_hw_dev *hw = params_vdev->dev->hw_dev;
4656 struct v4l2_rect *crop = ¶ms_vdev->dev->isp_sdev.in_crop;
4657 u32 width = hw->max_in.w, height = hw->max_in.h, size = width * height;
4658 u32 bigmode_max_w, bigmode_max_size;
4659 int k = 0, idx1[DEV_MAX] = { 0 };
4660 int n = 0, idx2[DEV_MAX] = { 0 };
4661 int i = 0, j = 0;
4662 bool is_bigmode = false;
4663
4664 if (ispdev->isp_ver == ISP_V32_L)
4665 return rkisp_params_check_bigmode_v32_lite(params_vdev);
4666
4667 multi_overflow:
4668 if (hw->is_multi_overflow) {
4669 ispdev->multi_index = 0;
4670 ispdev->multi_mode = 0;
4671 bigmode_max_w = ISP32_AUTO_BIGMODE_WIDTH;
4672 bigmode_max_size = ISP32_NOBIG_OVERFLOW_SIZE;
4673 dev_warn(dev, "over virtual isp max resolution, force to 2 readback\n");
4674 goto end;
4675 }
4676
4677 switch (hw->dev_link_num) {
4678 case 4:
4679 bigmode_max_w = ISP32_VIR4_AUTO_BIGMODE_WIDTH;
4680 bigmode_max_size = ISP32_VIR4_NOBIG_OVERFLOW_SIZE;
4681 ispdev->multi_index = ispdev->dev_id;
4682 ispdev->multi_mode = 2;
4683 /* internal buf of hw divided to four parts
4684 * bigmode nobigmode
4685 * _________ max width:1280 max width:640
4686 * |_sensor0_| max size:1280*800 max size:640*400
4687 * |_sensor1_| max size:1280*800 max size:640*400
4688 * |_sensor2_| max size:1280*800 max size:640*400
4689 * |_sensor3_| max size:1280*800 max size:640*400
4690 */
4691 for (i = 0; i < hw->dev_num; i++) {
4692 if (hw->isp_size[i].w <= ISP32_VIR4_MAX_WIDTH &&
4693 hw->isp_size[i].size <= ISP32_VIR4_MAX_SIZE)
4694 continue;
4695 dev_warn(dev, "isp%d %dx%d over four vir isp max:1280x800\n",
4696 i, hw->isp_size[i].w, hw->isp_size[i].h);
4697 hw->is_multi_overflow = true;
4698 goto multi_overflow;
4699 }
4700 break;
4701 case 3:
4702 bigmode_max_w = ISP32_VIR4_AUTO_BIGMODE_WIDTH;
4703 bigmode_max_size = ISP32_VIR4_NOBIG_OVERFLOW_SIZE;
4704 ispdev->multi_index = ispdev->dev_id;
4705 ispdev->multi_mode = 2;
4706 /* case0: bigmode nobigmode
4707 * _________ max width:1280 max width:640
4708 * |_sensor0_| max size:1280*800 max size:640*400
4709 * |_sensor1_| max size:1280*800 max size:640*400
4710 * |_sensor2_| max size:1280*800 max size:640*400
4711 * |_________|
4712 *
4713 * case1: bigmode special reg cfg
4714 * _________ max width:1920
4715 * | sensor0 | max size:1920*1080 mode=1 index=0
4716 * |_________|
4717 * |_sensor1_| max size:1280*800 mode=2 index=2
4718 * |_sensor2_| max size:1280*800 mode=2 index=3
4719 * max width:1280
4720 */
4721 for (i = 0; i < hw->dev_num; i++) {
4722 if (!hw->isp_size[i].size) {
4723 if (i < hw->dev_link_num)
4724 idx2[n++] = i;
4725 continue;
4726 }
4727 if (hw->isp_size[i].w <= ISP32_VIR4_MAX_WIDTH &&
4728 hw->isp_size[i].size <= ISP32_VIR4_MAX_SIZE)
4729 continue;
4730 idx1[k++] = i;
4731 }
4732 if (k) {
4733 is_bigmode = true;
4734 if (k != 1 ||
4735 (hw->isp_size[idx1[0]].size > ISP32_VIR2_MAX_SIZE)) {
4736 dev_warn(dev, "isp%d %dx%d over three vir isp max:1280x800\n",
4737 idx1[0], hw->isp_size[idx1[0]].w, hw->isp_size[idx1[0]].h);
4738 hw->is_multi_overflow = true;
4739 goto multi_overflow;
4740 } else {
4741 if (idx1[0] == ispdev->dev_id) {
4742 ispdev->multi_mode = 1;
4743 ispdev->multi_index = 0;
4744 } else {
4745 ispdev->multi_mode = 2;
4746 if (ispdev->multi_index == 0 ||
4747 ispdev->multi_index == 1)
4748 ispdev->multi_index = 3;
4749 }
4750 }
4751 } else if (ispdev->multi_index >= hw->dev_link_num) {
4752 ispdev->multi_index = idx2[ispdev->multi_index - hw->dev_link_num];
4753 }
4754 break;
4755 case 2:
4756 bigmode_max_w = ISP32_VIR2_AUTO_BIGMODE_WIDTH;
4757 bigmode_max_size = ISP32_VIR2_NOBIG_OVERFLOW_SIZE;
4758 ispdev->multi_index = ispdev->dev_id;
4759 ispdev->multi_mode = 1;
4760 /* case0: bigmode nobigmode
4761 * _________ max width:1920 max width:960
4762 * | sensor0 | max size:1920*1080 max size:960*540
4763 * |_________|
4764 * | sensor1 | max size:1920*1080 max size:960*540
4765 * |_________|
4766 *
4767 * case1: bigmode special reg cfg
4768 * _________ max width:3072
4769 * | sensor0 | max size: mode=0 index=0
4770 * | | 1920*1080+1280*800
4771 * |_________|
4772 * |_sensor1_| max size:1280*800 mode=2 index=3
4773 * max width:1280
4774 */
4775 for (i = 0; i < hw->dev_num; i++) {
4776 if (!hw->isp_size[i].size) {
4777 if (i < hw->dev_link_num)
4778 idx2[n++] = i;
4779 continue;
4780 }
4781 if (hw->isp_size[i].w <= ISP32_VIR2_MAX_WIDTH &&
4782 hw->isp_size[i].size <= ISP32_VIR2_MAX_SIZE) {
4783 if (hw->isp_size[i].w > ISP32_VIR4_MAX_WIDTH ||
4784 hw->isp_size[i].size > ISP32_VIR4_MAX_SIZE)
4785 j++;
4786 continue;
4787 }
4788 idx1[k++] = i;
4789 }
4790 if (k) {
4791 is_bigmode = true;
4792 if (k == 2 || j ||
4793 hw->isp_size[idx1[k - 1]].size > (ISP32_VIR4_MAX_SIZE + ISP32_VIR2_MAX_SIZE)) {
4794 dev_warn(dev, "isp%d %dx%d over two vir isp max:1920x1080\n",
4795 idx1[k - 1], hw->isp_size[idx1[k - 1]].w, hw->isp_size[idx1[k - 1]].h);
4796 hw->is_multi_overflow = true;
4797 goto multi_overflow;
4798 } else {
4799 if (idx1[0] == ispdev->dev_id) {
4800 ispdev->multi_mode = 0;
4801 ispdev->multi_index = 0;
4802 } else {
4803 ispdev->multi_mode = 2;
4804 ispdev->multi_index = 3;
4805 }
4806 }
4807 } else if (ispdev->multi_index >= hw->dev_link_num) {
4808 ispdev->multi_index = idx2[ispdev->multi_index - hw->dev_link_num];
4809 }
4810 break;
4811 default:
4812 bigmode_max_w = ISP32_AUTO_BIGMODE_WIDTH;
4813 bigmode_max_size = ISP32_NOBIG_OVERFLOW_SIZE;
4814 ispdev->multi_mode = 0;
4815 ispdev->multi_index = 0;
4816 width = crop->width;
4817 height = crop->height;
4818 size = width * height;
4819 break;
4820 }
4821
4822 end:
4823 if (!is_bigmode &&
4824 (width > bigmode_max_w || size > bigmode_max_size))
4825 is_bigmode = true;
4826 return ispdev->is_bigmode = is_bigmode;
4827 }
4828
4829 /* Not called when the camera active, thus not isr protection. */
4830 static void
rkisp_params_first_cfg_v32(struct rkisp_isp_params_vdev * params_vdev)4831 rkisp_params_first_cfg_v32(struct rkisp_isp_params_vdev *params_vdev)
4832 {
4833 struct rkisp_device *dev = params_vdev->dev;
4834 struct rkisp_isp_params_val_v32 *priv_val =
4835 (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val;
4836
4837 rkisp_params_check_bigmode_v32(params_vdev);
4838 spin_lock(¶ms_vdev->config_lock);
4839 /* override the default things */
4840 if (!params_vdev->isp32_params->module_cfg_update &&
4841 !params_vdev->isp32_params->module_en_update)
4842 dev_warn(dev->dev, "can not get first iq setting in stream on\n");
4843
4844 priv_val->bay3d_en = 0;
4845 priv_val->dhaz_en = 0;
4846 priv_val->drc_en = 0;
4847 priv_val->lsc_en = 0;
4848 priv_val->mge_en = 0;
4849 priv_val->lut3d_en = 0;
4850 if (dev->is_bigmode)
4851 rkisp_set_bits(params_vdev->dev, ISP3X_ISP_CTRL1, 0,
4852 ISP3X_BIGMODE_MANUAL | ISP3X_BIGMODE_FORCE_EN, false);
4853
4854 __isp_isr_meas_config(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL);
4855 __isp_isr_other_config(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL);
4856 __isp_isr_other_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL);
4857 __isp_isr_meas_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL);
4858
4859 priv_val->cur_hdrmge = params_vdev->isp32_params->others.hdrmge_cfg;
4860 priv_val->cur_hdrdrc = params_vdev->isp32_params->others.drc_cfg;
4861 priv_val->last_hdrmge = priv_val->cur_hdrmge;
4862 priv_val->last_hdrdrc = priv_val->cur_hdrdrc;
4863 spin_unlock(¶ms_vdev->config_lock);
4864
4865 if (dev->hw_dev->is_frm_buf && priv_val->buf_frm.mem_priv) {
4866 isp3_param_write(params_vdev, priv_val->buf_frm.size, ISP32L_FRM_BUF_WR_SIZE);
4867 isp3_param_write(params_vdev, priv_val->buf_frm.dma_addr, ISP32L_FRM_BUF_WR_BASE);
4868 isp3_param_write(params_vdev, priv_val->buf_frm.dma_addr, ISP32L_FRM_BUF_RD_BASE);
4869 }
4870 if (dev->hw_dev->is_single && (dev->isp_state & ISP_START))
4871 rkisp_set_bits(dev, ISP3X_ISP_CTRL0, 0, CIF_ISP_CTRL_ISP_CFG_UPD, true);
4872 }
4873
rkisp_save_first_param_v32(struct rkisp_isp_params_vdev * params_vdev,void * param)4874 static void rkisp_save_first_param_v32(struct rkisp_isp_params_vdev *params_vdev, void *param)
4875 {
4876 memcpy(params_vdev->isp32_params, param, params_vdev->vdev_fmt.fmt.meta.buffersize);
4877 rkisp_alloc_internal_buf(params_vdev, params_vdev->isp32_params);
4878 }
4879
rkisp_clear_first_param_v32(struct rkisp_isp_params_vdev * params_vdev)4880 static void rkisp_clear_first_param_v32(struct rkisp_isp_params_vdev *params_vdev)
4881 {
4882 memset(params_vdev->isp32_params, 0, sizeof(struct isp32_isp_params_cfg));
4883 }
4884
rkisp_deinit_mesh_buf(struct rkisp_isp_params_vdev * params_vdev,u64 module_id)4885 static void rkisp_deinit_mesh_buf(struct rkisp_isp_params_vdev *params_vdev,
4886 u64 module_id)
4887 {
4888 struct rkisp_isp_params_val_v32 *priv_val;
4889 struct rkisp_dummy_buffer *buf;
4890 int i;
4891
4892 priv_val = params_vdev->priv_val;
4893 if (!priv_val)
4894 return;
4895
4896 switch (module_id) {
4897 case ISP32_MODULE_CAC:
4898 buf = priv_val->buf_cac;
4899 break;
4900 case ISP32_MODULE_LDCH:
4901 default:
4902 buf = priv_val->buf_ldch;
4903 break;
4904 }
4905
4906 for (i = 0; i < ISP32_MESH_BUF_NUM; i++)
4907 rkisp_free_buffer(params_vdev->dev, buf + i);
4908 }
4909
rkisp_init_mesh_buf(struct rkisp_isp_params_vdev * params_vdev,struct rkisp_meshbuf_size * meshsize)4910 static int rkisp_init_mesh_buf(struct rkisp_isp_params_vdev *params_vdev,
4911 struct rkisp_meshbuf_size *meshsize)
4912 {
4913 struct rkisp_device *ispdev = params_vdev->dev;
4914 struct device *dev = ispdev->dev;
4915 struct rkisp_isp_params_val_v32 *priv_val;
4916 struct isp2x_mesh_head *mesh_head;
4917 struct rkisp_dummy_buffer *buf;
4918 u32 mesh_w = meshsize->meas_width;
4919 u32 mesh_h = meshsize->meas_height;
4920 u32 mesh_size, buf_size;
4921 int i, ret, buf_cnt = meshsize->buf_cnt;
4922 bool is_alloc;
4923
4924 priv_val = params_vdev->priv_val;
4925 if (!priv_val) {
4926 dev_err(dev, "priv_val is NULL\n");
4927 return -EINVAL;
4928 }
4929
4930 switch (meshsize->module_id) {
4931 case ISP32_MODULE_CAC:
4932 priv_val->buf_cac_idx = 0;
4933 buf = priv_val->buf_cac;
4934 mesh_w = (mesh_w + 62) / 64 * 9;
4935 mesh_h = (mesh_h + 62) / 64 * 2;
4936 mesh_size = mesh_w * 4 * mesh_h;
4937 break;
4938 case ISP32_MODULE_LDCH:
4939 default:
4940 priv_val->buf_ldch_idx = 0;
4941 buf = priv_val->buf_ldch;
4942 mesh_w = ((mesh_w + 15) / 16 + 2) / 2;
4943 mesh_h = (mesh_h + 7) / 8 + 1;
4944 mesh_size = mesh_w * 4 * mesh_h;
4945 break;
4946 }
4947
4948 if (buf_cnt <= 0 || buf_cnt > ISP32_MESH_BUF_NUM)
4949 buf_cnt = ISP32_MESH_BUF_NUM;
4950 buf_size = PAGE_ALIGN(mesh_size + ALIGN(sizeof(struct isp2x_mesh_head), 16));
4951 for (i = 0; i < buf_cnt; i++) {
4952 buf->is_need_vaddr = true;
4953 buf->is_need_dbuf = true;
4954 buf->is_need_dmafd = true;
4955 is_alloc = true;
4956 if (buf->mem_priv) {
4957 if (buf_size > buf->size) {
4958 rkisp_free_buffer(params_vdev->dev, buf);
4959 } else {
4960 is_alloc = false;
4961 buf->dma_fd = dma_buf_fd(buf->dbuf, O_CLOEXEC);
4962 if (buf->dma_fd < 0)
4963 goto err;
4964 }
4965 }
4966 if (is_alloc) {
4967 buf->size = buf_size;
4968 ret = rkisp_alloc_buffer(params_vdev->dev, buf);
4969 if (ret) {
4970 dev_err(dev, "%s failed\n", __func__);
4971 goto err;
4972 }
4973 mesh_head = (struct isp2x_mesh_head *)buf->vaddr;
4974 mesh_head->stat = MESH_BUF_INIT;
4975 mesh_head->data_oft = ALIGN(sizeof(struct isp2x_mesh_head), 16);
4976 }
4977 buf++;
4978 }
4979
4980 return 0;
4981 err:
4982 rkisp_deinit_mesh_buf(params_vdev, meshsize->module_id);
4983 return -ENOMEM;
4984 }
4985
4986 static void
rkisp_get_param_size_v32(struct rkisp_isp_params_vdev * params_vdev,unsigned int sizes[])4987 rkisp_get_param_size_v32(struct rkisp_isp_params_vdev *params_vdev,
4988 unsigned int sizes[])
4989 {
4990 sizes[0] = sizeof(struct isp32_isp_params_cfg);
4991 }
4992
4993 static void
rkisp_params_get_meshbuf_inf_v32(struct rkisp_isp_params_vdev * params_vdev,void * meshbuf_inf)4994 rkisp_params_get_meshbuf_inf_v32(struct rkisp_isp_params_vdev *params_vdev,
4995 void *meshbuf_inf)
4996 {
4997 struct rkisp_isp_params_val_v32 *priv_val;
4998 struct rkisp_meshbuf_info *meshbuf = meshbuf_inf;
4999 struct rkisp_dummy_buffer *buf;
5000 int i;
5001
5002 priv_val = params_vdev->priv_val;
5003 switch (meshbuf->module_id) {
5004 case ISP32_MODULE_CAC:
5005 priv_val->buf_cac_idx = 0;
5006 buf = priv_val->buf_cac;
5007 break;
5008 case ISP32_MODULE_LDCH:
5009 default:
5010 priv_val->buf_ldch_idx = 0;
5011 buf = priv_val->buf_ldch;
5012 break;
5013 }
5014
5015 for (i = 0; i < ISP32_MESH_BUF_NUM; i++) {
5016 if (!buf->mem_priv) {
5017 meshbuf->buf_fd[i] = -1;
5018 meshbuf->buf_size[i] = 0;
5019 } else {
5020 meshbuf->buf_fd[i] = buf->dma_fd;
5021 meshbuf->buf_size[i] = buf->size;
5022 }
5023 buf++;
5024 }
5025 }
5026
5027 static int
rkisp_params_set_meshbuf_size_v32(struct rkisp_isp_params_vdev * params_vdev,void * size)5028 rkisp_params_set_meshbuf_size_v32(struct rkisp_isp_params_vdev *params_vdev,
5029 void *size)
5030 {
5031 struct rkisp_meshbuf_size *meshsize = size;
5032
5033 return rkisp_init_mesh_buf(params_vdev, meshsize);
5034 }
5035
5036 static void
rkisp_params_free_meshbuf_v32(struct rkisp_isp_params_vdev * params_vdev,u64 module_id)5037 rkisp_params_free_meshbuf_v32(struct rkisp_isp_params_vdev *params_vdev,
5038 u64 module_id)
5039 {
5040 rkisp_deinit_mesh_buf(params_vdev, module_id);
5041 }
5042
5043 static int
rkisp_params_info2ddr_cfg_v32(struct rkisp_isp_params_vdev * params_vdev,void * arg)5044 rkisp_params_info2ddr_cfg_v32(struct rkisp_isp_params_vdev *params_vdev, void *arg)
5045 {
5046 struct rkisp_device *dev = params_vdev->dev;
5047 struct rkisp_isp_params_val_v32 *priv_val;
5048 struct rkisp_info2ddr *cfg = arg;
5049 struct rkisp_dummy_buffer *buf;
5050 u32 reg, ctrl, mask, size, val, wsize = 0, vsize = 0;
5051 int i, ret;
5052
5053 if (dev->isp_ver == ISP_V32_L && cfg->owner == RKISP_INFO2DRR_OWNER_GAIN) {
5054 dev_err(dev->dev, "%s no support gain for lite\n", __func__);
5055 return -EINVAL;
5056 }
5057 priv_val = params_vdev->priv_val;
5058
5059 if (cfg->buf_cnt > RKISP_INFO2DDR_BUF_MAX)
5060 cfg->buf_cnt = RKISP_INFO2DDR_BUF_MAX;
5061 else if (cfg->buf_cnt == 0)
5062 cfg->buf_cnt = 1;
5063 for (val = 0; val < cfg->buf_cnt; val++)
5064 cfg->buf_fd[val] = -1;
5065
5066 switch (cfg->owner) {
5067 case RKISP_INFO2DRR_OWNER_NULL:
5068 rkisp_clear_reg_cache_bits(dev, ISP3X_RAWAWB_CTRL,
5069 ISP32_RAWAWB_2DDR_PATH_EN);
5070 rkisp_clear_reg_cache_bits(dev, ISP3X_GAIN_CTRL,
5071 ISP3X_GAIN_2DDR_EN);
5072 priv_val->buf_info_owner = cfg->owner;
5073 return 0;
5074 case RKISP_INFO2DRR_OWNER_GAIN:
5075 ctrl = ISP3X_GAIN_2DDR_mode(cfg->u.gain.gain2ddr_mode);
5076 ctrl |= ISP3X_GAIN_2DDR_EN;
5077 mask = ISP3X_GAIN_2DDR_mode(3);
5078 reg = ISP3X_GAIN_CTRL;
5079
5080 if (cfg->wsize)
5081 wsize = (cfg->wsize + 7) / 8;
5082 else
5083 wsize = (dev->isp_sdev.in_crop.width + 7) / 8;
5084 /* 0 or 3: 4x8mode, 1: 2x8 mode, 2: 1x8mode */
5085 val = cfg->u.gain.gain2ddr_mode;
5086 val = (val == 1) ? 2 : ((val == 2) ? 1 : 4);
5087 if (cfg->vsize)
5088 vsize = cfg->vsize;
5089 else
5090 vsize = dev->isp_sdev.in_crop.height / val;
5091 break;
5092 case RKISP_INFO2DRR_OWNER_AWB:
5093 ctrl = cfg->u.awb.awb2ddr_sel ? ISP32_RAWAWB_2DDR_PATH_DS : 0;
5094 ctrl |= ISP32_RAWAWB_2DDR_PATH_EN;
5095 mask = ISP32_RAWAWB_2DDR_PATH_DS;
5096 reg = ISP3X_RAWAWB_CTRL;
5097
5098 val = cfg->u.awb.awb2ddr_sel ? 8 : 1;
5099 if (cfg->wsize)
5100 wsize = cfg->wsize;
5101 else
5102 wsize = dev->isp_sdev.in_crop.width * 4 / val;
5103 if (cfg->vsize)
5104 vsize = cfg->vsize;
5105 else
5106 vsize = dev->isp_sdev.in_crop.height / val;
5107 break;
5108 default:
5109 dev_err(dev->dev, "%s no support owner:%d\n", __func__, cfg->owner);
5110 return -EINVAL;
5111 }
5112
5113 if (!wsize || !vsize) {
5114 dev_err(dev->dev, "%s inval wsize:%d vsize:%d\n", __func__, wsize, vsize);
5115 return -EINVAL;
5116 }
5117
5118 wsize = ALIGN(wsize, 16);
5119 size = wsize * vsize;
5120 for (i = 0; i < cfg->buf_cnt; i++) {
5121 buf = &priv_val->buf_info[i];
5122 if (buf->mem_priv)
5123 rkisp_free_buffer(dev, buf);
5124 buf->size = size;
5125 buf->is_need_dbuf = true;
5126 buf->is_need_dmafd = true;
5127 buf->is_need_vaddr = true;
5128 ret = rkisp_alloc_buffer(dev, buf);
5129 if (ret) {
5130 dev_err(dev->dev, "%s alloc buf failed\n", __func__);
5131 goto err;
5132 }
5133 *(u32 *)buf->vaddr = RKISP_INFO2DDR_BUF_INIT;
5134 cfg->buf_fd[i] = buf->dma_fd;
5135 }
5136 buf = &priv_val->buf_info[0];
5137 isp3_param_write(params_vdev, buf->dma_addr, ISP3X_MI_GAIN_WR_BASE);
5138 isp3_param_write(params_vdev, buf->size, ISP3X_MI_GAIN_WR_SIZE);
5139 isp3_param_write(params_vdev, wsize, ISP3X_MI_GAIN_WR_LENGTH);
5140 if (dev->hw_dev->is_single)
5141 rkisp_write(dev, ISP3X_MI_WR_CTRL2, ISP3X_GAINSELF_UPD, true);
5142 rkisp_set_reg_cache_bits(dev, reg, mask, ctrl);
5143
5144 priv_val->buf_info_idx = 0;
5145 priv_val->buf_info_cnt = cfg->buf_cnt;
5146 priv_val->buf_info_owner = cfg->owner;
5147
5148 cfg->wsize = wsize;
5149 cfg->vsize = vsize;
5150 return 0;
5151 err:
5152 for (i -= 1; i >= 0; i--) {
5153 buf = &priv_val->buf_info[i];
5154 rkisp_free_buffer(dev, buf);
5155 cfg->buf_fd[i] = -1;
5156 }
5157 cfg->owner = RKISP_INFO2DRR_OWNER_NULL;
5158 cfg->buf_cnt = 0;
5159 return -ENOMEM;
5160 }
5161
5162 static void
rkisp_params_stream_stop_v32(struct rkisp_isp_params_vdev * params_vdev)5163 rkisp_params_stream_stop_v32(struct rkisp_isp_params_vdev *params_vdev)
5164 {
5165 struct rkisp_device *ispdev = params_vdev->dev;
5166 struct rkisp_isp_params_val_v32 *priv_val;
5167 int i;
5168
5169 priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val;
5170 rkisp_free_buffer(ispdev, &priv_val->buf_frm);
5171 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_iir);
5172 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_cur);
5173 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_ds);
5174 for (i = 0; i < ISP32_LSC_LUT_BUF_NUM; i++)
5175 rkisp_free_buffer(ispdev, &priv_val->buf_lsclut[i]);
5176 for (i = 0; i < ISP32_3DLUT_BUF_NUM; i++)
5177 rkisp_free_buffer(ispdev, &priv_val->buf_3dlut[i]);
5178 for (i = 0; i < RKISP_STATS_DDR_BUF_NUM; i++)
5179 rkisp_free_buffer(ispdev, &ispdev->stats_vdev.stats_buf[i]);
5180 priv_val->buf_info_owner = 0;
5181 priv_val->buf_info_cnt = 0;
5182 priv_val->buf_info_idx = -1;
5183 for (i = 0; i < RKISP_INFO2DDR_BUF_MAX; i++)
5184 rkisp_free_buffer(ispdev, &priv_val->buf_info[i]);
5185 }
5186
5187 static void
rkisp_params_fop_release_v32(struct rkisp_isp_params_vdev * params_vdev)5188 rkisp_params_fop_release_v32(struct rkisp_isp_params_vdev *params_vdev)
5189 {
5190 rkisp_deinit_mesh_buf(params_vdev, ISP32_MODULE_LDCH);
5191 rkisp_deinit_mesh_buf(params_vdev, ISP32_MODULE_CAC);
5192 }
5193
5194 /* Not called when the camera active, thus not isr protection. */
5195 static void
rkisp_params_disable_isp_v32(struct rkisp_isp_params_vdev * params_vdev)5196 rkisp_params_disable_isp_v32(struct rkisp_isp_params_vdev *params_vdev)
5197 {
5198 params_vdev->isp32_params->module_ens = 0;
5199 params_vdev->isp32_params->module_en_update = 0x7ffffffffff;
5200
5201 __isp_isr_other_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL);
5202 __isp_isr_meas_en(params_vdev, params_vdev->isp32_params, RKISP_PARAMS_ALL);
5203 }
5204
5205 static void
module_data_abandon(struct rkisp_isp_params_vdev * params_vdev,struct isp32_isp_params_cfg * params)5206 module_data_abandon(struct rkisp_isp_params_vdev *params_vdev,
5207 struct isp32_isp_params_cfg *params)
5208 {
5209 struct rkisp_isp_params_val_v32 *priv_val;
5210 struct isp2x_mesh_head *mesh_head;
5211 int i;
5212
5213 priv_val = (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val;
5214 if (params->module_cfg_update & ISP32_MODULE_LDCH) {
5215 const struct isp32_ldch_cfg *arg = ¶ms->others.ldch_cfg;
5216
5217 for (i = 0; i < ISP32_MESH_BUF_NUM; i++) {
5218 if (priv_val->buf_ldch[i].vaddr &&
5219 arg->buf_fd == priv_val->buf_ldch[i].dma_fd) {
5220 mesh_head = (struct isp2x_mesh_head *)priv_val->buf_ldch[i].vaddr;
5221 mesh_head->stat = MESH_BUF_CHIPINUSE;
5222 break;
5223 }
5224 }
5225 }
5226
5227 if (params->module_cfg_update & ISP32_MODULE_CAC) {
5228 const struct isp32_cac_cfg *arg = ¶ms->others.cac_cfg;
5229
5230 for (i = 0; i < ISP32_MESH_BUF_NUM; i++) {
5231 if (priv_val->buf_cac[i].vaddr &&
5232 arg->buf_fd == priv_val->buf_cac[i].dma_fd) {
5233 mesh_head = (struct isp2x_mesh_head *)priv_val->buf_cac[i].vaddr;
5234 mesh_head->stat = MESH_BUF_CHIPINUSE;
5235 break;
5236 }
5237 }
5238 }
5239 }
5240
5241 static void
rkisp_params_cfg_v32(struct rkisp_isp_params_vdev * params_vdev,u32 frame_id,enum rkisp_params_type type)5242 rkisp_params_cfg_v32(struct rkisp_isp_params_vdev *params_vdev,
5243 u32 frame_id, enum rkisp_params_type type)
5244 {
5245 struct isp32_isp_params_cfg *new_params = NULL;
5246 struct rkisp_buffer *cur_buf = params_vdev->cur_buf;
5247 struct rkisp_device *dev = params_vdev->dev;
5248 struct rkisp_hw_dev *hw_dev = dev->hw_dev;
5249
5250 spin_lock(¶ms_vdev->config_lock);
5251 if (!params_vdev->streamon)
5252 goto unlock;
5253
5254 /* get buffer by frame_id */
5255 while (!list_empty(¶ms_vdev->params) && !cur_buf) {
5256 cur_buf = list_first_entry(¶ms_vdev->params,
5257 struct rkisp_buffer, queue);
5258
5259 new_params = (struct isp32_isp_params_cfg *)(cur_buf->vaddr[0]);
5260 if (new_params->frame_id < frame_id) {
5261 list_del(&cur_buf->queue);
5262 if (list_empty(¶ms_vdev->params))
5263 break;
5264 else if (new_params->module_en_update ||
5265 (new_params->module_cfg_update & ISP32_MODULE_FORCE)) {
5266 /* update en immediately */
5267 __isp_isr_meas_config(params_vdev, new_params, type);
5268 __isp_isr_other_config(params_vdev, new_params, type);
5269 __isp_isr_other_en(params_vdev, new_params, type);
5270 __isp_isr_meas_en(params_vdev, new_params, type);
5271 new_params->module_cfg_update = 0;
5272 }
5273 if (new_params->module_cfg_update &
5274 (ISP32_MODULE_LDCH | ISP32_MODULE_CAC)) {
5275 module_data_abandon(params_vdev, new_params);
5276 }
5277 vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
5278 cur_buf = NULL;
5279 continue;
5280 } else if (new_params->frame_id == frame_id) {
5281 list_del(&cur_buf->queue);
5282 } else {
5283 cur_buf = NULL;
5284 }
5285 break;
5286 }
5287
5288 if (!cur_buf)
5289 goto unlock;
5290
5291 new_params = (struct isp32_isp_params_cfg *)(cur_buf->vaddr[0]);
5292 __isp_isr_meas_config(params_vdev, new_params, type);
5293 __isp_isr_other_config(params_vdev, new_params, type);
5294 __isp_isr_other_en(params_vdev, new_params, type);
5295 __isp_isr_meas_en(params_vdev, new_params, type);
5296 if (!hw_dev->is_single && type != RKISP_PARAMS_SHD)
5297 __isp_config_hdrshd(params_vdev);
5298
5299 if (type != RKISP_PARAMS_IMD) {
5300 struct rkisp_isp_params_val_v32 *priv_val =
5301 (struct rkisp_isp_params_val_v32 *)params_vdev->priv_val;
5302
5303 priv_val->last_hdrmge = priv_val->cur_hdrmge;
5304 priv_val->last_hdrdrc = priv_val->cur_hdrdrc;
5305 priv_val->cur_hdrmge = new_params->others.hdrmge_cfg;
5306 priv_val->cur_hdrdrc = new_params->others.drc_cfg;
5307 new_params->module_cfg_update = 0;
5308 vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
5309 cur_buf = NULL;
5310 }
5311
5312 unlock:
5313 params_vdev->cur_buf = cur_buf;
5314 spin_unlock(¶ms_vdev->config_lock);
5315 }
5316
5317 static void
rkisp_params_clear_fstflg(struct rkisp_isp_params_vdev * params_vdev)5318 rkisp_params_clear_fstflg(struct rkisp_isp_params_vdev *params_vdev)
5319 {
5320 u32 value = isp3_param_read(params_vdev, ISP3X_ISP_CTRL1);
5321
5322 value &= (ISP3X_YNR_FST_FRAME | ISP3X_ADRC_FST_FRAME |
5323 ISP3X_DHAZ_FST_FRAME | ISP3X_CNR_FST_FRAME |
5324 ISP3X_RAW3D_FST_FRAME);
5325 if (value) {
5326 isp3_param_clear_bits(params_vdev, ISP3X_ISP_CTRL1, value);
5327 }
5328 }
5329
5330 static void
rkisp_params_isr_v32(struct rkisp_isp_params_vdev * params_vdev,u32 isp_mis)5331 rkisp_params_isr_v32(struct rkisp_isp_params_vdev *params_vdev,
5332 u32 isp_mis)
5333 {
5334 struct rkisp_device *dev = params_vdev->dev;
5335 u32 cur_frame_id;
5336
5337 rkisp_dmarx_get_frame(dev, &cur_frame_id, NULL, NULL, true);
5338 if (isp_mis & CIF_ISP_V_START) {
5339 if (params_vdev->rdbk_times)
5340 params_vdev->rdbk_times--;
5341 if (!params_vdev->cur_buf)
5342 return;
5343
5344 if (IS_HDR_RDBK(dev->rd_mode) && !params_vdev->rdbk_times) {
5345 rkisp_params_cfg_v32(params_vdev, cur_frame_id, RKISP_PARAMS_SHD);
5346 return;
5347 }
5348 }
5349
5350 if ((isp_mis & CIF_ISP_FRAME) && !params_vdev->rdbk_times)
5351 rkisp_params_clear_fstflg(params_vdev);
5352
5353 if ((isp_mis & CIF_ISP_FRAME) && !IS_HDR_RDBK(dev->rd_mode))
5354 rkisp_params_cfg_v32(params_vdev, cur_frame_id + 1, RKISP_PARAMS_ALL);
5355 }
5356
5357 static struct rkisp_isp_params_ops rkisp_isp_params_ops_tbl = {
5358 .save_first_param = rkisp_save_first_param_v32,
5359 .clear_first_param = rkisp_clear_first_param_v32,
5360 .get_param_size = rkisp_get_param_size_v32,
5361 .first_cfg = rkisp_params_first_cfg_v32,
5362 .disable_isp = rkisp_params_disable_isp_v32,
5363 .isr_hdl = rkisp_params_isr_v32,
5364 .param_cfg = rkisp_params_cfg_v32,
5365 .param_cfgsram = rkisp_params_cfgsram_v32,
5366 .get_meshbuf_inf = rkisp_params_get_meshbuf_inf_v32,
5367 .set_meshbuf_size = rkisp_params_set_meshbuf_size_v32,
5368 .free_meshbuf = rkisp_params_free_meshbuf_v32,
5369 .stream_stop = rkisp_params_stream_stop_v32,
5370 .fop_release = rkisp_params_fop_release_v32,
5371 .check_bigmode = rkisp_params_check_bigmode_v32,
5372 .info2ddr_cfg = rkisp_params_info2ddr_cfg_v32,
5373 };
5374
rkisp_init_params_vdev_v32(struct rkisp_isp_params_vdev * params_vdev)5375 int rkisp_init_params_vdev_v32(struct rkisp_isp_params_vdev *params_vdev)
5376 {
5377 struct rkisp_isp_params_val_v32 *priv_val;
5378 int size;
5379
5380 priv_val = kzalloc(sizeof(*priv_val), GFP_KERNEL);
5381 if (!priv_val)
5382 return -ENOMEM;
5383
5384 size = sizeof(struct isp32_isp_params_cfg);
5385 params_vdev->isp32_params = vmalloc(size);
5386 if (!params_vdev->isp32_params) {
5387 kfree(priv_val);
5388 return -ENOMEM;
5389 }
5390
5391 params_vdev->priv_val = (void *)priv_val;
5392 params_vdev->ops = &rkisp_isp_params_ops_tbl;
5393 params_vdev->priv_ops = &isp_params_ops_v32;
5394 rkisp_clear_first_param_v32(params_vdev);
5395 tasklet_init(&priv_val->lsc_tasklet,
5396 isp_lsc_cfg_sram_task,
5397 (unsigned long)params_vdev);
5398 priv_val->buf_info_owner = 0;
5399 priv_val->buf_info_cnt = 0;
5400 priv_val->buf_info_idx = -1;
5401 return 0;
5402 }
5403
rkisp_uninit_params_vdev_v32(struct rkisp_isp_params_vdev * params_vdev)5404 void rkisp_uninit_params_vdev_v32(struct rkisp_isp_params_vdev *params_vdev)
5405 {
5406 struct rkisp_isp_params_val_v32 *priv_val = params_vdev->priv_val;
5407
5408 if (params_vdev->isp32_params)
5409 vfree(params_vdev->isp32_params);
5410 if (priv_val) {
5411 tasklet_kill(&priv_val->lsc_tasklet);
5412 kfree(priv_val);
5413 params_vdev->priv_val = NULL;
5414 }
5415 }
5416