1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020 Rockchip Electronics Co., Ltd. */
3
4 #include <linux/delay.h>
5 #include <linux/pm_runtime.h>
6 #include <media/v4l2-common.h>
7 #include <media/v4l2-event.h>
8 #include <media/v4l2-fh.h>
9 #include <media/v4l2-ioctl.h>
10 #include <media/v4l2-subdev.h>
11 #include <media/videobuf2-dma-contig.h>
12 #include <media/videobuf2-dma-sg.h>
13 #include "dev.h"
14 #include "regs.h"
15
16 #define CIF_ISP_REQ_BUFS_MIN 0
17
18 static int mi_frame_end(struct rkisp_stream *stream, u32 state);
19 static void rkisp_buf_queue(struct vb2_buffer *vb);
20
21 static const struct capture_fmt mp_fmts[] = {
22 /* yuv422 */
23 {
24 .fourcc = V4L2_PIX_FMT_UYVY,
25 .fmt_type = FMT_YUV,
26 .bpp = { 16 },
27 .cplanes = 1,
28 .mplanes = 1,
29 .uv_swap = 0,
30 .write_format = MI_CTRL_MP_WRITE_YUVINT,
31 .output_format = ISP32_MI_OUTPUT_YUV422,
32 }, {
33 .fourcc = V4L2_PIX_FMT_YUV422P,
34 .fmt_type = FMT_YUV,
35 .bpp = { 8, 4, 4 },
36 .cplanes = 3,
37 .mplanes = 1,
38 .uv_swap = 0,
39 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
40 .output_format = ISP32_MI_OUTPUT_YUV422,
41 }, {
42 .fourcc = V4L2_PIX_FMT_NV16,
43 .fmt_type = FMT_YUV,
44 .bpp = { 8, 16 },
45 .cplanes = 2,
46 .mplanes = 1,
47 .uv_swap = 0,
48 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
49 .output_format = ISP32_MI_OUTPUT_YUV422,
50 }, {
51 .fourcc = V4L2_PIX_FMT_NV61,
52 .fmt_type = FMT_YUV,
53 .bpp = { 8, 16 },
54 .cplanes = 2,
55 .mplanes = 1,
56 .uv_swap = 1,
57 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
58 .output_format = ISP32_MI_OUTPUT_YUV422,
59 }, {
60 .fourcc = V4L2_PIX_FMT_YUV422M,
61 .fmt_type = FMT_YUV,
62 .bpp = { 8, 8, 8 },
63 .cplanes = 3,
64 .mplanes = 3,
65 .uv_swap = 0,
66 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
67 .output_format = ISP32_MI_OUTPUT_YUV422,
68 },
69 /* yuv420 */
70 {
71 .fourcc = V4L2_PIX_FMT_NV21,
72 .fmt_type = FMT_YUV,
73 .bpp = { 8, 16 },
74 .cplanes = 2,
75 .mplanes = 1,
76 .uv_swap = 1,
77 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
78 .output_format = ISP32_MI_OUTPUT_YUV420,
79 }, {
80 .fourcc = V4L2_PIX_FMT_NV12,
81 .fmt_type = FMT_YUV,
82 .bpp = { 8, 16 },
83 .cplanes = 2,
84 .mplanes = 1,
85 .uv_swap = 0,
86 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
87 .output_format = ISP32_MI_OUTPUT_YUV420,
88 }, {
89 .fourcc = V4L2_PIX_FMT_NV21M,
90 .fmt_type = FMT_YUV,
91 .bpp = { 8, 16 },
92 .cplanes = 2,
93 .mplanes = 2,
94 .uv_swap = 1,
95 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
96 .output_format = ISP32_MI_OUTPUT_YUV420,
97 }, {
98 .fourcc = V4L2_PIX_FMT_NV12M,
99 .fmt_type = FMT_YUV,
100 .bpp = { 8, 16 },
101 .cplanes = 2,
102 .mplanes = 2,
103 .uv_swap = 0,
104 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
105 .output_format = ISP32_MI_OUTPUT_YUV420,
106 }, {
107 .fourcc = V4L2_PIX_FMT_YUV420,
108 .fmt_type = FMT_YUV,
109 .bpp = { 8, 8, 8 },
110 .cplanes = 3,
111 .mplanes = 1,
112 .uv_swap = 0,
113 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
114 .output_format = ISP32_MI_OUTPUT_YUV420,
115 },
116 /* yuv444 */
117 {
118 .fourcc = V4L2_PIX_FMT_YUV444M,
119 .fmt_type = FMT_YUV,
120 .bpp = { 8, 8, 8 },
121 .cplanes = 3,
122 .mplanes = 3,
123 .uv_swap = 0,
124 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
125 .output_format = 0,
126 },
127 /* raw */
128 {
129 .fourcc = V4L2_PIX_FMT_SRGGB8,
130 .fmt_type = FMT_BAYER,
131 .bpp = { 8 },
132 .mplanes = 1,
133 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
134 .output_format = 0,
135 }, {
136 .fourcc = V4L2_PIX_FMT_SGRBG8,
137 .fmt_type = FMT_BAYER,
138 .bpp = { 8 },
139 .mplanes = 1,
140 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
141 .output_format = 0,
142 }, {
143 .fourcc = V4L2_PIX_FMT_SGBRG8,
144 .fmt_type = FMT_BAYER,
145 .bpp = { 8 },
146 .mplanes = 1,
147 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
148 .output_format = 0,
149 }, {
150 .fourcc = V4L2_PIX_FMT_SBGGR8,
151 .fmt_type = FMT_BAYER,
152 .bpp = { 8 },
153 .mplanes = 1,
154 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
155 .output_format = 0,
156 }, {
157 .fourcc = V4L2_PIX_FMT_SRGGB10,
158 .fmt_type = FMT_BAYER,
159 .bpp = { 10 },
160 .mplanes = 1,
161 .write_format = MI_CTRL_MP_WRITE_RAW12,
162 .output_format = 0,
163 }, {
164 .fourcc = V4L2_PIX_FMT_SGRBG10,
165 .fmt_type = FMT_BAYER,
166 .bpp = { 10 },
167 .mplanes = 1,
168 .write_format = MI_CTRL_MP_WRITE_RAW12,
169 .output_format = 0,
170 }, {
171 .fourcc = V4L2_PIX_FMT_SGBRG10,
172 .fmt_type = FMT_BAYER,
173 .bpp = { 10 },
174 .mplanes = 1,
175 .write_format = MI_CTRL_MP_WRITE_RAW12,
176 .output_format = 0,
177 }, {
178 .fourcc = V4L2_PIX_FMT_SBGGR10,
179 .fmt_type = FMT_BAYER,
180 .bpp = { 10 },
181 .mplanes = 1,
182 .write_format = MI_CTRL_MP_WRITE_RAW12,
183 .output_format = 0,
184 }, {
185 .fourcc = V4L2_PIX_FMT_SRGGB12,
186 .fmt_type = FMT_BAYER,
187 .bpp = { 12 },
188 .mplanes = 1,
189 .write_format = MI_CTRL_MP_WRITE_RAW12,
190 .output_format = 0,
191 }, {
192 .fourcc = V4L2_PIX_FMT_SGRBG12,
193 .fmt_type = FMT_BAYER,
194 .bpp = { 12 },
195 .mplanes = 1,
196 .write_format = MI_CTRL_MP_WRITE_RAW12,
197 .output_format = 0,
198 }, {
199 .fourcc = V4L2_PIX_FMT_SGBRG12,
200 .fmt_type = FMT_BAYER,
201 .bpp = { 12 },
202 .mplanes = 1,
203 .write_format = MI_CTRL_MP_WRITE_RAW12,
204 .output_format = 0,
205 }, {
206 .fourcc = V4L2_PIX_FMT_SBGGR12,
207 .fmt_type = FMT_BAYER,
208 .bpp = { 12 },
209 .mplanes = 1,
210 .write_format = MI_CTRL_MP_WRITE_RAW12,
211 .output_format = 0,
212 },
213 };
214
215 static const struct capture_fmt sp_fmts[] = {
216 /* yuv422 */
217 {
218 .fourcc = V4L2_PIX_FMT_UYVY,
219 .fmt_type = FMT_YUV,
220 .bpp = { 16 },
221 .cplanes = 1,
222 .mplanes = 1,
223 .uv_swap = 0,
224 .write_format = MI_CTRL_SP_WRITE_INT,
225 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
226 }, {
227 .fourcc = V4L2_PIX_FMT_YUV422P,
228 .fmt_type = FMT_YUV,
229 .bpp = { 8, 8, 8 },
230 .cplanes = 3,
231 .mplanes = 1,
232 .uv_swap = 0,
233 .write_format = MI_CTRL_SP_WRITE_PLA,
234 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
235 }, {
236 .fourcc = V4L2_PIX_FMT_NV16,
237 .fmt_type = FMT_YUV,
238 .bpp = { 8, 16 },
239 .cplanes = 2,
240 .mplanes = 1,
241 .uv_swap = 0,
242 .write_format = MI_CTRL_SP_WRITE_SPLA,
243 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
244 }, {
245 .fourcc = V4L2_PIX_FMT_NV61,
246 .fmt_type = FMT_YUV,
247 .bpp = { 8, 16 },
248 .cplanes = 2,
249 .mplanes = 1,
250 .uv_swap = 1,
251 .write_format = MI_CTRL_SP_WRITE_SPLA,
252 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
253 }, {
254 .fourcc = V4L2_PIX_FMT_YUV422M,
255 .fmt_type = FMT_YUV,
256 .bpp = { 8, 8, 8 },
257 .cplanes = 3,
258 .mplanes = 3,
259 .uv_swap = 0,
260 .write_format = MI_CTRL_SP_WRITE_PLA,
261 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
262 },
263 /* yuv420 */
264 {
265 .fourcc = V4L2_PIX_FMT_NV21,
266 .fmt_type = FMT_YUV,
267 .bpp = { 8, 16 },
268 .cplanes = 2,
269 .mplanes = 1,
270 .uv_swap = 1,
271 .write_format = MI_CTRL_SP_WRITE_SPLA,
272 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
273 }, {
274 .fourcc = V4L2_PIX_FMT_NV12,
275 .fmt_type = FMT_YUV,
276 .bpp = { 8, 16 },
277 .cplanes = 2,
278 .mplanes = 1,
279 .uv_swap = 0,
280 .write_format = MI_CTRL_SP_WRITE_SPLA,
281 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
282 }, {
283 .fourcc = V4L2_PIX_FMT_NV21M,
284 .fmt_type = FMT_YUV,
285 .bpp = { 8, 16 },
286 .cplanes = 2,
287 .mplanes = 2,
288 .uv_swap = 1,
289 .write_format = MI_CTRL_SP_WRITE_SPLA,
290 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
291 }, {
292 .fourcc = V4L2_PIX_FMT_NV12M,
293 .fmt_type = FMT_YUV,
294 .bpp = { 8, 16 },
295 .cplanes = 2,
296 .mplanes = 2,
297 .uv_swap = 0,
298 .write_format = MI_CTRL_SP_WRITE_SPLA,
299 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
300 }, {
301 .fourcc = V4L2_PIX_FMT_YUV420,
302 .fmt_type = FMT_YUV,
303 .bpp = { 8, 8, 8 },
304 .cplanes = 3,
305 .mplanes = 1,
306 .uv_swap = 0,
307 .write_format = MI_CTRL_SP_WRITE_PLA,
308 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
309 },
310 /* yuv444 */
311 {
312 .fourcc = V4L2_PIX_FMT_YUV444M,
313 .fmt_type = FMT_YUV,
314 .bpp = { 8, 8, 8 },
315 .cplanes = 3,
316 .mplanes = 3,
317 .uv_swap = 0,
318 .write_format = MI_CTRL_SP_WRITE_PLA,
319 .output_format = MI_CTRL_SP_OUTPUT_YUV444,
320 },
321 /* yuv400 */
322 {
323 .fourcc = V4L2_PIX_FMT_GREY,
324 .fmt_type = FMT_YUV,
325 .bpp = { 8 },
326 .cplanes = 1,
327 .mplanes = 1,
328 .uv_swap = 0,
329 .write_format = MI_CTRL_SP_WRITE_PLA,
330 .output_format = MI_CTRL_SP_OUTPUT_YUV400,
331 },
332 /* rgb */
333 {
334 .fourcc = V4L2_PIX_FMT_XBGR32,
335 .fmt_type = FMT_RGB,
336 .bpp = { 32 },
337 .mplanes = 1,
338 .write_format = MI_CTRL_SP_WRITE_PLA,
339 .output_format = MI_CTRL_SP_OUTPUT_RGB888,
340 }, {
341 .fourcc = V4L2_PIX_FMT_RGB565,
342 .fmt_type = FMT_RGB,
343 .bpp = { 16 },
344 .mplanes = 1,
345 .write_format = MI_CTRL_SP_WRITE_PLA,
346 .output_format = MI_CTRL_SP_OUTPUT_RGB565,
347 },
348 };
349 static const struct capture_fmt dmatx_fmts[] = {
350 /* raw */
351 {
352 .fourcc = V4L2_PIX_FMT_SRGGB8,
353 .fmt_type = FMT_BAYER,
354 .bpp = { 8 },
355 .mplanes = 1,
356 }, {
357 .fourcc = V4L2_PIX_FMT_SGRBG8,
358 .fmt_type = FMT_BAYER,
359 .bpp = { 8 },
360 .mplanes = 1,
361 }, {
362 .fourcc = V4L2_PIX_FMT_SGBRG8,
363 .fmt_type = FMT_BAYER,
364 .bpp = { 8 },
365 .mplanes = 1,
366 }, {
367 .fourcc = V4L2_PIX_FMT_SBGGR8,
368 .fmt_type = FMT_BAYER,
369 .bpp = { 8 },
370 .mplanes = 1,
371 }, {
372 .fourcc = V4L2_PIX_FMT_GREY,
373 .fmt_type = FMT_BAYER,
374 .bpp = { 8 },
375 .mplanes = 1,
376 }, {
377 .fourcc = V4L2_PIX_FMT_SRGGB10,
378 .fmt_type = FMT_BAYER,
379 .bpp = { 10 },
380 .mplanes = 1,
381 }, {
382 .fourcc = V4L2_PIX_FMT_SGRBG10,
383 .fmt_type = FMT_BAYER,
384 .bpp = { 10 },
385 .mplanes = 1,
386 }, {
387 .fourcc = V4L2_PIX_FMT_SGBRG10,
388 .fmt_type = FMT_BAYER,
389 .bpp = { 10 },
390 .mplanes = 1,
391 }, {
392 .fourcc = V4L2_PIX_FMT_SBGGR10,
393 .fmt_type = FMT_BAYER,
394 .bpp = { 10 },
395 .mplanes = 1,
396 }, {
397 .fourcc = V4L2_PIX_FMT_Y10,
398 .fmt_type = FMT_BAYER,
399 .bpp = { 10 },
400 .mplanes = 1,
401 }, {
402 .fourcc = V4L2_PIX_FMT_SRGGB12,
403 .fmt_type = FMT_BAYER,
404 .bpp = { 12 },
405 .mplanes = 1,
406 }, {
407 .fourcc = V4L2_PIX_FMT_SGRBG12,
408 .fmt_type = FMT_BAYER,
409 .bpp = { 12 },
410 .mplanes = 1,
411 }, {
412 .fourcc = V4L2_PIX_FMT_SGBRG12,
413 .fmt_type = FMT_BAYER,
414 .bpp = { 12 },
415 .mplanes = 1,
416 }, {
417 .fourcc = V4L2_PIX_FMT_SBGGR12,
418 .fmt_type = FMT_BAYER,
419 .bpp = { 12 },
420 .mplanes = 1,
421 }, {
422 .fourcc = V4L2_PIX_FMT_Y12,
423 .fmt_type = FMT_BAYER,
424 .bpp = { 12 },
425 .mplanes = 1,
426 }, {
427 .fourcc = V4L2_PIX_FMT_YUYV,
428 .fmt_type = FMT_YUV,
429 .bpp = { 16 },
430 .mplanes = 1,
431 }, {
432 .fourcc = V4L2_PIX_FMT_YVYU,
433 .fmt_type = FMT_YUV,
434 .bpp = { 16 },
435 .mplanes = 1,
436 }, {
437 .fourcc = V4L2_PIX_FMT_UYVY,
438 .fmt_type = FMT_YUV,
439 .bpp = { 16 },
440 .mplanes = 1,
441 }, {
442 .fourcc = V4L2_PIX_FMT_VYUY,
443 .fmt_type = FMT_YUV,
444 .bpp = { 16 },
445 .mplanes = 1,
446 }, {
447 .fourcc = V4l2_PIX_FMT_EBD8,
448 .fmt_type = FMT_EBD,
449 .bpp = { 8 },
450 .mplanes = 1,
451 }, {
452 .fourcc = V4l2_PIX_FMT_SPD16,
453 .fmt_type = FMT_SPD,
454 .bpp = { 16 },
455 .mplanes = 1,
456 }
457 };
458
459 static struct stream_config rkisp2_dmatx0_stream_config = {
460 .fmts = dmatx_fmts,
461 .fmt_size = ARRAY_SIZE(dmatx_fmts),
462 .frame_end_id = MI_RAW0_WR_FRAME,
463 .mi = {
464 .y_size_init = MI_RAW0_WR_SIZE,
465 .y_base_ad_init = MI_RAW0_WR_BASE,
466 .y_base_ad_shd = MI_RAW0_WR_BASE_SHD,
467 .length = MI_RAW0_WR_LENGTH,
468 },
469 .dma = {
470 .ctrl = CSI2RX_RAW0_WR_CTRL,
471 .pic_size = CSI2RX_RAW0_WR_PIC_SIZE,
472 .pic_offs = CSI2RX_RAW0_WR_PIC_OFF,
473 },
474 };
475
476 static struct stream_config rkisp2_dmatx1_stream_config = {
477 .fmts = dmatx_fmts,
478 .fmt_size = ARRAY_SIZE(dmatx_fmts),
479 .frame_end_id = MI_RAW1_WR_FRAME,
480 .mi = {
481 .y_size_init = MI_RAW1_WR_SIZE,
482 .y_base_ad_init = MI_RAW1_WR_BASE,
483 .y_base_ad_shd = MI_RAW1_WR_BASE_SHD,
484 .length = MI_RAW1_WR_LENGTH,
485 },
486 .dma = {
487 .ctrl = CSI2RX_RAW1_WR_CTRL,
488 .pic_size = CSI2RX_RAW1_WR_PIC_SIZE,
489 .pic_offs = CSI2RX_RAW1_WR_PIC_OFF,
490 },
491 };
492
493 static struct stream_config rkisp2_dmatx3_stream_config = {
494 .fmts = dmatx_fmts,
495 .fmt_size = ARRAY_SIZE(dmatx_fmts),
496 .frame_end_id = MI_RAW3_WR_FRAME,
497 .mi = {
498 .y_size_init = MI_RAW3_WR_SIZE,
499 .y_base_ad_init = MI_RAW3_WR_BASE,
500 .y_base_ad_shd = MI_RAW3_WR_BASE_SHD,
501 .length = MI_RAW3_WR_LENGTH,
502 },
503 .dma = {
504 .ctrl = CSI2RX_RAW3_WR_CTRL,
505 .pic_size = CSI2RX_RAW3_WR_PIC_SIZE,
506 .pic_offs = CSI2RX_RAW3_WR_PIC_OFF,
507 },
508 };
509
is_rdbk_stream(struct rkisp_stream * stream)510 static bool is_rdbk_stream(struct rkisp_stream *stream)
511 {
512 struct rkisp_device *dev = stream->ispdev;
513 bool en = false;
514
515 if ((dev->hdr.op_mode == HDR_RDBK_FRAME1 &&
516 stream->id == RKISP_STREAM_DMATX2) ||
517 (dev->hdr.op_mode == HDR_RDBK_FRAME2 &&
518 (stream->id == RKISP_STREAM_DMATX2 ||
519 stream->id == RKISP_STREAM_DMATX0)))
520 en = true;
521 return en;
522 }
523
is_hdr_stream(struct rkisp_stream * stream)524 static bool is_hdr_stream(struct rkisp_stream *stream)
525 {
526 struct rkisp_device *dev = stream->ispdev;
527 bool en = false;
528
529 if (stream->id == RKISP_STREAM_DMATX0 &&
530 (dev->hdr.op_mode == HDR_FRAMEX2_DDR ||
531 dev->hdr.op_mode == HDR_LINEX2_DDR))
532 en = true;
533 return en;
534 }
535
536 /* configure dual-crop unit */
rkisp_stream_config_dcrop(struct rkisp_stream * stream,bool async)537 static int rkisp_stream_config_dcrop(struct rkisp_stream *stream, bool async)
538 {
539 struct rkisp_device *dev = stream->ispdev;
540 struct v4l2_rect *dcrop = &stream->dcrop;
541 struct v4l2_rect *input_win;
542
543 /* dual-crop unit get data from isp */
544 input_win = rkisp_get_isp_sd_win(&dev->isp_sdev);
545
546 if (dcrop->width == input_win->width &&
547 dcrop->height == input_win->height &&
548 dcrop->left == 0 && dcrop->top == 0) {
549 rkisp_disable_dcrop(stream, async);
550 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
551 "stream %d crop disabled\n", stream->id);
552 return 0;
553 }
554
555 rkisp_config_dcrop(stream, dcrop, async);
556
557 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
558 "stream %d crop: %dx%d -> %dx%d\n", stream->id,
559 input_win->width, input_win->height,
560 dcrop->width, dcrop->height);
561
562 return 0;
563 }
564
565 /* configure scale unit */
rkisp_stream_config_rsz(struct rkisp_stream * stream,bool async)566 static int rkisp_stream_config_rsz(struct rkisp_stream *stream, bool async)
567 {
568 struct rkisp_device *dev = stream->ispdev;
569 struct v4l2_pix_format_mplane output_fmt = stream->out_fmt;
570 struct capture_fmt *output_isp_fmt = &stream->out_isp_fmt;
571 struct ispsd_out_fmt *input_isp_fmt =
572 rkisp_get_ispsd_out_fmt(&dev->isp_sdev);
573 struct v4l2_rect in_y, in_c, out_y, out_c;
574 u32 xsubs_in = 1, ysubs_in = 1;
575 u32 xsubs_out = 1, ysubs_out = 1;
576
577 if (input_isp_fmt->fmt_type == FMT_BAYER)
578 goto disable;
579
580 /* set input and output sizes for scale calculation */
581 in_y.width = stream->dcrop.width;
582 in_y.height = stream->dcrop.height;
583 out_y.width = output_fmt.width;
584 out_y.height = output_fmt.height;
585
586 /* The size of Cb,Cr are related to the format */
587 if (rkisp_mbus_code_xysubs(input_isp_fmt->mbus_code, &xsubs_in, &ysubs_in)) {
588 v4l2_err(&dev->v4l2_dev, "Not xsubs/ysubs found\n");
589 return -EINVAL;
590 }
591 in_c.width = in_y.width / xsubs_in;
592 in_c.height = in_y.height / ysubs_in;
593
594 if (output_isp_fmt->fmt_type == FMT_YUV) {
595 rkisp_fcc_xysubs(output_isp_fmt->fourcc, &xsubs_out, &ysubs_out);
596 out_c.width = out_y.width / xsubs_out;
597 out_c.height = out_y.height / ysubs_out;
598 } else {
599 out_c.width = out_y.width / xsubs_in;
600 out_c.height = out_y.height / ysubs_in;
601 }
602
603 if (in_c.width == out_c.width && in_c.height == out_c.height)
604 goto disable;
605
606 /* set RSZ input and output */
607 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
608 "stream %d rsz/scale: %dx%d -> %dx%d\n",
609 stream->id, stream->dcrop.width, stream->dcrop.height,
610 output_fmt.width, output_fmt.height);
611 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
612 "chroma scaling %dx%d -> %dx%d\n",
613 in_c.width, in_c.height, out_c.width, out_c.height);
614
615 /* calculate and set scale */
616 rkisp_config_rsz(stream, &in_y, &in_c, &out_y, &out_c, async);
617
618 if (rkisp_debug)
619 rkisp_dump_rsz_regs(stream);
620
621 return 0;
622
623 disable:
624 rkisp_disable_rsz(stream, async);
625
626 return 0;
627 }
628
629 /***************************** stream operations*******************************/
630
631 /*
632 * memory base addresses should be with respect
633 * to the burst alignment restriction for AXI.
634 */
calc_burst_len(struct rkisp_stream * stream)635 static u32 calc_burst_len(struct rkisp_stream *stream)
636 {
637 struct rkisp_device *dev = stream->ispdev;
638 u32 y_size = stream->out_fmt.plane_fmt[0].bytesperline *
639 stream->out_fmt.height;
640 u32 cb_size = stream->out_fmt.plane_fmt[1].sizeimage;
641 u32 cr_size = stream->out_fmt.plane_fmt[2].sizeimage;
642 u32 cb_offs, cr_offs;
643 u32 bus = 16, burst;
644 int i;
645
646 /* y/c base addr: burstN * bus alignment */
647 cb_offs = y_size;
648 cr_offs = cr_size ? (cb_size + cb_offs) : 0;
649
650 if (!(cb_offs % (bus * 16)) && !(cr_offs % (bus * 16)))
651 burst = CIF_MI_CTRL_BURST_LEN_LUM_16 |
652 CIF_MI_CTRL_BURST_LEN_CHROM_16;
653 else if (!(cb_offs % (bus * 8)) && !(cr_offs % (bus * 8)))
654 burst = CIF_MI_CTRL_BURST_LEN_LUM_8 |
655 CIF_MI_CTRL_BURST_LEN_CHROM_8;
656 else
657 burst = CIF_MI_CTRL_BURST_LEN_LUM_4 |
658 CIF_MI_CTRL_BURST_LEN_CHROM_4;
659
660 if (cb_offs % (bus * 4) || cr_offs % (bus * 4))
661 v4l2_warn(&dev->v4l2_dev,
662 "%dx%d fmt:0x%x not support, should be %d aligned\n",
663 stream->out_fmt.width,
664 stream->out_fmt.height,
665 stream->out_fmt.pixelformat,
666 (cr_offs == 0) ? bus * 4 : bus * 16);
667
668 stream->burst = burst;
669 for (i = 0; i <= RKISP_STREAM_SP; i++)
670 if (burst > dev->cap_dev.stream[i].burst)
671 burst = dev->cap_dev.stream[i].burst;
672
673 if (stream->interlaced) {
674 if (!stream->out_fmt.width % (bus * 16))
675 stream->burst = CIF_MI_CTRL_BURST_LEN_LUM_16 |
676 CIF_MI_CTRL_BURST_LEN_CHROM_16;
677 else if (!stream->out_fmt.width % (bus * 8))
678 stream->burst = CIF_MI_CTRL_BURST_LEN_LUM_8 |
679 CIF_MI_CTRL_BURST_LEN_CHROM_8;
680 else
681 stream->burst = CIF_MI_CTRL_BURST_LEN_LUM_4 |
682 CIF_MI_CTRL_BURST_LEN_CHROM_4;
683 if (stream->out_fmt.width % (bus * 4))
684 v4l2_warn(&dev->v4l2_dev,
685 "interlaced: width should be %d aligned\n",
686 bus * 4);
687 burst = min(stream->burst, burst);
688 stream->burst = burst;
689 }
690
691 return burst;
692 }
693
694 /*
695 * configure memory interface for mainpath
696 * This should only be called when stream-on
697 */
mp_config_mi(struct rkisp_stream * stream)698 static int mp_config_mi(struct rkisp_stream *stream)
699 {
700 struct rkisp_device *dev = stream->ispdev;
701
702 /*
703 * NOTE: plane_fmt[0].sizeimage is total size of all planes for single
704 * memory plane formats, so calculate the size explicitly.
705 */
706 rkisp_write(dev, stream->config->mi.y_size_init,
707 stream->out_fmt.plane_fmt[0].bytesperline *
708 stream->out_fmt.height, false);
709 rkisp_write(dev, stream->config->mi.cb_size_init,
710 stream->out_fmt.plane_fmt[1].sizeimage, false);
711 rkisp_write(dev, stream->config->mi.cr_size_init,
712 stream->out_fmt.plane_fmt[2].sizeimage, false);
713
714 rkisp_set_bits(dev, CIF_MI_XTD_FORMAT_CTRL, CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP,
715 stream->out_isp_fmt.uv_swap ? CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP : 0, false);
716
717 rkisp_set_bits(dev, CIF_MI_CTRL, GENMASK(19, 16) | MI_CTRL_MP_FMT_MASK,
718 calc_burst_len(stream) | CIF_MI_CTRL_INIT_BASE_EN |
719 CIF_MI_CTRL_INIT_OFFSET_EN | CIF_MI_MP_AUTOUPDATE_ENABLE |
720 stream->out_isp_fmt.write_format, false);
721 mi_frame_end_int_enable(stream);
722 /* set up first buffer */
723 mi_frame_end(stream, FRAME_INIT);
724 return 0;
725 }
726
mbus_code_sp_in_fmt(u32 in_mbus_code,u32 out_fourcc,u32 * format)727 static int mbus_code_sp_in_fmt(u32 in_mbus_code, u32 out_fourcc, u32 *format)
728 {
729 switch (in_mbus_code) {
730 case MEDIA_BUS_FMT_YUYV8_2X8:
731 *format = MI_CTRL_SP_INPUT_YUV422;
732 break;
733 default:
734 return -EINVAL;
735 }
736
737 /*
738 * Only SP can support output format of YCbCr4:0:0,
739 * and the input format of SP must be YCbCr4:0:0
740 * when outputting YCbCr4:0:0.
741 * The output format of isp is YCbCr4:2:2,
742 * so the CbCr data is discarded here.
743 */
744 if (out_fourcc == V4L2_PIX_FMT_GREY)
745 *format = MI_CTRL_SP_INPUT_YUV400;
746
747 return 0;
748 }
749
750 /*
751 * configure memory interface for selfpath
752 * This should only be called when stream-on
753 */
sp_config_mi(struct rkisp_stream * stream)754 static int sp_config_mi(struct rkisp_stream *stream)
755 {
756 struct rkisp_device *dev = stream->ispdev;
757 struct capture_fmt *output_isp_fmt = &stream->out_isp_fmt;
758 struct ispsd_out_fmt *input_isp_fmt =
759 rkisp_get_ispsd_out_fmt(&dev->isp_sdev);
760 u32 sp_in_fmt, mul = 1;
761
762 if (mbus_code_sp_in_fmt(input_isp_fmt->mbus_code,
763 output_isp_fmt->fourcc, &sp_in_fmt)) {
764 v4l2_err(&dev->v4l2_dev, "Can't find the input format\n");
765 return -EINVAL;
766 }
767
768 /*
769 * NOTE: plane_fmt[0].sizeimage is total size of all planes for single
770 * memory plane formats, so calculate the size explicitly.
771 */
772 rkisp_write(dev, stream->config->mi.y_size_init,
773 stream->out_fmt.plane_fmt[0].bytesperline *
774 stream->out_fmt.height, false);
775 rkisp_write(dev, stream->config->mi.cb_size_init,
776 stream->out_fmt.plane_fmt[1].sizeimage, false);
777 rkisp_write(dev, stream->config->mi.cr_size_init,
778 stream->out_fmt.plane_fmt[2].sizeimage, false);
779 rkisp_write(dev, CIF_MI_SP_Y_PIC_WIDTH, stream->out_fmt.width, false);
780 if (stream->interlaced) {
781 mul = 2;
782 stream->u.sp.vir_offs = stream->out_fmt.plane_fmt[0].bytesperline;
783 }
784 rkisp_write(dev, CIF_MI_SP_Y_PIC_HEIGHT, stream->out_fmt.height / mul, false);
785 rkisp_write(dev, CIF_MI_SP_Y_LLENGTH, stream->u.sp.y_stride * mul, false);
786
787 rkisp_set_bits(dev, CIF_MI_XTD_FORMAT_CTRL, CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP,
788 output_isp_fmt->uv_swap ? CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP : 0, false);
789
790 rkisp_set_bits(dev, CIF_MI_CTRL, GENMASK(19, 16) | MI_CTRL_SP_FMT_MASK,
791 calc_burst_len(stream) | CIF_MI_CTRL_INIT_BASE_EN |
792 CIF_MI_CTRL_INIT_OFFSET_EN | stream->out_isp_fmt.write_format |
793 sp_in_fmt | output_isp_fmt->output_format |
794 CIF_MI_SP_AUTOUPDATE_ENABLE, false);
795 mi_frame_end_int_enable(stream);
796 /* set up first buffer */
797 mi_frame_end(stream, FRAME_INIT);
798 return 0;
799 }
800
dmatx3_config_mi(struct rkisp_stream * stream)801 static int dmatx3_config_mi(struct rkisp_stream *stream)
802 {
803 void __iomem *base = stream->ispdev->base_addr;
804 struct rkisp_device *dev = stream->ispdev;
805 struct rkisp_csi_device *csi = &dev->csi_dev;
806 u32 in_size;
807 u8 vc;
808
809 if (!csi->sink[CSI_SRC_CH4 - 1].linked || stream->streaming)
810 return -EBUSY;
811
812 if (!dev->active_sensor ||
813 (dev->active_sensor &&
814 dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY)) {
815 v4l2_err(&dev->v4l2_dev,
816 "only mipi sensor support rawwr3\n");
817 return -EINVAL;
818 }
819 atomic_set(&stream->sequence, 0);
820 in_size = stream->out_fmt.plane_fmt[0].sizeimage;
821 raw_wr_set_pic_size(stream,
822 stream->out_fmt.width,
823 stream->out_fmt.height);
824 raw_wr_set_pic_offs(stream, 0);
825 mi_set_y_size(stream, in_size);
826 mi_frame_end(stream, FRAME_INIT);
827 mi_frame_end_int_enable(stream);
828 mi_wr_ctrl2(base, SW_RAW3_WR_AUTOUPD);
829 mi_raw_length(stream);
830 vc = csi->sink[CSI_SRC_CH4 - 1].index;
831 raw_wr_ctrl(stream,
832 SW_CSI_RAW_WR_CH_EN(vc) |
833 stream->memory |
834 SW_CSI_RAW_WR_EN_ORG);
835 stream->u.dmatx.is_config = true;
836 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
837 "rawwr3 %dx%d ctrl:0x%x\n",
838 stream->out_fmt.width,
839 stream->out_fmt.height,
840 readl(base + CSI2RX_RAW3_WR_CTRL));
841 return 0;
842 }
843
dmatx2_config_mi(struct rkisp_stream * stream)844 static int dmatx2_config_mi(struct rkisp_stream *stream)
845 {
846 void __iomem *base = stream->ispdev->base_addr;
847 struct rkisp_device *dev = stream->ispdev;
848 struct rkisp_csi_device *csi = &dev->csi_dev;
849 u32 val, in_size;
850 u8 vc;
851
852 if (!csi->sink[CSI_SRC_CH3 - 1].linked || stream->streaming)
853 return -EBUSY;
854
855 if (!dev->active_sensor ||
856 (dev->active_sensor &&
857 dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY)) {
858 v4l2_err(&dev->v4l2_dev,
859 "only mipi sensor support rawwr2 path\n");
860 return -EINVAL;
861 }
862
863 if (!stream->u.dmatx.is_config) {
864 stream->u.dmatx.is_config = true;
865 atomic_set(&stream->sequence, 0);
866 in_size = stream->out_fmt.plane_fmt[0].sizeimage;
867 raw_wr_set_pic_size(stream,
868 stream->out_fmt.width,
869 stream->out_fmt.height);
870 raw_wr_set_pic_offs(stream, 0);
871 mi_set_y_size(stream, in_size);
872 mi_frame_end(stream, FRAME_INIT);
873 mi_frame_end_int_enable(stream);
874 mi_wr_ctrl2(base, SW_RAW1_WR_AUTOUPD);
875 mi_raw_length(stream);
876 vc = csi->sink[CSI_SRC_CH3 - 1].index;
877 /* short frame for esp mode */
878 if (dev->hdr.esp_mode != HDR_NORMAL_VC)
879 vc = 2;
880 val = SW_CSI_RAW_WR_CH_EN(vc);
881 val |= stream->memory;
882 if (dev->hdr.op_mode != HDR_NORMAL)
883 val |= SW_CSI_RAW_WR_EN_ORG;
884 raw_wr_ctrl(stream, val);
885 }
886 return 0;
887 }
888
dmatx0_config_mi(struct rkisp_stream * stream)889 static int dmatx0_config_mi(struct rkisp_stream *stream)
890 {
891 void __iomem *base = stream->ispdev->base_addr;
892 struct rkisp_device *dev = stream->ispdev;
893 struct rkisp_csi_device *csi = &dev->csi_dev;
894 u32 val, in_size;
895 u8 vc;
896
897 if (!csi->sink[CSI_SRC_CH1 - 1].linked || stream->streaming)
898 return -EBUSY;
899
900 if (!dev->active_sensor ||
901 (dev->active_sensor &&
902 dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY)) {
903 if (stream->id == RKISP_STREAM_DMATX0)
904 v4l2_err(&dev->v4l2_dev,
905 "only mipi sensor support rawwr0 path\n");
906 return -EINVAL;
907 }
908
909 if (!stream->u.dmatx.is_config) {
910 stream->u.dmatx.is_config = true;
911 atomic_set(&stream->sequence, 0);
912 in_size = stream->out_fmt.plane_fmt[0].sizeimage;
913 raw_wr_set_pic_size(stream,
914 stream->out_fmt.width,
915 stream->out_fmt.height);
916 raw_wr_set_pic_offs(stream, 0);
917 mi_set_y_size(stream, in_size);
918 mi_frame_end(stream, FRAME_INIT);
919 mi_frame_end_int_enable(stream);
920 mi_wr_ctrl2(base, SW_RAW0_WR_AUTOUPD);
921 mi_raw_length(stream);
922 vc = csi->sink[CSI_SRC_CH1 - 1].index;
923 /* long frame for esp mode */
924 if (dev->hdr.esp_mode != HDR_NORMAL_VC)
925 vc = 1;
926 val = SW_CSI_RAW_WR_CH_EN(vc);
927 val |= stream->memory;
928 if (dev->hdr.op_mode != HDR_NORMAL)
929 val |= SW_CSI_RAW_WR_EN_ORG;
930 raw_wr_ctrl(stream, val);
931 }
932
933 return 0;
934 }
935
mp_enable_mi(struct rkisp_stream * stream)936 static void mp_enable_mi(struct rkisp_stream *stream)
937 {
938 struct capture_fmt *isp_fmt = &stream->out_isp_fmt;
939 u32 val = CIF_MI_CTRL_MP_ENABLE;
940
941 if (isp_fmt->fmt_type == FMT_BAYER)
942 val = CIF_MI_CTRL_RAW_ENABLE;
943 rkisp_set_bits(stream->ispdev, CIF_MI_CTRL,
944 CIF_MI_CTRL_MP_ENABLE | CIF_MI_CTRL_RAW_ENABLE, val, false);
945 }
946
sp_enable_mi(struct rkisp_stream * stream)947 static void sp_enable_mi(struct rkisp_stream *stream)
948 {
949 struct rkisp_device *dev = stream->ispdev;
950 struct capture_fmt *fmt = &stream->out_isp_fmt;
951 u32 val = CIF_MI_CTRL_SP_ENABLE;
952 u32 mask = CIF_MI_SP_Y_FULL_YUV2RGB | CIF_MI_SP_CBCR_FULL_YUV2RGB;
953
954 if (fmt->fmt_type == FMT_RGB &&
955 dev->isp_sdev.quantization == V4L2_QUANTIZATION_FULL_RANGE)
956 val |= mask;
957 rkisp_set_bits(stream->ispdev, CIF_MI_CTRL, mask, val, false);
958 }
959
dmatx_enable_mi(struct rkisp_stream * stream)960 static void dmatx_enable_mi(struct rkisp_stream *stream)
961 {
962 raw_wr_enable(stream);
963 }
964
mp_disable_mi(struct rkisp_stream * stream)965 static void mp_disable_mi(struct rkisp_stream *stream)
966 {
967 rkisp_clear_bits(stream->ispdev, CIF_MI_CTRL,
968 CIF_MI_CTRL_MP_ENABLE | CIF_MI_CTRL_RAW_ENABLE, false);
969 }
970
sp_disable_mi(struct rkisp_stream * stream)971 static void sp_disable_mi(struct rkisp_stream *stream)
972 {
973 rkisp_clear_bits(stream->ispdev, CIF_MI_CTRL, CIF_MI_CTRL_SP_ENABLE, false);
974 }
975
update_dmatx_v2(struct rkisp_stream * stream)976 static void update_dmatx_v2(struct rkisp_stream *stream)
977 {
978 struct rkisp_device *dev = stream->ispdev;
979 struct rkisp_dummy_buffer *buf = NULL;
980 u8 index;
981
982 if (stream->next_buf) {
983 mi_set_y_addr(stream, stream->next_buf->buff_addr[RKISP_PLANE_Y]);
984 } else {
985 if (stream->id == RKISP_STREAM_DMATX0)
986 index = dev->hdr.index[HDR_DMA0];
987 else if (stream->id == RKISP_STREAM_DMATX2)
988 index = dev->hdr.index[HDR_DMA2];
989
990 if ((stream->id == RKISP_STREAM_DMATX0 ||
991 stream->id == RKISP_STREAM_DMATX2)) {
992 buf = hdr_dqbuf(&dev->hdr.q_tx[index]);
993 if (IS_HDR_RDBK(dev->hdr.op_mode) &&
994 !dev->dmarx_dev.trigger)
995 hdr_qbuf(&dev->hdr.q_rx[index], buf);
996 else
997 hdr_qbuf(&dev->hdr.q_tx[index], buf);
998 }
999 if (!buf && dev->hw_dev->dummy_buf.mem_priv) {
1000 buf = &dev->hw_dev->dummy_buf;
1001 stream->dbg.frameloss++;
1002 }
1003 if (buf)
1004 mi_set_y_addr(stream, buf->dma_addr);
1005 }
1006 v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
1007 "%s stream:%d Y:0x%x SHD:0x%x\n",
1008 __func__, stream->id,
1009 rkisp_read(dev, stream->config->mi.y_base_ad_init, true),
1010 rkisp_read(dev, stream->config->mi.y_base_ad_shd, true));
1011 }
1012
1013 /* Update buffer info to memory interface, it's called in interrupt */
update_mi(struct rkisp_stream * stream)1014 static void update_mi(struct rkisp_stream *stream)
1015 {
1016 struct rkisp_dummy_buffer *dummy_buf = &stream->ispdev->hw_dev->dummy_buf;
1017 struct rkisp_device *dev = stream->ispdev;
1018
1019 /* The dummy space allocated by dma_alloc_coherent is used, we can
1020 * throw data to it if there is no available buffer.
1021 */
1022 if (stream->next_buf) {
1023 rkisp_write(dev, stream->config->mi.y_base_ad_init,
1024 stream->next_buf->buff_addr[RKISP_PLANE_Y], false);
1025 rkisp_write(dev, stream->config->mi.cb_base_ad_init,
1026 stream->next_buf->buff_addr[RKISP_PLANE_CB], false);
1027 rkisp_write(dev, stream->config->mi.cr_base_ad_init,
1028 stream->next_buf->buff_addr[RKISP_PLANE_CR], false);
1029 /* mp/sp single buf updated at readback for multidevice */
1030 if (!dev->hw_dev->is_single) {
1031 stream->curr_buf = stream->next_buf;
1032 stream->next_buf = NULL;
1033 }
1034 } else if (dummy_buf->mem_priv) {
1035 rkisp_write(dev, stream->config->mi.y_base_ad_init,
1036 dummy_buf->dma_addr, false);
1037 rkisp_write(dev, stream->config->mi.cb_base_ad_init,
1038 dummy_buf->dma_addr, false);
1039 rkisp_write(dev, stream->config->mi.cr_base_ad_init,
1040 dummy_buf->dma_addr, false);
1041 stream->dbg.frameloss++;
1042 }
1043
1044 mi_set_y_offset(stream, 0);
1045 mi_set_cb_offset(stream, 0);
1046 mi_set_cr_offset(stream, 0);
1047 v4l2_dbg(2, rkisp_debug, &stream->ispdev->v4l2_dev,
1048 "%s stream:%d Y:0x%x CB:0x%x CR:0x%x | Y_SHD:0x%x\n",
1049 __func__, stream->id,
1050 rkisp_read(dev, stream->config->mi.y_base_ad_init, false),
1051 rkisp_read(dev, stream->config->mi.cb_base_ad_init, false),
1052 rkisp_read(dev, stream->config->mi.cr_base_ad_init, false),
1053 rkisp_read(dev, stream->config->mi.y_base_ad_shd, true));
1054 }
1055
mp_stop_mi(struct rkisp_stream * stream)1056 static void mp_stop_mi(struct rkisp_stream *stream)
1057 {
1058 stream->ops->disable_mi(stream);
1059 }
1060
sp_stop_mi(struct rkisp_stream * stream)1061 static void sp_stop_mi(struct rkisp_stream *stream)
1062 {
1063 stream->ops->disable_mi(stream);
1064 }
1065
dmatx_stop_mi(struct rkisp_stream * stream)1066 static void dmatx_stop_mi(struct rkisp_stream *stream)
1067 {
1068 raw_wr_disable(stream);
1069 stream->u.dmatx.is_config = false;
1070 }
1071
1072 static struct streams_ops rkisp_mp_streams_ops = {
1073 .config_mi = mp_config_mi,
1074 .enable_mi = mp_enable_mi,
1075 .disable_mi = mp_disable_mi,
1076 .stop_mi = mp_stop_mi,
1077 .set_data_path = stream_data_path,
1078 .is_stream_stopped = mp_is_stream_stopped,
1079 .update_mi = update_mi,
1080 .frame_end = mi_frame_end,
1081 };
1082
1083 static struct streams_ops rkisp_sp_streams_ops = {
1084 .config_mi = sp_config_mi,
1085 .enable_mi = sp_enable_mi,
1086 .disable_mi = sp_disable_mi,
1087 .stop_mi = sp_stop_mi,
1088 .set_data_path = stream_data_path,
1089 .is_stream_stopped = sp_is_stream_stopped,
1090 .update_mi = update_mi,
1091 .frame_end = mi_frame_end,
1092 };
1093
1094 static struct streams_ops rkisp2_dmatx0_streams_ops = {
1095 .config_mi = dmatx0_config_mi,
1096 .enable_mi = dmatx_enable_mi,
1097 .stop_mi = dmatx_stop_mi,
1098 .is_stream_stopped = dmatx0_is_stream_stopped,
1099 .update_mi = update_dmatx_v2,
1100 .frame_end = mi_frame_end,
1101 };
1102
1103 static struct streams_ops rkisp2_dmatx2_streams_ops = {
1104 .config_mi = dmatx2_config_mi,
1105 .enable_mi = dmatx_enable_mi,
1106 .stop_mi = dmatx_stop_mi,
1107 .is_stream_stopped = dmatx2_is_stream_stopped,
1108 .update_mi = update_dmatx_v2,
1109 .frame_end = mi_frame_end,
1110 };
1111
1112 static struct streams_ops rkisp2_dmatx3_streams_ops = {
1113 .config_mi = dmatx3_config_mi,
1114 .enable_mi = dmatx_enable_mi,
1115 .stop_mi = dmatx_stop_mi,
1116 .is_stream_stopped = dmatx3_is_stream_stopped,
1117 .update_mi = update_dmatx_v2,
1118 .frame_end = mi_frame_end,
1119 };
1120
rdbk_frame_end(struct rkisp_stream * stream)1121 static void rdbk_frame_end(struct rkisp_stream *stream)
1122 {
1123 struct rkisp_device *isp_dev = stream->ispdev;
1124 struct rkisp_capture_device *cap = &isp_dev->cap_dev;
1125 struct rkisp_sensor_info *sensor = isp_dev->active_sensor;
1126 u32 denominator = sensor->fi.interval.denominator;
1127 u32 numerator = sensor->fi.interval.numerator;
1128 u64 l_ts, s_ts;
1129 int ret, fps = -1, time = 30000000;
1130
1131 if (stream->id != RKISP_STREAM_DMATX2)
1132 return;
1133
1134 if (isp_dev->hdr.op_mode == HDR_RDBK_FRAME1) {
1135 rkisp_stream_buf_done(stream, cap->rdbk_buf[RDBK_S]);
1136 cap->rdbk_buf[RDBK_S] = NULL;
1137 return;
1138 }
1139
1140 if (denominator && numerator)
1141 time = numerator * 1000 / denominator * 1000 * 1000;
1142
1143 if (cap->rdbk_buf[RDBK_L] && cap->rdbk_buf[RDBK_S]) {
1144 l_ts = cap->rdbk_buf[RDBK_L]->vb.vb2_buf.timestamp;
1145 s_ts = cap->rdbk_buf[RDBK_S]->vb.vb2_buf.timestamp;
1146
1147 if ((s_ts - l_ts) > time) {
1148 ret = v4l2_subdev_call(sensor->sd,
1149 video, g_frame_interval, &sensor->fi);
1150 if (!ret) {
1151 denominator = sensor->fi.interval.denominator;
1152 numerator = sensor->fi.interval.numerator;
1153 time = numerator * 1000 / denominator * 1000 * 1000;
1154 if (numerator)
1155 fps = denominator / numerator;
1156 }
1157 if ((s_ts - l_ts) > time) {
1158 v4l2_err(&isp_dev->v4l2_dev,
1159 "timestamp no match, s:%lld l:%lld, fps:%d\n",
1160 s_ts, l_ts, fps);
1161 goto RDBK_FRM_UNMATCH;
1162 }
1163 }
1164
1165 if (s_ts < l_ts) {
1166 v4l2_err(&isp_dev->v4l2_dev,
1167 "s/l frame err, timestamp s:%lld l:%lld\n",
1168 s_ts, l_ts);
1169 goto RDBK_FRM_UNMATCH;
1170 }
1171
1172 cap->rdbk_buf[RDBK_S]->vb.sequence = cap->rdbk_buf[RDBK_L]->vb.sequence;
1173 rkisp_stream_buf_done(&cap->stream[RKISP_STREAM_DMATX0], cap->rdbk_buf[RDBK_L]);
1174 rkisp_stream_buf_done(stream, cap->rdbk_buf[RDBK_S]);
1175 } else {
1176 v4l2_err(&isp_dev->v4l2_dev, "lost long frames\n");
1177 goto RDBK_FRM_UNMATCH;
1178 }
1179
1180 cap->rdbk_buf[RDBK_L] = NULL;
1181 cap->rdbk_buf[RDBK_S] = NULL;
1182 return;
1183
1184 RDBK_FRM_UNMATCH:
1185 stream->dbg.frameloss++;
1186 if (cap->rdbk_buf[RDBK_L])
1187 rkisp_buf_queue(&cap->rdbk_buf[RDBK_L]->vb.vb2_buf);
1188 if (cap->rdbk_buf[RDBK_S])
1189 rkisp_buf_queue(&cap->rdbk_buf[RDBK_S]->vb.vb2_buf);
1190
1191 cap->rdbk_buf[RDBK_L] = NULL;
1192 cap->rdbk_buf[RDBK_S] = NULL;
1193 }
1194
1195 /*
1196 * This function is called when a frame end come. The next frame
1197 * is processing and we should set up buffer for next-next frame,
1198 * otherwise it will overflow.
1199 */
mi_frame_end(struct rkisp_stream * stream,u32 state)1200 static int mi_frame_end(struct rkisp_stream *stream, u32 state)
1201 {
1202 struct rkisp_device *dev = stream->ispdev;
1203 struct rkisp_capture_device *cap = &dev->cap_dev;
1204 struct capture_fmt *isp_fmt = &stream->out_isp_fmt;
1205 bool interlaced = stream->interlaced;
1206 unsigned long lock_flags = 0;
1207 int i = 0;
1208
1209 if (!stream->next_buf && stream->streaming &&
1210 dev->dmarx_dev.trigger == T_MANUAL &&
1211 is_rdbk_stream(stream))
1212 v4l2_info(&dev->v4l2_dev,
1213 "tx stream:%d lose frame:%d, isp state:0x%x frame:%d\n",
1214 stream->id, atomic_read(&stream->sequence) - 1,
1215 dev->isp_state, dev->dmarx_dev.cur_frame.id);
1216
1217 if (stream->curr_buf &&
1218 (!interlaced ||
1219 (stream->u.sp.field_rec == RKISP_FIELD_ODD &&
1220 stream->u.sp.field == RKISP_FIELD_EVEN))) {
1221 struct vb2_buffer *vb2_buf = &stream->curr_buf->vb.vb2_buf;
1222 u64 ns = 0;
1223
1224 /* Dequeue a filled buffer */
1225 for (i = 0; i < isp_fmt->mplanes; i++) {
1226 u32 payload_size =
1227 stream->out_fmt.plane_fmt[i].sizeimage;
1228 vb2_set_plane_payload(vb2_buf, i, payload_size);
1229 }
1230 if (stream->id == RKISP_STREAM_MP ||
1231 stream->id == RKISP_STREAM_SP) {
1232 rkisp_dmarx_get_frame(dev, &i, NULL, &ns, true);
1233 atomic_set(&stream->sequence, i);
1234 stream->curr_buf->vb.sequence = i;
1235 } else {
1236 stream->curr_buf->vb.sequence =
1237 atomic_read(&stream->sequence) - 1;
1238 }
1239 if (!ns)
1240 ns = ktime_get_ns();
1241 vb2_buf->timestamp = ns;
1242
1243 ns = ktime_get_ns();
1244 stream->dbg.interval = ns - stream->dbg.timestamp;
1245 stream->dbg.timestamp = ns;
1246 stream->dbg.id = stream->curr_buf->vb.sequence;
1247 if (stream->id == RKISP_STREAM_MP || stream->id == RKISP_STREAM_SP)
1248 stream->dbg.delay = ns - dev->isp_sdev.frm_timestamp;
1249
1250 if (!stream->streaming) {
1251 vb2_buffer_done(vb2_buf, VB2_BUF_STATE_ERROR);
1252 } else if (is_rdbk_stream(stream) &&
1253 dev->dmarx_dev.trigger == T_MANUAL) {
1254 if (stream->id == RKISP_STREAM_DMATX0) {
1255 if (cap->rdbk_buf[RDBK_L]) {
1256 v4l2_err(&dev->v4l2_dev,
1257 "multiple long data in hdr frame\n");
1258 rkisp_buf_queue(&cap->rdbk_buf[RDBK_L]->vb.vb2_buf);
1259 }
1260 cap->rdbk_buf[RDBK_L] = stream->curr_buf;
1261 } else {
1262 if (cap->rdbk_buf[RDBK_S]) {
1263 v4l2_err(&dev->v4l2_dev,
1264 "multiple short data in hdr frame\n");
1265 rkisp_buf_queue(&cap->rdbk_buf[RDBK_S]->vb.vb2_buf);
1266 }
1267 cap->rdbk_buf[RDBK_S] = stream->curr_buf;
1268 rdbk_frame_end(stream);
1269 }
1270 } else {
1271 rkisp_stream_buf_done(stream, stream->curr_buf);
1272 }
1273
1274 stream->curr_buf = NULL;
1275 }
1276
1277 if (!interlaced ||
1278 (stream->curr_buf == stream->next_buf &&
1279 stream->u.sp.field == RKISP_FIELD_ODD)) {
1280 /* Next frame is writing to it
1281 * Interlaced: odd field next buffer address
1282 */
1283 stream->curr_buf = stream->next_buf;
1284 stream->next_buf = NULL;
1285
1286 /* Set up an empty buffer for the next-next frame */
1287 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
1288 if (!list_empty(&stream->buf_queue)) {
1289 stream->next_buf =
1290 list_first_entry(&stream->buf_queue,
1291 struct rkisp_buffer,
1292 queue);
1293 list_del(&stream->next_buf->queue);
1294 }
1295 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
1296 } else if (stream->u.sp.field_rec == RKISP_FIELD_ODD &&
1297 stream->u.sp.field == RKISP_FIELD_EVEN) {
1298 /* Interlaced: event field next buffer address */
1299 if (stream->next_buf) {
1300 stream->next_buf->buff_addr[RKISP_PLANE_Y] +=
1301 stream->u.sp.vir_offs;
1302 stream->next_buf->buff_addr[RKISP_PLANE_CB] +=
1303 stream->u.sp.vir_offs;
1304 stream->next_buf->buff_addr[RKISP_PLANE_CR] +=
1305 stream->u.sp.vir_offs;
1306 }
1307 stream->curr_buf = stream->next_buf;
1308 }
1309
1310 stream->ops->update_mi(stream);
1311
1312 if (interlaced)
1313 stream->u.sp.field_rec = stream->u.sp.field;
1314
1315 return 0;
1316 }
1317
1318 /***************************** vb2 operations*******************************/
1319
1320 /*
1321 * Set flags and wait, it should stop in interrupt.
1322 * If it didn't, stop it by force.
1323 */
rkisp_stream_stop(struct rkisp_stream * stream)1324 static void rkisp_stream_stop(struct rkisp_stream *stream)
1325 {
1326 struct rkisp_device *dev = stream->ispdev;
1327 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
1328 unsigned long lock_flags = 0;
1329 int ret = 0;
1330 bool is_wait = dev->hw_dev->is_shutdown ? false : true;
1331
1332 if (!dev->dmarx_dev.trigger &&
1333 (is_rdbk_stream(stream) || is_hdr_stream(stream))) {
1334 stream->streaming = false;
1335 return;
1336 }
1337
1338 stream->stopping = true;
1339 if ((!dev->hw_dev->is_single && stream->id != RKISP_STREAM_MP &&
1340 stream->id != RKISP_STREAM_SP) || dev->hw_dev->is_single)
1341 stream->ops->stop_mi(stream);
1342
1343 if (stream->id == RKISP_STREAM_MP || stream->id == RKISP_STREAM_SP) {
1344 hdr_stop_dmatx(dev);
1345 if (IS_HDR_RDBK(dev->rd_mode) && !dev->hw_dev->is_single) {
1346 spin_lock_irqsave(&dev->hw_dev->rdbk_lock, lock_flags);
1347 if (dev->hw_dev->cur_dev_id != dev->dev_id || dev->hw_dev->is_idle) {
1348 is_wait = false;
1349 stream->ops->disable_mi(stream);
1350 }
1351 if (atomic_read(&dev->cap_dev.refcnt) == 1 && !is_wait)
1352 dev->isp_state = ISP_STOP;
1353 spin_unlock_irqrestore(&dev->hw_dev->rdbk_lock, lock_flags);
1354 }
1355 }
1356 if (is_wait && !stream->ops->is_stream_stopped(stream)) {
1357 ret = wait_event_timeout(stream->done,
1358 !stream->streaming,
1359 msecs_to_jiffies(500));
1360 if (!ret)
1361 v4l2_warn(v4l2_dev, "%s id:%d timeout\n",
1362 __func__, stream->id);
1363 }
1364
1365 stream->stopping = false;
1366 stream->streaming = false;
1367 if (stream->id == RKISP_STREAM_MP || stream->id == RKISP_STREAM_SP) {
1368 stream->ops->disable_mi(stream);
1369 rkisp_disable_dcrop(stream, true);
1370 rkisp_disable_rsz(stream, true);
1371 ret = (stream->id == RKISP_STREAM_MP) ?
1372 ISP_FRAME_MP : ISP_FRAME_SP;
1373 dev->irq_ends_mask &= ~ret;
1374 }
1375
1376 stream->burst =
1377 CIF_MI_CTRL_BURST_LEN_LUM_16 |
1378 CIF_MI_CTRL_BURST_LEN_CHROM_16;
1379 stream->interlaced = false;
1380 }
1381
1382 /*
1383 * Most of registers inside rockchip isp1 have shadow register since
1384 * they must be not changed during processing a frame.
1385 * Usually, each sub-module updates its shadow register after
1386 * processing the last pixel of a frame.
1387 */
rkisp_start(struct rkisp_stream * stream)1388 static int rkisp_start(struct rkisp_stream *stream)
1389 {
1390 struct rkisp_device *dev = stream->ispdev;
1391 int ret;
1392
1393 if (stream->ops->set_data_path)
1394 stream->ops->set_data_path(stream);
1395 ret = stream->ops->config_mi(stream);
1396 if (ret)
1397 return ret;
1398
1399 stream->ops->enable_mi(stream);
1400 if (stream->id == RKISP_STREAM_MP || stream->id == RKISP_STREAM_SP)
1401 hdr_config_dmatx(dev);
1402 stream->streaming = true;
1403
1404 return 0;
1405 }
1406
rkisp_queue_setup(struct vb2_queue * queue,unsigned int * num_buffers,unsigned int * num_planes,unsigned int sizes[],struct device * alloc_ctxs[])1407 static int rkisp_queue_setup(struct vb2_queue *queue,
1408 unsigned int *num_buffers,
1409 unsigned int *num_planes,
1410 unsigned int sizes[],
1411 struct device *alloc_ctxs[])
1412 {
1413 struct rkisp_stream *stream = queue->drv_priv;
1414 struct rkisp_device *dev = stream->ispdev;
1415 const struct v4l2_pix_format_mplane *pixm = NULL;
1416 const struct capture_fmt *isp_fmt = NULL;
1417 u32 i;
1418
1419 pixm = &stream->out_fmt;
1420 isp_fmt = &stream->out_isp_fmt;
1421 *num_planes = isp_fmt->mplanes;
1422
1423 for (i = 0; i < isp_fmt->mplanes; i++) {
1424 const struct v4l2_plane_pix_format *plane_fmt;
1425
1426 plane_fmt = &pixm->plane_fmt[i];
1427 /* height to align with 16 when allocating memory
1428 * so that Rockchip encoder can use DMA buffer directly
1429 */
1430 sizes[i] = (isp_fmt->fmt_type == FMT_YUV) ?
1431 plane_fmt->sizeimage / pixm->height *
1432 ALIGN(pixm->height, 16) :
1433 plane_fmt->sizeimage;
1434 }
1435
1436 rkisp_chk_tb_over(dev);
1437 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev, "%s count %d, size %d\n",
1438 v4l2_type_names[queue->type], *num_buffers, sizes[0]);
1439
1440 return 0;
1441 }
1442
1443 /*
1444 * The vb2_buffer are stored in rkisp_buffer, in order to unify
1445 * mplane buffer and none-mplane buffer.
1446 */
rkisp_buf_queue(struct vb2_buffer * vb)1447 static void rkisp_buf_queue(struct vb2_buffer *vb)
1448 {
1449 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1450 struct rkisp_buffer *ispbuf = to_rkisp_buffer(vbuf);
1451 struct vb2_queue *queue = vb->vb2_queue;
1452 struct rkisp_stream *stream = queue->drv_priv;
1453 unsigned long lock_flags = 0;
1454 struct v4l2_pix_format_mplane *pixm = &stream->out_fmt;
1455 struct capture_fmt *isp_fmt = &stream->out_isp_fmt;
1456 struct sg_table *sgt;
1457 int i;
1458
1459 memset(ispbuf->buff_addr, 0, sizeof(ispbuf->buff_addr));
1460 for (i = 0; i < isp_fmt->mplanes; i++) {
1461 vb2_plane_vaddr(vb, i);
1462 if (stream->ispdev->hw_dev->is_dma_sg_ops) {
1463 sgt = vb2_dma_sg_plane_desc(vb, i);
1464 ispbuf->buff_addr[i] = sg_dma_address(sgt->sgl);
1465 } else {
1466 ispbuf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
1467 }
1468 }
1469 /*
1470 * NOTE: plane_fmt[0].sizeimage is total size of all planes for single
1471 * memory plane formats, so calculate the size explicitly.
1472 */
1473 if (isp_fmt->mplanes == 1) {
1474 for (i = 0; i < isp_fmt->cplanes - 1; i++) {
1475 ispbuf->buff_addr[i + 1] = (i == 0) ?
1476 ispbuf->buff_addr[i] +
1477 pixm->plane_fmt[i].bytesperline *
1478 pixm->height :
1479 ispbuf->buff_addr[i] +
1480 pixm->plane_fmt[i].sizeimage;
1481 }
1482 }
1483
1484 v4l2_dbg(2, rkisp_debug, &stream->ispdev->v4l2_dev,
1485 "stream:%d queue buf:0x%x\n",
1486 stream->id, ispbuf->buff_addr[0]);
1487
1488 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
1489 list_add_tail(&ispbuf->queue, &stream->buf_queue);
1490 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
1491 }
1492
rkisp_create_dummy_buf(struct rkisp_stream * stream)1493 static int rkisp_create_dummy_buf(struct rkisp_stream *stream)
1494 {
1495 return rkisp_alloc_common_dummy_buf(stream->ispdev);
1496 }
1497
rkisp_destroy_dummy_buf(struct rkisp_stream * stream)1498 static void rkisp_destroy_dummy_buf(struct rkisp_stream *stream)
1499 {
1500 struct rkisp_device *dev = stream->ispdev;
1501
1502 hdr_destroy_buf(dev);
1503 rkisp_free_common_dummy_buf(dev);
1504 }
1505
destroy_buf_queue(struct rkisp_stream * stream,enum vb2_buffer_state state)1506 static void destroy_buf_queue(struct rkisp_stream *stream,
1507 enum vb2_buffer_state state)
1508 {
1509 struct rkisp_device *isp_dev = stream->ispdev;
1510 struct rkisp_capture_device *cap = &isp_dev->cap_dev;
1511 unsigned long lock_flags = 0;
1512 struct rkisp_buffer *buf;
1513
1514 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
1515 if (cap->rdbk_buf[RDBK_L] && stream->id == RKISP_STREAM_DMATX0) {
1516 list_add_tail(&cap->rdbk_buf[RDBK_L]->queue,
1517 &stream->buf_queue);
1518 if (cap->rdbk_buf[RDBK_L] == stream->curr_buf)
1519 stream->curr_buf = NULL;
1520 if (cap->rdbk_buf[RDBK_L] == stream->next_buf)
1521 stream->next_buf = NULL;
1522 cap->rdbk_buf[RDBK_L] = NULL;
1523 }
1524 if (cap->rdbk_buf[RDBK_S] && stream->id == RKISP_STREAM_DMATX2) {
1525 list_add_tail(&cap->rdbk_buf[RDBK_S]->queue,
1526 &stream->buf_queue);
1527 if (cap->rdbk_buf[RDBK_S] == stream->curr_buf)
1528 stream->curr_buf = NULL;
1529 if (cap->rdbk_buf[RDBK_S] == stream->next_buf)
1530 stream->next_buf = NULL;
1531 cap->rdbk_buf[RDBK_S] = NULL;
1532 }
1533 if (stream->curr_buf) {
1534 list_add_tail(&stream->curr_buf->queue, &stream->buf_queue);
1535 if (stream->curr_buf == stream->next_buf)
1536 stream->next_buf = NULL;
1537 stream->curr_buf = NULL;
1538 }
1539 if (stream->next_buf) {
1540 list_add_tail(&stream->next_buf->queue, &stream->buf_queue);
1541 stream->next_buf = NULL;
1542 }
1543 while (!list_empty(&stream->buf_queue)) {
1544 buf = list_first_entry(&stream->buf_queue,
1545 struct rkisp_buffer, queue);
1546 list_del(&buf->queue);
1547 vb2_buffer_done(&buf->vb.vb2_buf, state);
1548 }
1549 while (!list_empty(&stream->buf_done_list)) {
1550 buf = list_first_entry(&stream->buf_done_list,
1551 struct rkisp_buffer, queue);
1552 list_del(&buf->queue);
1553 vb2_buffer_done(&buf->vb.vb2_buf, state);
1554 }
1555 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
1556 }
1557
rkisp_stop_streaming(struct vb2_queue * queue)1558 static void rkisp_stop_streaming(struct vb2_queue *queue)
1559 {
1560 struct rkisp_stream *stream = queue->drv_priv;
1561 struct rkisp_vdev_node *node = &stream->vnode;
1562 struct rkisp_device *dev = stream->ispdev;
1563 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
1564 int ret;
1565
1566 mutex_lock(&dev->hw_dev->dev_lock);
1567
1568 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1569 "%s %d\n", __func__, stream->id);
1570
1571 if (!stream->streaming)
1572 goto end;
1573
1574 rkisp_stream_stop(stream);
1575 if (stream->id == RKISP_STREAM_MP ||
1576 stream->id == RKISP_STREAM_SP) {
1577 /* call to the other devices */
1578 media_pipeline_stop(&node->vdev.entity);
1579 ret = dev->pipe.set_stream(&dev->pipe, false);
1580 if (ret < 0)
1581 v4l2_err(v4l2_dev,
1582 "pipeline stream-off failed:%d\n", ret);
1583 }
1584
1585 /* release buffers */
1586 destroy_buf_queue(stream, VB2_BUF_STATE_ERROR);
1587
1588 ret = dev->pipe.close(&dev->pipe);
1589 if (ret < 0)
1590 v4l2_err(v4l2_dev, "pipeline close failed error:%d\n", ret);
1591 rkisp_destroy_dummy_buf(stream);
1592 atomic_dec(&dev->cap_dev.refcnt);
1593 tasklet_disable(&stream->buf_done_tasklet);
1594 end:
1595 mutex_unlock(&dev->hw_dev->dev_lock);
1596 }
1597
rkisp_stream_start(struct rkisp_stream * stream)1598 static int rkisp_stream_start(struct rkisp_stream *stream)
1599 {
1600 struct v4l2_device *v4l2_dev = &stream->ispdev->v4l2_dev;
1601 struct rkisp_device *dev = stream->ispdev;
1602 struct rkisp_stream *other = &dev->cap_dev.stream[stream->id ^ 1];
1603 bool async = false;
1604 int ret;
1605
1606 /* STREAM DMATX don't have rsz and dcrop */
1607 if (stream->id == RKISP_STREAM_DMATX0 ||
1608 stream->id == RKISP_STREAM_DMATX1 ||
1609 stream->id == RKISP_STREAM_DMATX2 ||
1610 stream->id == RKISP_STREAM_DMATX3)
1611 goto end;
1612
1613 if (other->streaming)
1614 async = true;
1615
1616 ret = rkisp_stream_config_rsz(stream, async);
1617 if (ret < 0) {
1618 v4l2_err(v4l2_dev, "config rsz failed with error %d\n", ret);
1619 return ret;
1620 }
1621
1622 /*
1623 * can't be async now, otherwise the latter started stream fails to
1624 * produce mi interrupt.
1625 */
1626 ret = rkisp_stream_config_dcrop(stream, false);
1627 if (ret < 0) {
1628 v4l2_err(v4l2_dev, "config dcrop failed with error %d\n", ret);
1629 return ret;
1630 }
1631
1632 end:
1633 return rkisp_start(stream);
1634 }
1635
1636 static int
rkisp_start_streaming(struct vb2_queue * queue,unsigned int count)1637 rkisp_start_streaming(struct vb2_queue *queue, unsigned int count)
1638 {
1639 struct rkisp_stream *stream = queue->drv_priv;
1640 struct rkisp_vdev_node *node = &stream->vnode;
1641 struct rkisp_device *dev = stream->ispdev;
1642 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
1643 int ret = -1;
1644
1645 mutex_lock(&dev->hw_dev->dev_lock);
1646
1647 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1648 "%s %d\n", __func__, stream->id);
1649
1650 if (WARN_ON(stream->streaming)) {
1651 mutex_unlock(&dev->hw_dev->dev_lock);
1652 return -EBUSY;
1653 }
1654
1655 memset(&stream->dbg, 0, sizeof(stream->dbg));
1656 atomic_inc(&dev->cap_dev.refcnt);
1657 if (!dev->isp_inp || !stream->linked) {
1658 v4l2_err(v4l2_dev, "check video link or isp input\n");
1659 goto buffer_done;
1660 }
1661
1662 if (atomic_read(&dev->cap_dev.refcnt) == 1 &&
1663 (dev->isp_inp & INP_CSI || dev->isp_inp & INP_DVP)) {
1664 /* update sensor info when first streaming */
1665 ret = rkisp_update_sensor_info(dev);
1666 if (ret < 0) {
1667 v4l2_err(v4l2_dev,
1668 "update sensor info failed %d\n",
1669 ret);
1670 goto buffer_done;
1671 }
1672 }
1673
1674 if (dev->active_sensor &&
1675 dev->active_sensor->fmt[0].format.field == V4L2_FIELD_INTERLACED) {
1676 if (stream->id != RKISP_STREAM_SP) {
1677 v4l2_err(v4l2_dev,
1678 "only selfpath support interlaced\n");
1679 ret = -EINVAL;
1680 goto buffer_done;
1681 }
1682 stream->interlaced = true;
1683 stream->u.sp.field = RKISP_FIELD_INVAL;
1684 stream->u.sp.field_rec = RKISP_FIELD_INVAL;
1685 }
1686
1687 ret = rkisp_create_dummy_buf(stream);
1688 if (ret < 0)
1689 goto buffer_done;
1690
1691 /* enable clocks/power-domains */
1692 ret = dev->pipe.open(&dev->pipe, &node->vdev.entity, true);
1693 if (ret < 0) {
1694 v4l2_err(v4l2_dev, "open cif pipeline failed %d\n", ret);
1695 goto destroy_dummy_buf;
1696 }
1697
1698 /* configure stream hardware to start */
1699 ret = rkisp_stream_start(stream);
1700 if (ret < 0) {
1701 v4l2_err(v4l2_dev, "start streaming failed\n");
1702 goto close_pipe;
1703 }
1704
1705 if (stream->id == RKISP_STREAM_MP ||
1706 stream->id == RKISP_STREAM_SP) {
1707 /* start sub-devices */
1708 ret = dev->pipe.set_stream(&dev->pipe, true);
1709 if (ret < 0)
1710 goto stop_stream;
1711
1712 ret = media_pipeline_start(&node->vdev.entity, &dev->pipe.pipe);
1713 if (ret < 0) {
1714 v4l2_err(&dev->v4l2_dev,
1715 "start pipeline failed %d\n", ret);
1716 goto pipe_stream_off;
1717 }
1718 }
1719 tasklet_enable(&stream->buf_done_tasklet);
1720 mutex_unlock(&dev->hw_dev->dev_lock);
1721 return 0;
1722
1723 pipe_stream_off:
1724 dev->pipe.set_stream(&dev->pipe, false);
1725 stop_stream:
1726 rkisp_stream_stop(stream);
1727 close_pipe:
1728 dev->pipe.close(&dev->pipe);
1729 destroy_dummy_buf:
1730 rkisp_destroy_dummy_buf(stream);
1731 buffer_done:
1732 destroy_buf_queue(stream, VB2_BUF_STATE_QUEUED);
1733 atomic_dec(&dev->cap_dev.refcnt);
1734 stream->streaming = false;
1735 mutex_unlock(&dev->hw_dev->dev_lock);
1736 return ret;
1737 }
1738
1739 static struct vb2_ops rkisp_vb2_ops = {
1740 .queue_setup = rkisp_queue_setup,
1741 .buf_queue = rkisp_buf_queue,
1742 .wait_prepare = vb2_ops_wait_prepare,
1743 .wait_finish = vb2_ops_wait_finish,
1744 .stop_streaming = rkisp_stop_streaming,
1745 .start_streaming = rkisp_start_streaming,
1746 };
1747
rkisp_init_vb2_queue(struct vb2_queue * q,struct rkisp_stream * stream,enum v4l2_buf_type buf_type)1748 static int rkisp_init_vb2_queue(struct vb2_queue *q,
1749 struct rkisp_stream *stream,
1750 enum v4l2_buf_type buf_type)
1751 {
1752 q->type = buf_type;
1753 q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
1754 q->drv_priv = stream;
1755 q->ops = &rkisp_vb2_ops;
1756 q->mem_ops = stream->ispdev->hw_dev->mem_ops;
1757 q->buf_struct_size = sizeof(struct rkisp_buffer);
1758 q->min_buffers_needed = CIF_ISP_REQ_BUFS_MIN;
1759 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1760 q->lock = &stream->apilock;
1761 q->dev = stream->ispdev->hw_dev->dev;
1762 q->allow_cache_hints = 1;
1763 q->bidirectional = 1;
1764 if (stream->ispdev->hw_dev->is_dma_contig)
1765 q->dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
1766 q->gfp_flags = GFP_DMA32;
1767 return vb2_queue_init(q);
1768 }
1769
rkisp_stream_init(struct rkisp_device * dev,u32 id)1770 static int rkisp_stream_init(struct rkisp_device *dev, u32 id)
1771 {
1772 struct rkisp_capture_device *cap_dev = &dev->cap_dev;
1773 struct rkisp_stream *stream;
1774 struct video_device *vdev;
1775 struct rkisp_vdev_node *node;
1776 int ret = 0;
1777
1778 stream = &cap_dev->stream[id];
1779 stream->id = id;
1780 stream->ispdev = dev;
1781 vdev = &stream->vnode.vdev;
1782
1783 INIT_LIST_HEAD(&stream->buf_queue);
1784 init_waitqueue_head(&stream->done);
1785 spin_lock_init(&stream->vbq_lock);
1786 stream->linked = true;
1787
1788 switch (id) {
1789 case RKISP_STREAM_SP:
1790 strlcpy(vdev->name, SP_VDEV_NAME,
1791 sizeof(vdev->name));
1792 stream->ops = &rkisp_sp_streams_ops;
1793 stream->config = &rkisp_sp_stream_config;
1794 stream->config->fmts = sp_fmts;
1795 stream->config->fmt_size = ARRAY_SIZE(sp_fmts);
1796 break;
1797 case RKISP_STREAM_DMATX0:
1798 strlcpy(vdev->name, DMATX0_VDEV_NAME,
1799 sizeof(vdev->name));
1800 stream->ops = &rkisp2_dmatx0_streams_ops;
1801 stream->config = &rkisp2_dmatx0_stream_config;
1802 break;
1803 case RKISP_STREAM_DMATX2:
1804 strlcpy(vdev->name, DMATX2_VDEV_NAME,
1805 sizeof(vdev->name));
1806 stream->ops = &rkisp2_dmatx2_streams_ops;
1807 stream->config = &rkisp2_dmatx1_stream_config;
1808 break;
1809 case RKISP_STREAM_DMATX3:
1810 strlcpy(vdev->name, DMATX3_VDEV_NAME,
1811 sizeof(vdev->name));
1812 stream->ops = &rkisp2_dmatx3_streams_ops;
1813 stream->config = &rkisp2_dmatx3_stream_config;
1814 break;
1815 default:
1816 strlcpy(vdev->name, MP_VDEV_NAME,
1817 sizeof(vdev->name));
1818 stream->ops = &rkisp_mp_streams_ops;
1819 stream->config = &rkisp_mp_stream_config;
1820 stream->config->fmts = mp_fmts;
1821 stream->config->fmt_size = ARRAY_SIZE(mp_fmts);
1822 }
1823
1824 node = vdev_to_node(vdev);
1825 rkisp_init_vb2_queue(&node->buf_queue, stream,
1826 V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
1827 ret = rkisp_register_stream_vdev(stream);
1828 if (ret < 0)
1829 return ret;
1830
1831 stream->streaming = false;
1832 stream->interlaced = false;
1833 stream->burst =
1834 CIF_MI_CTRL_BURST_LEN_LUM_16 |
1835 CIF_MI_CTRL_BURST_LEN_CHROM_16;
1836 atomic_set(&stream->sequence, 0);
1837 return 0;
1838 }
1839
rkisp_register_stream_v21(struct rkisp_device * dev)1840 int rkisp_register_stream_v21(struct rkisp_device *dev)
1841 {
1842 struct rkisp_capture_device *cap_dev = &dev->cap_dev;
1843 int ret;
1844
1845 ret = rkisp_stream_init(dev, RKISP_STREAM_MP);
1846 if (ret < 0)
1847 goto err;
1848 ret = rkisp_stream_init(dev, RKISP_STREAM_SP);
1849 if (ret < 0)
1850 goto err_free_mp;
1851 ret = rkisp_stream_init(dev, RKISP_STREAM_DMATX0);
1852 if (ret < 0)
1853 goto err_free_sp;
1854 ret = rkisp_stream_init(dev, RKISP_STREAM_DMATX2);
1855 if (ret < 0)
1856 goto err_free_tx0;
1857 ret = rkisp_stream_init(dev, RKISP_STREAM_DMATX3);
1858 if (ret < 0)
1859 goto err_free_tx2;
1860
1861 return 0;
1862 err_free_tx2:
1863 rkisp_unregister_stream_vdev(&cap_dev->stream[RKISP_STREAM_DMATX2]);
1864 err_free_tx0:
1865 rkisp_unregister_stream_vdev(&cap_dev->stream[RKISP_STREAM_DMATX0]);
1866 err_free_sp:
1867 rkisp_unregister_stream_vdev(&cap_dev->stream[RKISP_STREAM_SP]);
1868 err_free_mp:
1869 rkisp_unregister_stream_vdev(&cap_dev->stream[RKISP_STREAM_MP]);
1870 err:
1871 return ret;
1872 }
1873
rkisp_unregister_stream_v21(struct rkisp_device * dev)1874 void rkisp_unregister_stream_v21(struct rkisp_device *dev)
1875 {
1876 struct rkisp_capture_device *cap_dev = &dev->cap_dev;
1877 struct rkisp_stream *stream;
1878
1879 stream = &cap_dev->stream[RKISP_STREAM_MP];
1880 rkisp_unregister_stream_vdev(stream);
1881 stream = &cap_dev->stream[RKISP_STREAM_SP];
1882 rkisp_unregister_stream_vdev(stream);
1883 stream = &cap_dev->stream[RKISP_STREAM_DMATX0];
1884 rkisp_unregister_stream_vdev(stream);
1885 stream = &cap_dev->stream[RKISP_STREAM_DMATX2];
1886 rkisp_unregister_stream_vdev(stream);
1887 stream = &cap_dev->stream[RKISP_STREAM_DMATX3];
1888 rkisp_unregister_stream_vdev(stream);
1889 }
1890
1891 /**************** Interrupter Handler ****************/
1892
rkisp_mi_v21_isr(u32 mis_val,struct rkisp_device * dev)1893 void rkisp_mi_v21_isr(u32 mis_val, struct rkisp_device *dev)
1894 {
1895 struct rkisp_stream *stream;
1896 unsigned int i;
1897 static u8 end_tx0, end_tx2;
1898
1899 v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
1900 "mi isr:0x%x\n", mis_val);
1901
1902 if (mis_val & CIF_MI_DMA_READY)
1903 rkisp_dmarx_isr(mis_val, dev);
1904
1905 for (i = 0; i < RKISP_MAX_STREAM; ++i) {
1906 stream = &dev->cap_dev.stream[i];
1907
1908 if (!(mis_val & CIF_MI_FRAME(stream)))
1909 continue;
1910
1911 if (i == RKISP_STREAM_DMATX0)
1912 end_tx0 = true;
1913 if (i == RKISP_STREAM_DMATX2)
1914 end_tx2 = true;
1915
1916 mi_frame_end_int_clear(stream);
1917
1918 if (stream->stopping) {
1919 /*
1920 * Make sure stream is actually stopped, whose state
1921 * can be read from the shadow register, before
1922 * wake_up() thread which would immediately free all
1923 * frame buffers. stop_mi() takes effect at the next
1924 * frame end that sync the configurations to shadow
1925 * regs.
1926 */
1927 if (!dev->hw_dev->is_single &&
1928 (stream->id == RKISP_STREAM_MP || stream->id == RKISP_STREAM_SP)) {
1929 stream->stopping = false;
1930 stream->streaming = false;
1931 stream->ops->disable_mi(stream);
1932 wake_up(&stream->done);
1933 } else if (stream->ops->is_stream_stopped(stream)) {
1934 stream->stopping = false;
1935 stream->streaming = false;
1936 wake_up(&stream->done);
1937 }
1938 if (i == RKISP_STREAM_MP) {
1939 end_tx0 = false;
1940 end_tx2 = false;
1941 }
1942 } else {
1943 mi_frame_end(stream, FRAME_IRQ);
1944 if (dev->dmarx_dev.trigger == T_AUTO &&
1945 ((dev->hdr.op_mode == HDR_RDBK_FRAME1 && end_tx2) ||
1946 (dev->hdr.op_mode == HDR_RDBK_FRAME2 && end_tx2 && end_tx0))) {
1947 end_tx0 = false;
1948 end_tx2 = false;
1949 rkisp_trigger_read_back(dev, false, false, false);
1950 }
1951 }
1952 }
1953
1954 if (mis_val & CIF_MI_MP_FRAME) {
1955 stream = &dev->cap_dev.stream[RKISP_STREAM_MP];
1956 if (!stream->streaming)
1957 dev->irq_ends_mask &= ~ISP_FRAME_MP;
1958 rkisp_check_idle(dev, ISP_FRAME_MP);
1959 }
1960 if (mis_val & CIF_MI_SP_FRAME) {
1961 stream = &dev->cap_dev.stream[RKISP_STREAM_SP];
1962 if (!stream->streaming)
1963 dev->irq_ends_mask &= ~ISP_FRAME_SP;
1964 rkisp_check_idle(dev, ISP_FRAME_SP);
1965 }
1966 }
1967
rkisp_mipi_v21_isr(unsigned int phy,unsigned int packet,unsigned int overflow,unsigned int state,struct rkisp_device * dev)1968 void rkisp_mipi_v21_isr(unsigned int phy, unsigned int packet,
1969 unsigned int overflow, unsigned int state,
1970 struct rkisp_device *dev)
1971 {
1972 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
1973 struct rkisp_stream *stream;
1974 u32 packet_err = PACKET_ERR_F_BNDRY_MATCG | PACKET_ERR_F_SEQ |
1975 PACKET_ERR_FRAME_DATA | PACKET_ERR_ECC_1BIT |
1976 PACKET_ERR_ECC_2BIT | PACKET_ERR_CHECKSUM;
1977 u32 state_err = RAW_WR_SIZE_ERR | RAW_RD_SIZE_ERR;
1978 int i, id;
1979
1980 v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
1981 "csi state:0x%x\n", state);
1982 dev->csi_dev.irq_cnt++;
1983 if (phy && (dev->isp_inp & INP_CSI) &&
1984 dev->csi_dev.err_cnt++ < RKISP_CONTI_ERR_MAX)
1985 v4l2_warn(v4l2_dev, "MIPI error: phy: 0x%08x\n", phy);
1986 if ((packet & packet_err) && (dev->isp_inp & INP_CSI) &&
1987 dev->csi_dev.err_cnt < RKISP_CONTI_ERR_MAX) {
1988 if (packet & 0xfff)
1989 dev->csi_dev.err_cnt++;
1990 v4l2_warn(v4l2_dev, "MIPI error: packet: 0x%08x\n", packet);
1991 }
1992 if (overflow && dev->csi_dev.err_cnt++ < RKISP_CONTI_ERR_MAX)
1993 v4l2_warn(v4l2_dev, "MIPI error: overflow: 0x%08x\n", overflow);
1994 if (state & state_err)
1995 v4l2_warn(v4l2_dev, "MIPI error: size: 0x%08x\n", state);
1996 if (state & ISP21_MIPI_DROP_FRM)
1997 v4l2_warn(v4l2_dev, "MIPI drop frame\n");
1998
1999 /* first Y_STATE irq as csi sof event */
2000 if (state & (RAW0_Y_STATE | RAW1_Y_STATE)) {
2001 for (i = 0; i < HDR_DMA_MAX - 1; i++) {
2002 if (!((RAW0_Y_STATE << i) & state) ||
2003 dev->csi_dev.tx_first[i])
2004 continue;
2005 dev->csi_dev.tx_first[i] = true;
2006 id = i ? 2 : 0;
2007 rkisp_csi_sof(dev, id);
2008 stream = &dev->cap_dev.stream[id + RKISP_STREAM_DMATX0];
2009 atomic_inc(&stream->sequence);
2010 }
2011 }
2012 if (state & (RAW0_WR_FRAME | RAW1_WR_FRAME)) {
2013 dev->csi_dev.err_cnt = 0;
2014 for (i = 0; i < HDR_DMA_MAX - 1; i++) {
2015 if (!((RAW0_WR_FRAME << i) & state))
2016 continue;
2017 if (!dev->csi_dev.tx_first[i]) {
2018 id = i ? RKISP_STREAM_DMATX2 : RKISP_STREAM_DMATX0;
2019 stream = &dev->cap_dev.stream[id];
2020 atomic_inc(&stream->sequence);
2021 }
2022 dev->csi_dev.tx_first[i] = false;
2023 }
2024 }
2025 if (state & ISP21_RAW3_WR_FRAME) {
2026 dev->csi_dev.err_cnt = 0;
2027 stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX3];
2028 atomic_inc(&stream->sequence);
2029 }
2030
2031 if (dev->csi_dev.err_cnt > RKISP_CONTI_ERR_MAX) {
2032 if (!(dev->isp_state & ISP_MIPI_ERROR)) {
2033 dev->isp_state |= ISP_MIPI_ERROR;
2034 rkisp_write(dev, CSI2RX_MASK_PHY, 0, true);
2035 rkisp_write(dev, CSI2RX_MASK_PACKET, 0, true);
2036 rkisp_write(dev, CSI2RX_MASK_OVERFLOW, 0, true);
2037 if (dev->hw_dev->monitor.is_en) {
2038 if (!completion_done(&dev->hw_dev->monitor.cmpl))
2039 complete(&dev->hw_dev->monitor.cmpl);
2040 dev->hw_dev->monitor.state |= ISP_MIPI_ERROR;
2041 }
2042 }
2043 }
2044 }
2045