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Searched refs:intel_de_write (Results 1 – 25 of 35) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/
H A Dintel_vdsc.c521 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0, in intel_dsc_pps_configure()
528 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0, in intel_dsc_pps_configure()
531 intel_de_write(dev_priv, in intel_dsc_pps_configure()
535 intel_de_write(dev_priv, in intel_dsc_pps_configure()
545 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1, in intel_dsc_pps_configure()
552 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1, in intel_dsc_pps_configure()
555 intel_de_write(dev_priv, in intel_dsc_pps_configure()
559 intel_de_write(dev_priv, in intel_dsc_pps_configure()
570 intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2, in intel_dsc_pps_configure()
577 intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2, in intel_dsc_pps_configure()
[all …]
H A Dvlv_dsi.c103 intel_de_write(dev_priv, reg, val); in write_data()
165 intel_de_write(dev_priv, MIPI_INTR_STAT(port), in intel_dsi_host_transfer()
175 intel_de_write(dev_priv, ctrl_reg, in intel_dsi_host_transfer()
231 intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); in dpi_send_cmd()
238 intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd); in dpi_send_cmd()
338 intel_de_write(dev_priv, MIPI_CTRL(port), in glk_dsi_enable_io()
345 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp); in glk_dsi_enable_io()
354 intel_de_write(dev_priv, MIPI_CTRL(port), tmp); in glk_dsi_enable_io()
389 intel_de_write(dev_priv, MIPI_CTRL(PORT_A), in glk_dsi_device_ready()
398 intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); in glk_dsi_device_ready()
[all …]
H A Dintel_color.c160 intel_de_write(dev_priv, PIPE_CSC_PREOFF_HI(pipe), preoff[0]); in ilk_update_pipe_csc()
161 intel_de_write(dev_priv, PIPE_CSC_PREOFF_ME(pipe), preoff[1]); in ilk_update_pipe_csc()
162 intel_de_write(dev_priv, PIPE_CSC_PREOFF_LO(pipe), preoff[2]); in ilk_update_pipe_csc()
164 intel_de_write(dev_priv, PIPE_CSC_COEFF_RY_GY(pipe), in ilk_update_pipe_csc()
166 intel_de_write(dev_priv, PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16); in ilk_update_pipe_csc()
168 intel_de_write(dev_priv, PIPE_CSC_COEFF_RU_GU(pipe), in ilk_update_pipe_csc()
170 intel_de_write(dev_priv, PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16); in ilk_update_pipe_csc()
172 intel_de_write(dev_priv, PIPE_CSC_COEFF_RV_GV(pipe), in ilk_update_pipe_csc()
174 intel_de_write(dev_priv, PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16); in ilk_update_pipe_csc()
177 intel_de_write(dev_priv, PIPE_CSC_POSTOFF_HI(pipe), in ilk_update_pipe_csc()
[all …]
H A Dintel_combo_phy.c87 intel_de_write(dev_priv, ICL_PORT_COMP_DW1(phy), val); in cnl_set_procmon_ref_values()
89 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); in cnl_set_procmon_ref_values()
90 intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10); in cnl_set_procmon_ref_values()
157 intel_de_write(dev_priv, CHICKEN_MISC_2, val); in cnl_combo_phys_init()
164 intel_de_write(dev_priv, CNL_PORT_COMP_DW0, val); in cnl_combo_phys_init()
168 intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val); in cnl_combo_phys_init()
181 intel_de_write(dev_priv, CHICKEN_MISC_2, val); in cnl_combo_phys_uninit()
350 intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val); in intel_combo_phy_power_up_lanes()
387 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); in icl_combo_phys_init()
395 intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val); in icl_combo_phys_init()
[all …]
H A Dicl_dsi.c141 intel_de_write(dev_priv, DSI_CMD_TXPYLD(dsi_trans), tmp); in add_payld_to_queue()
181 intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp); in dsi_send_pkt_hdr()
226 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); in dsi_program_swing_and_deemphasis()
233 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); in dsi_program_swing_and_deemphasis()
241 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); in dsi_program_swing_and_deemphasis()
249 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); in dsi_program_swing_and_deemphasis()
257 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); in dsi_program_swing_and_deemphasis()
268 intel_de_write(dev_priv, in dsi_program_swing_and_deemphasis()
305 intel_de_write(dev_priv, DSS_CTL2, dss_ctl2); in configure_dual_link_mode()
311 intel_de_write(dev_priv, DSS_CTL1, dss_ctl1); in configure_dual_link_mode()
[all …]
H A Dintel_tv.c929 intel_de_write(dev_priv, TV_CTL, in intel_enable_tv()
942 intel_de_write(dev_priv, TV_CTL, in intel_disable_tv()
1384 intel_de_write(dev_priv, TV_H_CTL_1, hctl1); in set_tv_mode_timings()
1385 intel_de_write(dev_priv, TV_H_CTL_2, hctl2); in set_tv_mode_timings()
1386 intel_de_write(dev_priv, TV_H_CTL_3, hctl3); in set_tv_mode_timings()
1387 intel_de_write(dev_priv, TV_V_CTL_1, vctl1); in set_tv_mode_timings()
1388 intel_de_write(dev_priv, TV_V_CTL_2, vctl2); in set_tv_mode_timings()
1389 intel_de_write(dev_priv, TV_V_CTL_3, vctl3); in set_tv_mode_timings()
1390 intel_de_write(dev_priv, TV_V_CTL_4, vctl4); in set_tv_mode_timings()
1391 intel_de_write(dev_priv, TV_V_CTL_5, vctl5); in set_tv_mode_timings()
[all …]
H A Dintel_ddi.c1247 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), in intel_prepare_dp_ddi_buffers()
1249 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), in intel_prepare_dp_ddi_buffers()
1280 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), in intel_prepare_hdmi_ddi_buffers()
1282 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), in intel_prepare_hdmi_ddi_buffers()
1400 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train()
1407 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
1413 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
1417 intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel); in hsw_fdi_link_train()
1424 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
1434 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), in hsw_fdi_link_train()
[all …]
H A Dintel_fbc.c89 intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl); in i8xx_fbc_deactivate()
119 intel_de_write(dev_priv, FBC_TAG(i), 0); in i8xx_fbc_activate()
129 intel_de_write(dev_priv, FBC_CONTROL2, fbc_ctl2); in i8xx_fbc_activate()
130 intel_de_write(dev_priv, FBC_FENCE_OFF, in i8xx_fbc_activate()
142 intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl); in i8xx_fbc_activate()
163 intel_de_write(dev_priv, DPFC_FENCE_YOFF, in g4x_fbc_activate()
166 intel_de_write(dev_priv, DPFC_FENCE_YOFF, 0); in g4x_fbc_activate()
170 intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); in g4x_fbc_activate()
181 intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl); in g4x_fbc_deactivate()
219 intel_de_write(dev_priv, MSG_FBC_REND_STATE, FBC_REND_NUKE); in snb_fbc_recompress()
[all …]
H A Dintel_audio.c313 intel_de_write(dev_priv, reg_elda, tmp); in intel_eld_uptodate()
340 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp); in g4x_audio_codec_disable()
372 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp); in g4x_audio_codec_enable()
377 intel_de_write(dev_priv, G4X_HDMIW_HDMIEDID, in g4x_audio_codec_enable()
382 intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp); in g4x_audio_codec_enable()
417 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp); in hsw_dp_audio_config_update()
430 intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); in hsw_dp_audio_config_update()
463 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp); in hsw_hdmi_audio_config_update()
472 intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); in hsw_hdmi_audio_config_update()
506 intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp); in hsw_audio_codec_disable()
[all …]
H A Dintel_panel.c607 intel_de_write(dev_priv, BLC_PWM_PCH_CTL2, val | level); in lpt_set_backlight()
617 intel_de_write(dev_priv, BLC_PWM_CPU_CTL, tmp | level); in pch_set_backlight()
645 intel_de_write(dev_priv, BLC_PWM_CTL, tmp | level); in i9xx_set_backlight()
656 intel_de_write(dev_priv, VLV_BLC_PWM_CTL(pipe), tmp | level); in vlv_set_backlight()
665 intel_de_write(dev_priv, in bxt_set_backlight()
749 intel_de_write(dev_priv, BLC_PWM_CPU_CTL2, in lpt_disable_backlight()
754 intel_de_write(dev_priv, BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); in lpt_disable_backlight()
766 intel_de_write(dev_priv, BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); in pch_disable_backlight()
769 intel_de_write(dev_priv, BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); in pch_disable_backlight()
785 intel_de_write(dev_priv, BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE); in i965_disable_backlight()
[all …]
H A Dvlv_dsi_pll.c245 intel_de_write(dev_priv, BXT_DSI_PLL_ENABLE, val); in bxt_dsi_pll_disable()
351 intel_de_write(dev_priv, MIPI_CTRL(port), in vlv_dsi_reset_clocks()
398 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1, in glk_dsi_program_esc_clock()
400 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2, in glk_dsi_program_esc_clock()
455 intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp); in bxt_dsi_program_clocks()
518 intel_de_write(dev_priv, BXT_DSI_PLL_CTL, config->dsi_pll.ctrl); in bxt_dsi_pll_enable()
532 intel_de_write(dev_priv, BXT_DSI_PLL_ENABLE, val); in bxt_dsi_pll_enable()
558 intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp); in bxt_dsi_reset_clocks()
562 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1, tmp); in bxt_dsi_reset_clocks()
566 intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2, tmp); in bxt_dsi_reset_clocks()
[all …]
H A Dintel_dpll_mgr.c432 intel_de_write(dev_priv, PCH_FP0(id), pll->state.hw_state.fp0); in ibx_pch_dpll_prepare()
433 intel_de_write(dev_priv, PCH_FP1(id), pll->state.hw_state.fp1); in ibx_pch_dpll_prepare()
457 intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
468 intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); in ibx_pch_dpll_enable()
478 intel_de_write(dev_priv, PCH_DPLL(id), 0); in ibx_pch_dpll_disable()
558 intel_de_write(dev_priv, WRPLL_CTL(id), pll->state.hw_state.wrpll); in hsw_ddi_wrpll_enable()
566 intel_de_write(dev_priv, SPLL_CTL, pll->state.hw_state.spll); in hsw_ddi_spll_enable()
578 intel_de_write(dev_priv, WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE); in hsw_ddi_wrpll_disable()
596 intel_de_write(dev_priv, SPLL_CTL, val & ~SPLL_PLL_ENABLE); in hsw_ddi_spll_disable()
1175 intel_de_write(dev_priv, DPLL_CTRL1, val); in skl_ddi_pll_write_ctrl1()
[all …]
H A Dintel_hdmi.c230 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); in g4x_write_infoframe()
233 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data); in g4x_write_infoframe()
238 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0); in g4x_write_infoframe()
244 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); in g4x_write_infoframe()
262 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); in g4x_read_infoframe()
304 intel_de_write(dev_priv, reg, val); in ibx_write_infoframe()
307 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), in ibx_write_infoframe()
313 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0); in ibx_write_infoframe()
319 intel_de_write(dev_priv, reg, val); in ibx_write_infoframe()
338 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); in ibx_read_infoframe()
[all …]
H A Dintel_hdcp.c179 intel_de_write(dev_priv, HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER); in intel_hdcp_clear_keys()
180 intel_de_write(dev_priv, HDCP_KEY_STATUS, in intel_hdcp_clear_keys()
218 intel_de_write(dev_priv, HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER); in intel_hdcp_load_keys()
231 intel_de_write(dev_priv, HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER); in intel_hdcp_load_keys()
239 intel_de_write(dev_priv, HDCP_SHA_TEXT, sha_text); in intel_write_sha_text()
306 intel_de_write(dev_priv, HDCP_SHA_V_PRIME(i), vprime); in intel_hdcp_validate_v_prime()
323 intel_de_write(dev_priv, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); in intel_hdcp_validate_v_prime()
342 intel_de_write(dev_priv, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
375 intel_de_write(dev_priv, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
384 intel_de_write(dev_priv, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
[all …]
H A Dintel_dsb.c55 intel_de_write(i915, DSB_CTRL(pipe, id), dsb_ctrl); in intel_dsb_enable_engine()
73 intel_de_write(i915, DSB_CTRL(pipe, id), dsb_ctrl); in intel_dsb_disable_engine()
102 intel_de_write(dev_priv, reg, val); in intel_dsb_indexed_reg_write()
179 intel_de_write(dev_priv, reg, val); in intel_dsb_reg_write()
223 intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id), in intel_dsb_commit()
239 intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id), in intel_dsb_commit()
H A Dintel_dpio_phy.c284 intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
289 intel_de_write(dev_priv, BXT_PORT_TX_DW2_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
300 intel_de_write(dev_priv, BXT_PORT_TX_DW3_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
305 intel_de_write(dev_priv, BXT_PORT_TX_DW4_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
309 intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
382 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, val); in _bxt_ddi_phy_init()
404 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW9(phy), val); in _bxt_ddi_phy_init()
409 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW10(phy), val); in _bxt_ddi_phy_init()
415 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW28(phy), val); in _bxt_ddi_phy_init()
420 intel_de_write(dev_priv, BXT_PORT_CL2CM_DW6(phy), val); in _bxt_ddi_phy_init()
[all …]
H A Dintel_fifo_underrun.c102 intel_de_write(dev_priv, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); in i9xx_check_fifo_underruns()
121 intel_de_write(dev_priv, reg, in i9xx_set_fifo_underrun_reporting()
155 intel_de_write(dev_priv, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); in ivb_check_fifo_underruns()
168 intel_de_write(dev_priv, GEN7_ERR_INT, in ivb_set_fifo_underrun_reporting()
223 intel_de_write(dev_priv, SERR_INT, in cpt_check_pch_fifo_underruns()
239 intel_de_write(dev_priv, SERR_INT, in cpt_set_fifo_underrun_reporting()
H A Dintel_psr.c138 intel_de_write(dev_priv, imr_reg, val); in psr_irq_control()
212 intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder), in intel_psr_irq_handler()
236 intel_de_write(dev_priv, imr_reg, val); in intel_psr_irq_handler()
380 intel_de_write(dev_priv, in hsw_psr_setup_aux()
392 intel_de_write(dev_priv, EDP_PSR_AUX_CTL(dev_priv->psr.transcoder), in hsw_psr_setup_aux()
502 intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder), val); in hsw_activate_psr1()
564 intel_de_write(dev_priv, in hsw_activate_psr2()
568 intel_de_write(dev_priv, in hsw_activate_psr2()
576 intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder), 0); in hsw_activate_psr2()
578 intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder), val); in hsw_activate_psr2()
[all …]
H A Dintel_lvds.c211 intel_de_write(dev_priv, PP_CONTROL(0), val); in intel_lvds_pps_init_hw()
213 intel_de_write(dev_priv, PP_ON_DELAYS(0), in intel_lvds_pps_init_hw()
216 intel_de_write(dev_priv, PP_OFF_DELAYS(0), in intel_lvds_pps_init_hw()
219 intel_de_write(dev_priv, PP_DIVISOR(0), in intel_lvds_pps_init_hw()
299 intel_de_write(dev_priv, lvds_encoder->reg, temp); in intel_pre_enable_lvds()
314 intel_de_write(dev_priv, lvds_encoder->reg, in intel_enable_lvds()
317 intel_de_write(dev_priv, PP_CONTROL(0), in intel_enable_lvds()
336 intel_de_write(dev_priv, PP_CONTROL(0), in intel_disable_lvds()
342 intel_de_write(dev_priv, lvds_encoder->reg, in intel_disable_lvds()
H A Dintel_display.c524 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), in skl_wa_827()
527 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), in skl_wa_827()
537 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), in icl_wa_scalerclkgating()
540 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), in icl_wa_scalerclkgating()
1404 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _vlv_enable_pll()
1426 intel_de_write(dev_priv, DPLL_MD(pipe), in vlv_enable_pll()
1455 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _chv_enable_pll()
1483 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); in chv_enable_pll()
1484 intel_de_write(dev_priv, DPLL_MD(PIPE_B), in chv_enable_pll()
1486 intel_de_write(dev_priv, CBR4_VLV, 0); in chv_enable_pll()
[all …]
H A Dintel_cdclk.c521 intel_de_write(dev_priv, GCI_CONTROL, in vlv_program_pfi_credits()
524 intel_de_write(dev_priv, GCI_CONTROL, in vlv_program_pfi_credits()
753 intel_de_write(dev_priv, LCPLL_CTL, val); in bdw_set_cdclk()
784 intel_de_write(dev_priv, LCPLL_CTL, val); in bdw_set_cdclk()
788 intel_de_write(dev_priv, LCPLL_CTL, val); in bdw_set_cdclk()
797 intel_de_write(dev_priv, CDCLK_FREQ, in bdw_set_cdclk()
984 intel_de_write(dev_priv, DPLL_CTRL1, val); in skl_dpll0_enable()
987 intel_de_write(dev_priv, LCPLL1_CTL, in skl_dpll0_enable()
1001 intel_de_write(dev_priv, LCPLL1_CTL, in skl_dpll0_disable()
1073 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
[all …]
H A Dintel_dvo.c197 intel_de_write(dev_priv, dvo_reg, temp & ~DVO_ENABLE); in intel_disable_dvo()
215 intel_de_write(dev_priv, dvo_reg, temp | DVO_ENABLE); in intel_enable_dvo()
307 intel_de_write(dev_priv, dvo_srcdim_reg, in intel_dvo_pre_enable()
310 intel_de_write(dev_priv, dvo_reg, dvo_val); in intel_dvo_pre_enable()
495 intel_de_write(dev_priv, DPLL(pipe), in intel_dvo_init()
503 intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]); in intel_dvo_init()
H A Dintel_crt.c186 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); in intel_crt_set_dpms()
203 intel_de_write(dev_priv, crt->adpa_reg, adpa); in intel_crt_set_dpms()
470 intel_de_write(dev_priv, crt->adpa_reg, adpa); in ilk_crt_detect_hotplug()
480 intel_de_write(dev_priv, crt->adpa_reg, save_adpa); in ilk_crt_detect_hotplug()
527 intel_de_write(dev_priv, crt->adpa_reg, adpa); in valleyview_crt_detect_hotplug()
533 intel_de_write(dev_priv, crt->adpa_reg, save_adpa); in valleyview_crt_detect_hotplug()
593 intel_de_write(dev_priv, PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); in intel_crt_detect_hotplug()
957 intel_de_write(dev_priv, crt->adpa_reg, adpa); in intel_crt_reset()
1015 intel_de_write(dev_priv, adpa_reg, in intel_crt_init()
1019 intel_de_write(dev_priv, adpa_reg, adpa); in intel_crt_init()
H A Dintel_display_power.c425 intel_de_write(dev_priv, regs->driver, in hsw_power_well_enable()
438 intel_de_write(dev_priv, CNL_AUX_ANAOVRD1(pw_idx), val); in hsw_power_well_enable()
465 intel_de_write(dev_priv, regs->driver, in hsw_power_well_disable()
484 intel_de_write(dev_priv, regs->driver, in icl_combo_phy_aux_power_well_enable()
489 intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy), in icl_combo_phy_aux_power_well_enable()
500 intel_de_write(dev_priv, ICL_AUX_ANAOVRD1(pw_idx), val); in icl_combo_phy_aux_power_well_enable()
516 intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy), in icl_combo_phy_aux_power_well_disable()
520 intel_de_write(dev_priv, regs->driver, in icl_combo_phy_aux_power_well_disable()
610 intel_de_write(dev_priv, DP_AUX_CH_CTL(aux_ch), val); in icl_tc_phy_aux_power_well_enable()
613 intel_de_write(dev_priv, regs->driver, in icl_tc_phy_aux_power_well_enable()
[all …]
H A Dintel_pipe_crc.c191 intel_de_write(dev_priv, PORT_DFT2_G4X, tmp); in vlv_pipe_crc_ctl_reg()
257 intel_de_write(dev_priv, PORT_DFT2_G4X, tmp); in vlv_undo_pipe_scramble_reset()
617 intel_de_write(dev_priv, PIPE_CRC_CTL(crtc->index), val); in intel_crtc_set_crc_source()
652 intel_de_write(dev_priv, PIPE_CRC_CTL(crtc->index), val); in intel_crtc_enable_pipe_crc()
667 intel_de_write(dev_priv, PIPE_CRC_CTL(crtc->index), 0); in intel_crtc_disable_pipe_crc()

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