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Searched refs:input_clk (Results 1 – 20 of 20) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/i2c/
H A Di2c-uniphier.c43 unsigned long input_clk; /* master clock (Hz) */ member
60 priv->input_clk = IOBUS_FREQ; in uniphier_i2c_probe()
184 writel((priv->input_clk / speed / 2 << 16) | (priv->input_clk / speed), in uniphier_i2c_set_bus_speed()
H A Di2c-cdns.c151 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk, in cdns_i2c_calc_divs() argument
159 temp = input_clk / (22 * fscl); in cdns_i2c_calc_divs()
170 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1)); in cdns_i2c_calc_divs()
176 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1)); in cdns_i2c_calc_divs()
/OK3568_Linux_fs/u-boot/drivers/mmc/
H A Drockchip_sdhci.c206 unsigned int input_clk; in rockchip_emmc_set_clock() local
228 input_clk = clk_set_rate(&priv->emmc_clk, clock); in rockchip_emmc_set_clock()
229 if (IS_ERR_VALUE(input_clk)) in rockchip_emmc_set_clock()
230 input_clk = host->max_clk; in rockchip_emmc_set_clock()
239 if ((input_clk / div) <= clock) in rockchip_emmc_set_clock()
251 if (input_clk <= clock) { in rockchip_emmc_set_clock()
257 if ((input_clk / div) <= clock) in rockchip_emmc_set_clock()
266 if ((input_clk / div) <= clock) in rockchip_emmc_set_clock()
H A Ddavinci_mmc.c40 sysclk2 = host->input_clk; in dmmc_set_clock()
/OK3568_Linux_fs/kernel/drivers/i2c/busses/
H A Di2c-cadence.c199 unsigned long input_clk; member
961 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk, in cdns_i2c_calc_divs() argument
969 temp = input_clk / (22 * fscl); in cdns_i2c_calc_divs()
980 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1)); in cdns_i2c_calc_divs()
986 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1)); in cdns_i2c_calc_divs()
1076 unsigned long input_clk = ndata->new_rate; in cdns_i2c_clk_notifier_cb() local
1081 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b); in cdns_i2c_clk_notifier_cb()
1095 id->input_clk = ndata->new_rate; in cdns_i2c_clk_notifier_cb()
1233 id->input_clk = clk_get_rate(id->clk); in cdns_i2c_probe()
1247 ret = cdns_i2c_setclk(id->input_clk, id); in cdns_i2c_probe()
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dsnps,hsdk-pll-clock.txt17 input_clk: input-clk {
27 clocks = <&input_clk>;
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/
H A Dnouveau_led.c60 u32 input_clk = 27e6; /* PDISPLAY.SOR[1].PWM is connected to the crystal */ in nouveau_led_set_brightness() local
64 div = input_clk / freq; in nouveau_led_set_brightness()
/OK3568_Linux_fs/kernel/arch/arc/boot/dts/
H A Dhsdk.dts62 input_clk: input-clk { label
127 clocks = <&input_clk>;
274 clocks = <&input_clk>;
H A Daxc003.dtsi24 input_clk: input-clk { label
34 clocks = <&input_clk>;
H A Daxc003_idu.dtsi24 input_clk: input-clk { label
34 clocks = <&input_clk>;
H A Daxc001.dtsi31 input_clk: input-clk { label
H A Daxs10x_mb.dtsi70 clocks = <&input_clk>;
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega20_hwmgr.c2965 int32_t input_index, input_clk, input_vol, i; in vega20_odn_edit_dpm_table() local
2988 input_clk = input[i + 1]; in vega20_odn_edit_dpm_table()
2996 if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value || in vega20_odn_edit_dpm_table()
2997 input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) { in vega20_odn_edit_dpm_table()
2999 input_clk, in vega20_odn_edit_dpm_table()
3005 if ((input_index == 0 && od_table->GfxclkFmin != input_clk) || in vega20_odn_edit_dpm_table()
3006 (input_index == 1 && od_table->GfxclkFmax != input_clk)) in vega20_odn_edit_dpm_table()
3010 od_table->GfxclkFmin = input_clk; in vega20_odn_edit_dpm_table()
3012 od_table->GfxclkFmax = input_clk; in vega20_odn_edit_dpm_table()
3031 input_clk = input[i + 1]; in vega20_odn_edit_dpm_table()
[all …]
H A Dvega10_hwmgr.c5358 uint32_t input_clk; in vega10_odn_edit_dpm_table() local
5401 input_clk = input[i+1] * 100; in vega10_odn_edit_dpm_table()
5404 if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { in vega10_odn_edit_dpm_table()
5405 dpm_table->dpm_levels[input_level].value = input_clk; in vega10_odn_edit_dpm_table()
5406 podn_vdd_dep_table->entries[input_level].clk = input_clk; in vega10_odn_edit_dpm_table()
H A Dsmu7_hwmgr.c5034 uint32_t input_clk; in smu7_odn_edit_dpm_table() local
5075 input_clk = input[i+1] * 100; in smu7_odn_edit_dpm_table()
5078 if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { in smu7_odn_edit_dpm_table()
5079 podn_dpm_table_in_backend->entries[input_level].clock = input_clk; in smu7_odn_edit_dpm_table()
5080 podn_vdd_dep_in_backend->entries[input_level].clk = input_clk; in smu7_odn_edit_dpm_table()
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-si5341.c73 struct clk *input_clk[SI5341_NUM_INPUTS]; member
1372 m_den = clk_get_rate(data->input_clk[sel]) / 10; in si5341_initialize_pll()
1391 if (!data->input_clk[res]) { in si5341_clk_select_active_input()
1396 if (data->input_clk[i]) { in si5341_clk_select_active_input()
1413 err = clk_prepare_enable(data->input_clk[res]); in si5341_clk_select_active_input()
1452 data->input_clk[i] = input; in si5341_probe()
/OK3568_Linux_fs/u-boot/board/lego/ev3/
H A Dlegoev3.c54 mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID); in board_mmc_init()
/OK3568_Linux_fs/u-boot/arch/arm/mach-davinci/include/mach/
H A Dsdmmc_defs.h150 uint input_clk; /* Input clock to MMC controller */ member
/OK3568_Linux_fs/u-boot/board/davinci/da8xxevm/
H A Domapl138_lcdk.c367 mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID); in board_mmc_init()
H A Dda850evm.c211 mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID); in board_mmc_init()