Searched refs:dtpr2 (Results 1 – 11 of 11) sorted by relevance
29 .dtpr2 = 0x50022A00ul,80 .dtpr2 = 0x50022A00ul,
28 .dtpr2 = 0x5002D200ul,
34 debug_ddr_cfg("dtpr2 0x%08X\n", ptr->dtpr2); in dump_phy_config()336 spd_cb->phy_cfg.dtpr2 = 0 << 31 | 1 << 30 | 0 << 29 | in init_ddr3param()339 spd_cb->phy_cfg.dtpr2 |= (((spd->t_xp > spd->t_xpdll) ? in init_ddr3param()343 spd_cb->phy_cfg.dtpr2 |= (((spd->t_xs > spd->t_xsdll) ? in init_ddr3param()
52 __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET); in ddr3_init_ddrphy()
28 unsigned int dtpr2; member
79 u32 dtpr2; member
184 u32 dtpr2; /* 0x50 dram timing parameters register 2 */ member
173 u32 dtpr2; /* 0x3c dram timing parameters register 2 */ member
137 writel(dram_para.tpr4, &mctl_phy->dtpr2); in mctl_init()
145 (MCTL_TEXSR << 0), &mctl_phy->dtpr2); in mctl_channel_init()
91 dtpr2