1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2015 Google, Inc 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2014 Rockchip Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _ASM_ARCH_RK3288_SDRAM_H__ 10*4882a593Smuzhiyun #define _ASM_ARCH_RK3288_SDRAM_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct rk3288_sdram_channel { 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * bit width in address, eg: 15*4882a593Smuzhiyun * 8 banks using 3 bit to address, 16*4882a593Smuzhiyun * 2 cs using 1 bit to address. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun u8 rank; 19*4882a593Smuzhiyun u8 col; 20*4882a593Smuzhiyun u8 bk; 21*4882a593Smuzhiyun u8 bw; 22*4882a593Smuzhiyun u8 dbw; 23*4882a593Smuzhiyun u8 row_3_4; 24*4882a593Smuzhiyun u8 cs0_row; 25*4882a593Smuzhiyun u8 cs1_row; 26*4882a593Smuzhiyun #if CONFIG_IS_ENABLED(OF_PLATDATA) 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * For of-platdata, which would otherwise convert this into two 29*4882a593Smuzhiyun * byte-swapped integers. With a size of 9 bytes, this struct will 30*4882a593Smuzhiyun * appear in of-platdata as a byte array. 31*4882a593Smuzhiyun * 32*4882a593Smuzhiyun * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff) 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun u8 dummy; 35*4882a593Smuzhiyun #endif 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun struct rk3288_sdram_pctl_timing { 39*4882a593Smuzhiyun u32 togcnt1u; 40*4882a593Smuzhiyun u32 tinit; 41*4882a593Smuzhiyun u32 trsth; 42*4882a593Smuzhiyun u32 togcnt100n; 43*4882a593Smuzhiyun u32 trefi; 44*4882a593Smuzhiyun u32 tmrd; 45*4882a593Smuzhiyun u32 trfc; 46*4882a593Smuzhiyun u32 trp; 47*4882a593Smuzhiyun u32 trtw; 48*4882a593Smuzhiyun u32 tal; 49*4882a593Smuzhiyun u32 tcl; 50*4882a593Smuzhiyun u32 tcwl; 51*4882a593Smuzhiyun u32 tras; 52*4882a593Smuzhiyun u32 trc; 53*4882a593Smuzhiyun u32 trcd; 54*4882a593Smuzhiyun u32 trrd; 55*4882a593Smuzhiyun u32 trtp; 56*4882a593Smuzhiyun u32 twr; 57*4882a593Smuzhiyun u32 twtr; 58*4882a593Smuzhiyun u32 texsr; 59*4882a593Smuzhiyun u32 txp; 60*4882a593Smuzhiyun u32 txpdll; 61*4882a593Smuzhiyun u32 tzqcs; 62*4882a593Smuzhiyun u32 tzqcsi; 63*4882a593Smuzhiyun u32 tdqs; 64*4882a593Smuzhiyun u32 tcksre; 65*4882a593Smuzhiyun u32 tcksrx; 66*4882a593Smuzhiyun u32 tcke; 67*4882a593Smuzhiyun u32 tmod; 68*4882a593Smuzhiyun u32 trstl; 69*4882a593Smuzhiyun u32 tzqcl; 70*4882a593Smuzhiyun u32 tmrr; 71*4882a593Smuzhiyun u32 tckesr; 72*4882a593Smuzhiyun u32 tdpd; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0); 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun struct rk3288_sdram_phy_timing { 77*4882a593Smuzhiyun u32 dtpr0; 78*4882a593Smuzhiyun u32 dtpr1; 79*4882a593Smuzhiyun u32 dtpr2; 80*4882a593Smuzhiyun u32 mr[4]; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun struct rk3288_base_params { 84*4882a593Smuzhiyun u32 noc_timing; 85*4882a593Smuzhiyun u32 noc_activate; 86*4882a593Smuzhiyun u32 ddrconfig; 87*4882a593Smuzhiyun u32 ddr_freq; 88*4882a593Smuzhiyun u32 dramtype; 89*4882a593Smuzhiyun /* 90*4882a593Smuzhiyun * DDR Stride is address mapping for DRAM space 91*4882a593Smuzhiyun * Stride Ch 0 range Ch1 range Total 92*4882a593Smuzhiyun * 0x00 0-256MB 256MB-512MB 512MB 93*4882a593Smuzhiyun * 0x05 0-1GB 0-1GB 1GB 94*4882a593Smuzhiyun * 0x09 0-2GB 0-2GB 2GB 95*4882a593Smuzhiyun * 0x0d 0-4GB 0-4GB 4GB 96*4882a593Smuzhiyun * 0x17 N/A 0-4GB 4GB 97*4882a593Smuzhiyun * 0x1a 0-4GB 4GB-8GB 8GB 98*4882a593Smuzhiyun */ 99*4882a593Smuzhiyun u32 stride; 100*4882a593Smuzhiyun u32 odt; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #endif 104