xref: /OK3568_Linux_fs/u-boot/board/ti/ks2_evm/ddr3_cfg.c (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Keystone2: DDR3 configuration
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * (C) Copyright 2012-2014
5*4882a593Smuzhiyun  *     Texas Instruments Incorporated, <www.ti.com>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * SPDX-License-Identifier:     GPL-2.0+
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <asm/arch/ddr3.h>
13*4882a593Smuzhiyun #include "ddr3_cfg.h"
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun struct ddr3_phy_config ddr3phy_1600_2g = {
16*4882a593Smuzhiyun 	.pllcr          = 0x0001C000ul,
17*4882a593Smuzhiyun 	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
18*4882a593Smuzhiyun 	.pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
19*4882a593Smuzhiyun 	.ptr0           = 0x42C21590ul,
20*4882a593Smuzhiyun 	.ptr1           = 0xD05612C0ul,
21*4882a593Smuzhiyun 	.ptr2           = 0, /* not set in gel */
22*4882a593Smuzhiyun 	.ptr3           = 0x0D861A80ul,
23*4882a593Smuzhiyun 	.ptr4           = 0x0C827100ul,
24*4882a593Smuzhiyun 	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
25*4882a593Smuzhiyun 	.dcr_val        = ((1 << 10)),
26*4882a593Smuzhiyun 	.dtpr0          = 0x9D5CBB66ul,
27*4882a593Smuzhiyun 	.dtpr1          = 0x12868300ul,
28*4882a593Smuzhiyun 	.dtpr2          = 0x5002D200ul,
29*4882a593Smuzhiyun 	.mr0            = 0x00001C70ul,
30*4882a593Smuzhiyun 	.mr1            = 0x00000006ul,
31*4882a593Smuzhiyun 	.mr2            = 0x00000018ul,
32*4882a593Smuzhiyun 	.dtcr           = 0x710035C7ul,
33*4882a593Smuzhiyun 	.pgcr2          = 0x00F07A12ul,
34*4882a593Smuzhiyun 	.zq0cr1         = 0x0001005Dul,
35*4882a593Smuzhiyun 	.zq1cr1         = 0x0001005Bul,
36*4882a593Smuzhiyun 	.zq2cr1         = 0x0001005Bul,
37*4882a593Smuzhiyun 	.pir_v1         = 0x00000033ul,
38*4882a593Smuzhiyun 	.pir_v2         = 0x0000FF81ul,
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun struct ddr3_emif_config ddr3_1600_2g = {
42*4882a593Smuzhiyun 	.sdcfg          = 0x6200CE62ul,
43*4882a593Smuzhiyun 	.sdtim1         = 0x166C9855ul,
44*4882a593Smuzhiyun 	.sdtim2         = 0x00001D4Aul,
45*4882a593Smuzhiyun 	.sdtim3         = 0x435DFF53ul,
46*4882a593Smuzhiyun 	.sdtim4         = 0x543F0CFFul,
47*4882a593Smuzhiyun 	.zqcfg          = 0x70073200ul,
48*4882a593Smuzhiyun 	.sdrfc          = 0x00001869ul,
49*4882a593Smuzhiyun };
50