1 /* 2 * Copyright (c) 2015 Google, Inc 3 * 4 * Copyright 2014 Rockchip Inc. 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #ifndef _ASM_ARCH_RK3288_SDRAM_H__ 10 #define _ASM_ARCH_RK3288_SDRAM_H__ 11 12 struct rk3288_sdram_channel { 13 /* 14 * bit width in address, eg: 15 * 8 banks using 3 bit to address, 16 * 2 cs using 1 bit to address. 17 */ 18 u8 rank; 19 u8 col; 20 u8 bk; 21 u8 bw; 22 u8 dbw; 23 u8 row_3_4; 24 u8 cs0_row; 25 u8 cs1_row; 26 #if CONFIG_IS_ENABLED(OF_PLATDATA) 27 /* 28 * For of-platdata, which would otherwise convert this into two 29 * byte-swapped integers. With a size of 9 bytes, this struct will 30 * appear in of-platdata as a byte array. 31 * 32 * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff) 33 */ 34 u8 dummy; 35 #endif 36 }; 37 38 struct rk3288_sdram_pctl_timing { 39 u32 togcnt1u; 40 u32 tinit; 41 u32 trsth; 42 u32 togcnt100n; 43 u32 trefi; 44 u32 tmrd; 45 u32 trfc; 46 u32 trp; 47 u32 trtw; 48 u32 tal; 49 u32 tcl; 50 u32 tcwl; 51 u32 tras; 52 u32 trc; 53 u32 trcd; 54 u32 trrd; 55 u32 trtp; 56 u32 twr; 57 u32 twtr; 58 u32 texsr; 59 u32 txp; 60 u32 txpdll; 61 u32 tzqcs; 62 u32 tzqcsi; 63 u32 tdqs; 64 u32 tcksre; 65 u32 tcksrx; 66 u32 tcke; 67 u32 tmod; 68 u32 trstl; 69 u32 tzqcl; 70 u32 tmrr; 71 u32 tckesr; 72 u32 tdpd; 73 }; 74 check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0); 75 76 struct rk3288_sdram_phy_timing { 77 u32 dtpr0; 78 u32 dtpr1; 79 u32 dtpr2; 80 u32 mr[4]; 81 }; 82 83 struct rk3288_base_params { 84 u32 noc_timing; 85 u32 noc_activate; 86 u32 ddrconfig; 87 u32 ddr_freq; 88 u32 dramtype; 89 /* 90 * DDR Stride is address mapping for DRAM space 91 * Stride Ch 0 range Ch1 range Total 92 * 0x00 0-256MB 256MB-512MB 512MB 93 * 0x05 0-1GB 0-1GB 1GB 94 * 0x09 0-2GB 0-2GB 2GB 95 * 0x0d 0-4GB 0-4GB 4GB 96 * 0x17 N/A 0-4GB 4GB 97 * 0x1a 0-4GB 4GB-8GB 8GB 98 */ 99 u32 stride; 100 u32 odt; 101 }; 102 103 #endif 104