Searched refs:bus_sw_cap (Results 1 – 11 of 11) sorted by relevance
41 struct bus_sw_cap_t *sw_cap = &phl_com->bus_sw_cap; in phl_ltr_sw_trigger()67 phl_com->bus_sw_cap.ltr_sw_ctrl = enable; in phl_ltr_sw_ctrl()79 phl_com->bus_sw_cap.ltr_hw_ctrl = enable; in phl_ltr_hw_ctrl()85 phl_com->bus_sw_cap.ltr_sw_ctrl = enable; in phl_ltr_sw_ctrl_ntfy()90 return phl_com->bus_sw_cap.ltr_cur_state; in phl_ltr_get_cur_state()95 return phl_com->bus_sw_cap.ltr_last_trigger_time; in phl_ltr_get_last_trigger_time()101 struct bus_sw_cap_t *sw_cap = &phl_com->bus_sw_cap; in phl_ltr_get_tri_cnt()
2651 struct bus_sw_cap_t bus_sw_cap; /* SW controlled bus capability */ member
117 struct bus_sw_cap_t *bus_sw_cap = &phl_info->phl_com->bus_sw_cap; in phl_pcie_trx_mit_watchdog() local118 struct rtw_pcie_trx_mit_info_t *mit_ctl = &bus_sw_cap->mit_ctl; in phl_pcie_trx_mit_watchdog()
2675 struct bus_sw_cap_t bus_sw_cap; /* SW controlled bus capability */ member
1241 …phl_com->bus_sw_cap.l0s_ctrl = (rtw_pci_aspm_enable & BIT1) ? RTW_PCIE_BUS_FUNC_ENABLE : RTW_PCIE_… in rtw_core_update_default_setting()1242 …phl_com->bus_sw_cap.l1_ctrl = (rtw_pci_aspm_enable & BIT2) ? RTW_PCIE_BUS_FUNC_ENABLE : RTW_PCIE_B… in rtw_core_update_default_setting()1243 …phl_com->bus_sw_cap.l1ss_ctrl = (rtw_pci_aspm_enable & BIT3) ? RTW_PCIE_BUS_FUNC_ENABLE : RTW_PCIE… in rtw_core_update_default_setting()1244 phl_com->bus_sw_cap.wake_ctrl = RTW_PCIE_BUS_FUNC_DEFAULT; in rtw_core_update_default_setting()1245 …phl_com->bus_sw_cap.crq_ctrl = (rtw_pci_aspm_enable & BIT0) ? RTW_PCIE_BUS_FUNC_ENABLE : RTW_PCIE_… in rtw_core_update_default_setting()1247 phl_com->bus_sw_cap.l0s_ctrl = RTW_PCIE_BUS_FUNC_DISABLE; in rtw_core_update_default_setting()1248 phl_com->bus_sw_cap.l1_ctrl = RTW_PCIE_BUS_FUNC_DISABLE; in rtw_core_update_default_setting()1249 phl_com->bus_sw_cap.l1ss_ctrl = RTW_PCIE_BUS_FUNC_DISABLE; in rtw_core_update_default_setting()1250 phl_com->bus_sw_cap.wake_ctrl = RTW_PCIE_BUS_FUNC_DEFAULT; in rtw_core_update_default_setting()1251 phl_com->bus_sw_cap.crq_ctrl = RTW_PCIE_BUS_FUNC_DISABLE; in rtw_core_update_default_setting()[all …]
1234 phl_com->bus_sw_cap.l0s_ctrl = RTW_PCIE_BUS_FUNC_DISABLE; in rtw_core_update_default_setting()1235 phl_com->bus_sw_cap.l1_ctrl = RTW_PCIE_BUS_FUNC_DISABLE; in rtw_core_update_default_setting()1236 phl_com->bus_sw_cap.l1ss_ctrl = RTW_PCIE_BUS_FUNC_DISABLE; in rtw_core_update_default_setting()1237 phl_com->bus_sw_cap.wake_ctrl = RTW_PCIE_BUS_FUNC_DEFAULT; in rtw_core_update_default_setting()1238 phl_com->bus_sw_cap.crq_ctrl = RTW_PCIE_BUS_FUNC_DISABLE; in rtw_core_update_default_setting()1240 phl_com->bus_sw_cap.txbd_num = 256; in rtw_core_update_default_setting()1241 phl_com->bus_sw_cap.rxbd_num = 256; in rtw_core_update_default_setting()1242 phl_com->bus_sw_cap.rpbd_num = 0; /* by default */ in rtw_core_update_default_setting()1244 phl_com->bus_sw_cap.rxbuf_num = 1024; in rtw_core_update_default_setting()1246 phl_com->bus_sw_cap.rxbuf_num = 512; in rtw_core_update_default_setting()[all …]
178 (phl_com->bus_sw_cap.ltr_sw_ctrl ? true : false) : false; in rtw_hal_ltr_is_sw_ctrl()187 (phl_com->bus_sw_cap.ltr_hw_ctrl ? true : false) : false; in rtw_hal_ltr_is_hw_ctrl()
22 struct bus_sw_cap_t *bus_sw = &phl_com->bus_sw_cap; in _hal_bus_cap_pre_decision()130 struct bus_sw_cap_t *bus_sw = &phl_com->bus_sw_cap; in _hal_bus_final_cap_decision()
22 struct bus_sw_cap_t *bus_sw = &phl_com->bus_sw_cap; in _hal_bus_cap_pre_decision()129 struct bus_sw_cap_t *bus_sw = &phl_com->bus_sw_cap; in _hal_bus_final_cap_decision()
318 u16 ltr_thre = phl_info->phl_com->bus_sw_cap.ltr_sw_ctrl_thre; in _phl_judge_idle_ltr_switching_conditions()