1
2 /******************************************************************************
3 *
4 * Copyright(c) 2020 Realtek Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 *****************************************************************************/
16 #define _PHL_DM_C_
17 #include "phl_headers.h"
18
rtw_phl_set_edcca_mode(void * phl,enum rtw_edcca_mode mode)19 void rtw_phl_set_edcca_mode(void *phl, enum rtw_edcca_mode mode)
20 {
21 struct phl_info_t *phl_info = (struct phl_info_t *)phl;
22
23 PHL_INFO("[Cert], set phl_com edcca_mode : %d !! \n", mode);
24 phl_info->phl_com->edcca_mode = mode;
25 }
26
rtw_phl_get_edcca_mode(void * phl)27 enum rtw_edcca_mode rtw_phl_get_edcca_mode(void *phl)
28 {
29 struct phl_info_t *phl_info = (struct phl_info_t *)phl;
30
31 return phl_info->phl_com->edcca_mode;
32 }
33
34 #ifdef CONFIG_PCI_HCI
35 #ifdef RTW_WKARD_DYNAMIC_LTR
36 enum rtw_phl_status
phl_ltr_sw_trigger(struct rtw_phl_com_t * phl_com,void * hal,enum rtw_pcie_ltr_state state)37 phl_ltr_sw_trigger(struct rtw_phl_com_t *phl_com, void *hal,
38 enum rtw_pcie_ltr_state state)
39 {
40 enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
41 struct bus_sw_cap_t *sw_cap = &phl_com->bus_sw_cap;
42
43 status = rtw_hal_ltr_sw_trigger(hal, state);
44
45 if (status == RTW_HAL_STATUS_SUCCESS) {
46 sw_cap->ltr_cur_state = state;
47 sw_cap->ltr_last_trigger_time = _os_get_cur_time_us();
48 state == RTW_PCIE_LTR_SW_ACT ?
49 sw_cap->ltr_sw_act_tri_cnt++ : sw_cap->ltr_sw_idle_tri_cnt++;
50 return RTW_PHL_STATUS_SUCCESS;
51 } else {
52 return RTW_PHL_STATUS_FAILURE;
53 }
54 }
55
56 /* Switching sw ctrl will trigger active ltr at the same time
57 to prevent inconsistent state */
58 /* usage : echo phl ltr set [enable/disable] */
59 enum rtw_phl_status
phl_ltr_sw_ctrl(struct rtw_phl_com_t * phl_com,void * hal,bool enable)60 phl_ltr_sw_ctrl(struct rtw_phl_com_t *phl_com, void *hal, bool enable)
61 {
62 enum rtw_hal_status status = RTW_HAL_STATUS_FAILURE;
63
64 status = phl_ltr_sw_trigger(phl_com, hal, RTW_PCIE_LTR_SW_ACT);
65
66 if (status == RTW_HAL_STATUS_SUCCESS) {
67 phl_com->bus_sw_cap.ltr_sw_ctrl = enable;
68 return RTW_PHL_STATUS_SUCCESS;
69 } else {
70 return RTW_PHL_STATUS_FAILURE;
71 }
72 }
73
74 /* switch to hw control. it's valid that only hw supports hw mode */
75 /* usage : echo phl ltr set [enable/disable] */
76 void
phl_ltr_hw_ctrl(struct rtw_phl_com_t * phl_com,bool enable)77 phl_ltr_hw_ctrl(struct rtw_phl_com_t *phl_com, bool enable)
78 {
79 phl_com->bus_sw_cap.ltr_hw_ctrl = enable;
80 }
81
82 /* For pm module, this will not trigger active ltr since halmac will take care of*/
phl_ltr_sw_ctrl_ntfy(struct rtw_phl_com_t * phl_com,bool enable)83 void phl_ltr_sw_ctrl_ntfy(struct rtw_phl_com_t *phl_com, bool enable)
84 {
85 phl_com->bus_sw_cap.ltr_sw_ctrl = enable;
86 }
87
phl_ltr_get_cur_state(struct rtw_phl_com_t * phl_com)88 u8 phl_ltr_get_cur_state(struct rtw_phl_com_t *phl_com)
89 {
90 return phl_com->bus_sw_cap.ltr_cur_state;
91 }
92
phl_ltr_get_last_trigger_time(struct rtw_phl_com_t * phl_com)93 u32 phl_ltr_get_last_trigger_time(struct rtw_phl_com_t *phl_com)
94 {
95 return phl_com->bus_sw_cap.ltr_last_trigger_time;
96 }
97
phl_ltr_get_tri_cnt(struct rtw_phl_com_t * phl_com,enum rtw_pcie_ltr_state state)98 u32 phl_ltr_get_tri_cnt(struct rtw_phl_com_t *phl_com,
99 enum rtw_pcie_ltr_state state)
100 {
101 struct bus_sw_cap_t *sw_cap = &phl_com->bus_sw_cap;
102
103 return state == RTW_PCIE_LTR_SW_ACT ?
104 sw_cap->ltr_sw_act_tri_cnt : sw_cap->ltr_sw_idle_tri_cnt;
105 }
106
107 #define TP_MBPS 100
phl_ltr_ctrl_watchdog(struct phl_info_t * phl_info)108 void phl_ltr_ctrl_watchdog(struct phl_info_t *phl_info)
109 {
110 struct rtw_phl_com_t *phl_com = phl_info->phl_com;
111 struct rtw_stats *sts = &phl_com->phl_stats;
112 u32 tx_tp_m = 0, rx_tp_m = 0;
113 static bool start = false;
114
115 /* only valid if it's currenlty running hw mode */
116 if (!rtw_hal_ltr_is_hw_ctrl(phl_com, phl_info->hal))
117 return;
118
119 tx_tp_m = sts->tx_tp_kbits >> 10;
120 rx_tp_m = sts->rx_tp_kbits >> 10;
121
122 /* PHL_INFO("%s tx_tp_m = %u /rx_tp_m = %u \n", __func__, tx_tp_m, rx_tp_m);*/
123
124 if ((tx_tp_m > TP_MBPS || rx_tp_m > TP_MBPS) && !start) {
125 start = true;
126 rtw_hal_ltr_en_hw_mode(phl_info->hal, false);
127 rtw_hal_ltr_sw_trigger(phl_info->hal, RTW_PCIE_LTR_SW_ACT);
128 }
129
130 if (start && tx_tp_m < TP_MBPS && rx_tp_m < TP_MBPS) {
131 start = false;
132 rtw_hal_ltr_en_hw_mode(phl_info->hal, true);
133 }
134 }
135 #endif /* RTW_WKARD_DYNAMIC_LTR */
136 #endif /* CONFIG_PCI_HCI */