1 /******************************************************************************
2 *
3 * Copyright(c) 2019 - 2021 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #include "hal_headers.h"
16
_hal_bus_cap_pre_decision(struct rtw_phl_com_t * phl_com,void * hal)17 static void _hal_bus_cap_pre_decision(struct rtw_phl_com_t *phl_com,
18 void *hal)
19 {
20 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
21 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
22 struct bus_sw_cap_t *bus_sw = &phl_com->bus_sw_cap;
23 struct bus_hw_cap_t *bus_hw = &hal_com->bus_hw_cap;
24 struct bus_cap_t *bus_cap = &hal_com->bus_cap;
25
26 #ifdef CONFIG_PCI_HCI
27 bus_cap->l0s_ctrl = bus_sw->l0s_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
28 bus_hw->l0s_ctrl : bus_sw->l0s_ctrl;
29 bus_cap->l1_ctrl = bus_sw->l1_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
30 bus_hw->l1_ctrl : bus_sw->l1_ctrl;
31 bus_cap->l1ss_ctrl = bus_sw->l1ss_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
32 bus_hw->l1ss_ctrl : bus_sw->l1ss_ctrl;
33 bus_cap->wake_ctrl = bus_sw->wake_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
34 bus_hw->wake_ctrl : bus_sw->wake_ctrl;
35 bus_cap->crq_ctrl = bus_sw->crq_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
36 bus_hw->crq_ctrl : bus_sw->crq_ctrl;
37
38
39 bus_cap->l0sdly_ctrl = bus_sw->l0sdly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ?
40 bus_hw->l0sdly_ctrl : bus_sw->l0sdly_ctrl;
41 bus_cap->l1dly_ctrl = bus_sw->l1dly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ?
42 bus_hw->l1dly_ctrl : bus_sw->l1dly_ctrl;
43 bus_cap->clkdly_ctrl = bus_sw->clkdly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ?
44 bus_hw->clkdly_ctrl : bus_sw->clkdly_ctrl;
45
46
47 bus_cap->txbd_num = (bus_sw->txbd_num) ?
48 ((bus_sw->txbd_num > bus_hw->max_txbd_num) ?
49 bus_hw->max_txbd_num : bus_sw->txbd_num) :
50 bus_hw->max_txbd_num;
51 bus_cap->read_txbd_th = bus_cap->txbd_num >> bus_sw->read_txbd_lvl;
52
53 bus_cap->rxbd_num = (bus_sw->rxbd_num) ?
54 ((bus_sw->rxbd_num > bus_hw->max_rxbd_num) ?
55 bus_hw->max_rxbd_num : bus_sw->rxbd_num) :
56 bus_hw->max_rxbd_num;
57 bus_cap->rpbd_num = (bus_sw->rpbd_num) ?
58 ((bus_sw->rpbd_num > bus_hw->max_rpbd_num) ?
59 bus_hw->max_rpbd_num : bus_sw->rpbd_num) :
60 bus_hw->max_rpbd_num;
61
62 /* rx buffer number must be larger or equal to rx bd number */
63 bus_cap->rxbuf_num = (bus_sw->rxbuf_num < bus_cap->rxbd_num) ?
64 bus_cap->rxbd_num : bus_sw->rxbuf_num;
65 bus_cap->rpbuf_num = (bus_sw->rpbuf_num < bus_cap->rpbd_num) ?
66 bus_cap->rpbd_num : bus_sw->rpbuf_num;
67
68 bus_cap->ltr_act.ctrl = bus_sw->ltr_act.ctrl;
69 bus_cap->ltr_act.val = bus_sw->ltr_act.val;
70 bus_cap->ltr_idle.ctrl = bus_sw->ltr_idle.ctrl;
71 bus_cap->ltr_idle.val = bus_sw->ltr_idle.val;
72 bus_cap->ltr_init_state = bus_sw->ltr_init_state;
73 bus_cap->ltr_sw_ctrl = bus_hw->ltr_sw_ctrl ?
74 (bus_sw->ltr_sw_ctrl ? true : false) : false;
75 bus_cap->ltr_hw_ctrl = bus_hw->ltr_hw_ctrl ?
76 (bus_sw->ltr_hw_ctrl ? true : false) : false;
77 #elif defined (CONFIG_USB_HCI)
78 bus_cap->tx_buf_size = (bus_sw->tx_buf_size) ?
79 ((bus_sw->tx_buf_size < bus_hw->tx_buf_size) ?
80 bus_sw->tx_buf_size : bus_hw->tx_buf_size) :
81 bus_hw->tx_buf_size;
82 bus_cap->tx_buf_num = (bus_sw->tx_buf_num) ?
83 ((bus_sw->tx_buf_num < bus_hw->tx_buf_num) ?
84 bus_sw->tx_buf_num : bus_hw->tx_buf_num) :
85 bus_hw->tx_buf_num;
86 bus_cap->tx_mgnt_buf_size = (bus_sw->tx_mgnt_buf_size) ?
87 ((bus_sw->tx_mgnt_buf_size < bus_hw->tx_mgnt_buf_size) ?
88 bus_sw->tx_mgnt_buf_size : bus_hw->tx_mgnt_buf_size) :
89 bus_hw->tx_mgnt_buf_size;
90 bus_cap->tx_mgnt_buf_num = (bus_sw->tx_mgnt_buf_num) ?
91 ((bus_sw->tx_mgnt_buf_num < bus_hw->tx_mgnt_buf_num) ?
92 bus_sw->tx_mgnt_buf_num : bus_hw->tx_mgnt_buf_num) :
93 bus_hw->tx_mgnt_buf_num;
94 bus_cap->tx_h2c_buf_num = (bus_sw->tx_h2c_buf_num) ?
95 ((bus_sw->tx_h2c_buf_num < bus_hw->tx_h2c_buf_num) ?
96 bus_sw->tx_h2c_buf_num : bus_hw->tx_h2c_buf_num) :
97 bus_hw->tx_h2c_buf_num;
98 bus_cap->rx_buf_size = (bus_sw->rx_buf_size) ?
99 ((bus_sw->rx_buf_size < bus_hw->rx_buf_size) ?
100 bus_sw->rx_buf_size : bus_hw->rx_buf_size) :
101 bus_hw->rx_buf_size;
102 bus_cap->rx_buf_num = (bus_sw->rx_buf_num) ?
103 ((bus_sw->rx_buf_num < bus_hw->rx_buf_num) ?
104 bus_sw->rx_buf_num : bus_hw->rx_buf_num) :
105 bus_hw->rx_buf_num;
106 bus_cap->in_token_num = (bus_sw->in_token_num) ?
107 ((bus_sw->in_token_num < bus_hw->in_token_num) ?
108 bus_sw->in_token_num : bus_hw->in_token_num) :
109 bus_hw->in_token_num;
110 #elif defined(CONFIG_SDIO_HCI)
111 bus_cap->tx_buf_size = bus_sw->tx_buf_size ?
112 bus_sw->tx_buf_size : bus_hw->tx_buf_size;
113 bus_cap->tx_buf_num = bus_sw->tx_buf_num ?
114 bus_sw->tx_buf_num : bus_hw->tx_buf_num;
115 bus_cap->tx_mgnt_buf_size = bus_sw->tx_mgnt_buf_size ?
116 bus_sw->tx_mgnt_buf_size : bus_hw->tx_mgnt_buf_size;
117 bus_cap->tx_mgnt_buf_num = bus_sw->tx_mgnt_buf_num ?
118 bus_sw->tx_mgnt_buf_num : bus_hw->tx_mgnt_buf_num;
119 bus_cap->rx_buf_size = bus_sw->rx_buf_size ?
120 bus_sw->rx_buf_size : bus_hw->rx_buf_size;
121 bus_cap->rx_buf_num = bus_sw->rx_buf_num ?
122 bus_sw->rx_buf_num : bus_hw->rx_buf_num;
123 #endif
124 }
125
126 #ifdef CONFIG_PCI_HCI
_hal_bus_final_cap_decision(struct rtw_phl_com_t * phl_com,struct rtw_hal_com_t * hal_com)127 static void _hal_bus_final_cap_decision(struct rtw_phl_com_t *phl_com,
128 struct rtw_hal_com_t *hal_com)
129 {
130 struct bus_sw_cap_t *bus_sw = &phl_com->bus_sw_cap;
131 struct bus_hw_cap_t *bus_hw = &hal_com->bus_hw_cap;
132 struct bus_cap_t *bus_cap = &hal_com->bus_cap;
133
134 bus_cap->l0s_ctrl = bus_sw->l0s_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
135 bus_hw->l0s_ctrl : bus_sw->l0s_ctrl;
136 bus_cap->l1_ctrl = bus_sw->l1_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
137 bus_hw->l1_ctrl : bus_sw->l1_ctrl;
138 bus_cap->l1ss_ctrl = bus_sw->l1ss_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
139 bus_hw->l1ss_ctrl : bus_sw->l1ss_ctrl;
140 bus_cap->wake_ctrl = bus_sw->wake_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
141 bus_hw->wake_ctrl : bus_sw->wake_ctrl;
142 bus_cap->crq_ctrl = bus_sw->crq_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
143 bus_hw->crq_ctrl : bus_sw->crq_ctrl;
144
145 bus_cap->l0sdly_ctrl = bus_sw->l0sdly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ?
146 bus_hw->l0sdly_ctrl : bus_sw->l0sdly_ctrl;
147 bus_cap->l1dly_ctrl = bus_sw->l1dly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ?
148 bus_hw->l1dly_ctrl : bus_sw->l1dly_ctrl;
149 bus_cap->clkdly_ctrl = bus_sw->clkdly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ?
150 bus_hw->clkdly_ctrl : bus_sw->clkdly_ctrl;
151
152
153 bus_cap->txbd_num = (bus_sw->txbd_num) ?
154 ((bus_sw->txbd_num > bus_hw->max_txbd_num) ?
155 bus_hw->max_txbd_num : bus_sw->txbd_num) :
156 bus_hw->max_txbd_num;
157 bus_cap->read_txbd_th = bus_cap->txbd_num >> bus_sw->read_txbd_lvl;
158
159 bus_cap->rxbd_num = (bus_sw->rxbd_num) ?
160 ((bus_sw->rxbd_num > bus_hw->max_rxbd_num) ?
161 bus_hw->max_rxbd_num : bus_sw->rxbd_num) :
162 bus_hw->max_rxbd_num;
163 bus_cap->rpbd_num = (bus_sw->rpbd_num) ?
164 ((bus_sw->rpbd_num > bus_hw->max_rpbd_num) ?
165 bus_hw->max_rpbd_num : bus_sw->rpbd_num) :
166 bus_hw->max_rpbd_num;
167
168 bus_cap->ltr_act.ctrl = bus_sw->ltr_act.ctrl;
169 bus_cap->ltr_act.val = bus_sw->ltr_act.val;
170 bus_cap->ltr_idle.ctrl = bus_sw->ltr_idle.ctrl;
171 bus_cap->ltr_idle.val = bus_sw->ltr_idle.val;
172 bus_cap->ltr_init_state = bus_sw->ltr_init_state;
173 bus_cap->ltr_sw_ctrl = bus_hw->ltr_sw_ctrl ?
174 (bus_sw->ltr_sw_ctrl ? true : false) : false;
175 bus_cap->ltr_hw_ctrl = bus_hw->ltr_hw_ctrl ?
176 (bus_sw->ltr_hw_ctrl ? true : false) : false;
177
178 #ifdef RTW_WKARD_GET_PROCESSOR_ID
179 bus_cap->proc_id = bus_sw->proc_id;
180 #endif
181 }
182 #endif
183
_hal_ps_final_cap_decision(struct rtw_phl_com_t * phl_com,struct rtw_hal_com_t * hal_com)184 static void _hal_ps_final_cap_decision(struct rtw_phl_com_t *phl_com,
185 struct rtw_hal_com_t *hal_com)
186 {
187 struct rtw_ps_cap_t *ps_cap = &phl_com->dev_cap.ps_cap;
188 struct rtw_ps_cap_t *ps_sw_cap = &phl_com->dev_sw_cap.ps_cap;
189 struct rtw_ps_cap_t *ps_hw_cap = &hal_com->dev_hw_cap.ps_cap;
190
191 /* sw */
192 ps_cap->init_rf_state = ps_sw_cap->init_rf_state;
193 ps_cap->init_rt_stop_rson = ps_sw_cap->init_rt_stop_rson;
194 ps_cap->leave_fail_act = ps_sw_cap->leave_fail_act;
195 ps_cap->ips_en = ps_sw_cap->ips_en;
196 ps_cap->ips_wow_en = ps_sw_cap->ips_wow_en;
197 ps_cap->lps_en = ps_sw_cap->lps_en;
198 ps_cap->lps_awake_interval = ps_sw_cap->lps_awake_interval;
199 ps_cap->lps_listen_bcn_mode = ps_sw_cap->lps_listen_bcn_mode;
200 ps_cap->lps_smart_ps_mode = ps_sw_cap->lps_smart_ps_mode;
201 ps_cap->lps_rssi_enter_threshold = ps_sw_cap->lps_rssi_enter_threshold;
202 ps_cap->lps_rssi_leave_threshold = ps_sw_cap->lps_rssi_leave_threshold;
203 ps_cap->lps_rssi_diff_threshold = ps_sw_cap->lps_rssi_diff_threshold;
204 ps_cap->lps_wow_en = ps_sw_cap->lps_wow_en;
205 ps_cap->lps_wow_awake_interval = ps_sw_cap->lps_wow_awake_interval;
206 ps_cap->lps_wow_listen_bcn_mode = ps_sw_cap->lps_wow_listen_bcn_mode;
207 ps_cap->lps_wow_smart_ps_mode = ps_sw_cap->lps_wow_smart_ps_mode;
208 /* hw */
209 ps_cap->lps_pause_tx = ps_hw_cap->lps_pause_tx;
210 /* sw & hw */
211 ps_cap->ips_cap = (ps_sw_cap->ips_cap & ps_hw_cap->ips_cap);
212 ps_cap->ips_wow_cap = (ps_sw_cap->ips_wow_cap & ps_hw_cap->ips_wow_cap);
213 ps_cap->lps_cap = (ps_sw_cap->lps_cap & ps_hw_cap->lps_cap);
214 ps_cap->lps_wow_cap = (ps_sw_cap->lps_wow_cap & ps_hw_cap->lps_wow_cap);
215 }
216
_hal_edcca_final_cap_decision(struct rtw_phl_com_t * phl_com,struct rtw_hal_com_t * hal_com)217 static void _hal_edcca_final_cap_decision(struct rtw_phl_com_t *phl_com,
218 struct rtw_hal_com_t *hal_com)
219 {
220 struct rtw_edcca_cap_t *edcca_cap = &phl_com->dev_cap.edcca_cap;
221 struct rtw_edcca_cap_t *edcca_sw_cap = &phl_com->dev_sw_cap.edcca_cap;
222 struct rtw_edcca_cap_t *edcca_hw_cap = &hal_com->dev_hw_cap.edcca_cap;
223
224 edcca_cap->edcca_adap_th_2g = (edcca_sw_cap->edcca_adap_th_2g)?
225 (edcca_sw_cap->edcca_adap_th_2g):
226 (edcca_hw_cap->edcca_adap_th_2g);
227 edcca_cap->edcca_adap_th_5g = (edcca_sw_cap->edcca_adap_th_5g)?
228 (edcca_sw_cap->edcca_adap_th_5g):
229 (edcca_hw_cap->edcca_adap_th_5g);
230
231 edcca_cap->edcca_carrier_sense_th = (edcca_sw_cap->edcca_carrier_sense_th)?
232 (edcca_sw_cap->edcca_carrier_sense_th):
233 (edcca_hw_cap->edcca_carrier_sense_th);
234 }
235
rtw_hal_fw_cap_pre_config(struct rtw_phl_com_t * phl_com,void * hal)236 void rtw_hal_fw_cap_pre_config(struct rtw_phl_com_t *phl_com, void *hal)
237 {
238
239 struct dev_cap_t *dev_cap = &phl_com->dev_cap;
240 struct dev_cap_t *dev_sw_cap = &phl_com->dev_sw_cap;
241
242 /* leaving for fw hw cap
243 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
244 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
245 struct dev_cap_t *dev_hw_cap = &hal_com->dev_hw_cap;
246 */
247
248 dev_cap->fw_cap.fw_src = dev_sw_cap->fw_cap.fw_src;
249 dev_cap->fw_cap.dlram_en = dev_sw_cap->fw_cap.dlram_en;
250 dev_cap->fw_cap.dlrom_en = dev_sw_cap->fw_cap.dlrom_en;
251 }
252
rtw_hal_bus_cap_pre_config(struct rtw_phl_com_t * phl_com,void * hal)253 void rtw_hal_bus_cap_pre_config(struct rtw_phl_com_t *phl_com, void *hal)
254 {
255 _hal_bus_cap_pre_decision(phl_com, hal);
256 }
257
258
259
rtw_hal_fw_final_cap_config(struct rtw_phl_com_t * phl_com,void * hal)260 void rtw_hal_fw_final_cap_config(struct rtw_phl_com_t *phl_com, void *hal)
261 {
262
263 struct dev_cap_t *dev_cap = &phl_com->dev_cap;
264 struct dev_cap_t *dev_sw_cap = &phl_com->dev_sw_cap;
265
266 /* leaving for fw hw cap
267 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
268 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
269 struct dev_cap_t *dev_hw_cap = &hal_com->dev_hw_cap;
270 */
271
272 dev_cap->fw_cap.fw_src = dev_sw_cap->fw_cap.fw_src;
273 dev_cap->fw_cap.dlram_en = dev_sw_cap->fw_cap.dlram_en;
274 dev_cap->fw_cap.dlrom_en = dev_sw_cap->fw_cap.dlrom_en;
275 }
276
rtw_hal_final_cap_decision(struct rtw_phl_com_t * phl_com,void * hal)277 void rtw_hal_final_cap_decision(struct rtw_phl_com_t *phl_com, void *hal)
278 {
279 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
280 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
281 struct phy_hw_cap_t *phy_hw = hal_com->phy_hw_cap;
282 struct phy_sw_cap_t *phy_sw = phl_com->phy_sw_cap;
283 struct phy_cap_t *phy_cap = phl_com->phy_cap;
284
285 struct dev_cap_t *dev_cap = &phl_com->dev_cap;
286 struct dev_cap_t *dev_sw_cap = &phl_com->dev_sw_cap;
287 struct dev_cap_t *dev_hw_cap = &hal_com->dev_hw_cap;
288
289 #ifdef RTW_WKARD_PHY_CAP
290 phy_cap[0].proto_sup = phy_sw[0].proto_sup;
291 phy_cap[1].proto_sup = phy_sw[1].proto_sup;
292 phy_cap[0].band_sup = phy_sw[0].band_sup;
293 phy_cap[1].band_sup = phy_sw[1].band_sup;
294 phy_cap[0].bw_sup = phy_sw[0].bw_sup;
295 phy_cap[1].bw_sup = phy_sw[1].bw_sup;
296
297 phy_cap[0].txss = (phy_sw[0].txss)?((phy_sw[0].txss > phy_hw[0].tx_num)?
298 phy_hw[0].tx_num:phy_sw[0].txss):phy_hw[0].tx_num;
299 phy_cap[0].rxss = (phy_sw[0].rxss)?((phy_sw[0].rxss > phy_hw[0].rx_num)?
300 phy_hw[0].rx_num:phy_sw[0].rxss):phy_hw[0].rx_num;
301 phy_cap[1].txss = (phy_sw[1].txss)?((phy_sw[1].txss > phy_hw[1].tx_num)?
302 phy_hw[1].tx_num:phy_sw[1].txss):phy_hw[1].tx_num;
303 phy_cap[1].rxss = (phy_sw[1].rxss)?((phy_sw[1].rxss > phy_hw[1].rx_num)?
304 phy_hw[1].rx_num:phy_sw[1].rxss):phy_hw[1].rx_num;
305 phy_cap[0].hw_rts_time_th = (phy_sw[0].hw_rts_time_th)?
306 phy_sw[0].hw_rts_time_th:phy_hw[0].hw_rts_time_th;
307 phy_cap[1].hw_rts_time_th = (phy_sw[1].hw_rts_time_th)?
308 phy_sw[1].hw_rts_time_th:phy_hw[1].hw_rts_time_th;
309 phy_cap[0].hw_rts_len_th = (phy_sw[0].hw_rts_len_th)?
310 phy_sw[0].hw_rts_len_th:phy_hw[0].hw_rts_len_th;
311 phy_cap[1].hw_rts_len_th = (phy_sw[1].hw_rts_len_th)?
312 phy_sw[1].hw_rts_len_th:phy_hw[1].hw_rts_len_th;
313 /* fw */
314 rtw_hal_fw_final_cap_config(phl_com,hal);
315 #endif
316
317 #ifdef RTW_WKARD_LAMODE
318 if (dev_sw_cap->la_mode && dev_hw_cap->la_mode)
319 dev_cap->la_mode = true;
320 #endif
321
322 /* wow, to be refined along with hw cap */
323 dev_cap->wow_cap.magic_sup = dev_sw_cap->wow_cap.magic_sup;
324 dev_cap->wow_cap.pattern_sup = dev_sw_cap->wow_cap.pattern_sup;
325 dev_cap->wow_cap.arp_ofld_sup = dev_sw_cap->wow_cap.arp_ofld_sup;
326 dev_cap->wow_cap.ns_oflod_sup = dev_sw_cap->wow_cap.ns_oflod_sup;
327 dev_cap->wow_cap.gtk_ofld_sup = dev_sw_cap->wow_cap.gtk_ofld_sup;
328 dev_cap->wow_cap.ping_pattern_wake_sup = dev_sw_cap->wow_cap.ping_pattern_wake_sup;
329 dev_cap->wow_cap.nlo_sup = dev_sw_cap->wow_cap.nlo_sup;
330
331 if (dev_sw_cap->pkg_type != 0xFF)
332 dev_cap->pkg_type = dev_sw_cap->pkg_type;
333 else
334 dev_cap->pkg_type = dev_hw_cap->pkg_type;
335
336 if (dev_sw_cap->rfe_type != 0xFF)
337 dev_cap->rfe_type = dev_sw_cap->rfe_type;
338 else
339 dev_cap->rfe_type = dev_hw_cap->rfe_type;
340
341 dev_cap->bypass_rfe_chk = dev_sw_cap->bypass_rfe_chk;
342
343 hal_com->dbcc_en = false;/*init default value*/
344 #ifdef CONFIG_DBCC_SUPPORT
345 if (dev_sw_cap->dbcc_sup && dev_hw_cap->dbcc_sup)
346 dev_cap->dbcc_sup = true;
347 /*TODO - update dbcc_en from sw & hw cap
348 if (dev_cap->dbcc_sup && dft->dbcc_en)
349 hal_com->dbcc_en = true;
350 */
351 #endif
352
353 #ifdef CONFIG_MCC_SUPPORT
354 if (dev_sw_cap->mcc_sup && dev_hw_cap->mcc_sup)
355 dev_cap->mcc_sup = true;
356 #endif /*CONFIG_MCC_SUPPORT*/
357
358 #ifdef CONFIG_PHL_TWT
359 dev_cap->twt_sup = (dev_sw_cap->twt_sup & dev_hw_cap->twt_sup);
360 #endif /*CONFIG_PHL_TWT*/
361
362 if (dev_sw_cap->hw_hdr_conv && dev_hw_cap->hw_hdr_conv)
363 dev_cap->hw_hdr_conv = true;
364 if (dev_sw_cap->tx_mu_ru && dev_hw_cap->tx_mu_ru)
365 dev_cap->tx_mu_ru = true;
366
367 dev_cap->xcap = dev_hw_cap->xcap;
368 dev_cap->domain = dev_hw_cap->domain;
369 dev_cap->btc_mode = dev_sw_cap->btc_mode;
370
371 #ifdef CONFIG_PCI_HCI
372 _hal_bus_final_cap_decision(phl_com, hal_com);
373 #endif
374
375 if (dev_sw_cap->pwrbyrate_off != 0xFF)
376 dev_cap->pwrbyrate_off = dev_sw_cap->pwrbyrate_off;
377 else
378 dev_cap->pwrbyrate_off = PW_BY_RATE_ON;
379
380 if (dev_sw_cap->pwrlmt_type != 0xFF)
381 dev_cap->pwrlmt_type = dev_sw_cap->pwrlmt_type;
382 else
383 dev_cap->pwrlmt_type = PWLMT_BY_EFUSE;
384
385 if (dev_sw_cap->rf_board_opt != 0xFF)
386 dev_cap->rf_board_opt = dev_sw_cap->rf_board_opt;
387 else
388 dev_cap->rf_board_opt = dev_hw_cap->rf_board_opt;
389
390 if (RTW_HW_CAP_ULRU_AUTO == dev_sw_cap->sta_ulru) {
391 /* auto : use hw default setting */
392 dev_cap->sta_ulru = dev_hw_cap->sta_ulru;
393 } else {
394 /* forced use sw settings */
395 dev_cap->sta_ulru = dev_sw_cap->sta_ulru;
396 }
397 PHL_INFO("sta_ulru final : 0x%x ; sw 0x%x ; hw 0x%x\n",
398 dev_cap->sta_ulru, dev_sw_cap->sta_ulru, dev_hw_cap->sta_ulru);
399
400 #ifdef RTW_WKARD_BB_DISABLE_STA_2G40M_ULOFDMA
401 /* 2.4G 40MHz UL OFDAM : bb ask to disable */
402 if (RTW_HW_CAP_ULRU_AUTO == dev_sw_cap->sta_ulru_2g40mhz) {
403 /* auto : use hw default setting */
404 dev_cap->sta_ulru_2g40mhz = dev_hw_cap->sta_ulru_2g40mhz;
405 } else {
406 /* forced use sw settings */
407 dev_cap->sta_ulru_2g40mhz = dev_sw_cap->sta_ulru_2g40mhz;
408 }
409 PHL_INFO("sta_ulru_2g40mhz final : 0x%x ; sw 0x%x ; hw 0x%x\n",
410 dev_cap->sta_ulru_2g40mhz, dev_sw_cap->sta_ulru_2g40mhz, dev_hw_cap->sta_ulru_2g40mhz);
411 #endif
412
413 _hal_ps_final_cap_decision(phl_com, hal_com);
414
415 _hal_edcca_final_cap_decision(phl_com, hal_com);
416
417 if (dev_hw_cap->hw_stype_cap != EFUSE_HW_STYPE_GENERAL)
418 dev_cap->hw_stype_cap = dev_hw_cap->hw_stype_cap;
419 else
420 dev_cap->hw_stype_cap = EFUSE_HW_STYPE_NONE;
421
422 if (dev_hw_cap->wl_func_cap != EFUSE_WL_FUNC_GENERAL)
423 dev_cap->wl_func_cap = dev_hw_cap->wl_func_cap;
424 else
425 dev_cap->wl_func_cap = EFUSE_WL_FUNC_NONE;
426
427 dev_cap->rpq_agg_num = dev_sw_cap->rpq_agg_num ?
428 dev_sw_cap->rpq_agg_num : dev_hw_cap->rpq_agg_num;
429
430 /* MAC_AX_QTA_SCC_TURBO, decide by sw, need to be refined after we have hw cap */
431 dev_cap->quota_turbo = dev_sw_cap->quota_turbo;
432 }
433
434 /**
435 * rtw_hal_get_bf_proto_cap
436 * input:
437 * @phl: (struct phl_info_t *phl_info)
438 * @band:
439 * input_output:
440 * @proto_cap: (struct protocol_cap_t *proto_cap) the variable to save the bf_cap result.
441 * return:
442 * @rtw_hal_status:
443 */
444 enum rtw_hal_status
rtw_hal_get_bf_proto_cap(struct rtw_phl_com_t * phl_com,void * hal,u8 band,struct protocol_cap_t * proto_cap)445 rtw_hal_get_bf_proto_cap(struct rtw_phl_com_t *phl_com, void *hal,
446 u8 band, struct protocol_cap_t *proto_cap)
447 {
448 #ifdef RTW_WKARD_PHY_CAP
449 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
450 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
451 struct protocol_cap_t *hw_cap = NULL;
452 struct protocol_cap_t *sw_cap = NULL;
453
454 if (band >= HW_BAND_MAX) {
455 PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "rtw_hal_get_bf_proto_cap : invalid band index \n");
456 return RTW_HAL_STATUS_FAILURE;
457 }
458 if (proto_cap == NULL) {
459 PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "rtw_hal_get_bf_proto_cap : input proto_cap is NULL \n");
460 return RTW_HAL_STATUS_FAILURE;
461 }
462
463
464 hw_cap = &hal_com->proto_hw_cap[band];
465 sw_cap = &phl_com->proto_sw_cap[band];
466
467 proto_cap->he_su_bfmr =
468 (sw_cap->he_su_bfmr && hw_cap->he_su_bfmr) ? 1 : 0;
469 proto_cap->he_su_bfme =
470 (sw_cap->he_su_bfme && hw_cap->he_su_bfme) ? 1 : 0;
471 proto_cap->he_mu_bfmr =
472 (sw_cap->he_mu_bfmr && hw_cap->he_mu_bfmr) ? 1 : 0;
473 proto_cap->he_mu_bfme =
474 (sw_cap->he_mu_bfme && hw_cap->he_mu_bfme) ? 1 : 0;
475 proto_cap->non_trig_cqi_fb =
476 (sw_cap->non_trig_cqi_fb && hw_cap->non_trig_cqi_fb) ? 1 : 0;
477 proto_cap->trig_cqi_fb =
478 (sw_cap->trig_cqi_fb && hw_cap->trig_cqi_fb) ? 1 : 0;
479
480 proto_cap->vht_su_bfme =
481 (sw_cap->vht_su_bfme && hw_cap->vht_su_bfme) ? 1 : 0;
482 proto_cap->vht_su_bfmr =
483 (sw_cap->vht_su_bfmr && hw_cap->vht_su_bfmr) ? 1 : 0;
484 proto_cap->vht_mu_bfme =
485 (sw_cap->vht_mu_bfme && hw_cap->vht_mu_bfme) ? 1 : 0;
486 proto_cap->vht_mu_bfmr =
487 (sw_cap->vht_mu_bfmr && hw_cap->vht_mu_bfmr) ? 1 : 0;
488
489 proto_cap->ht_su_bfme =
490 (sw_cap->ht_su_bfme && hw_cap->ht_su_bfme) ? 1 : 0;
491 proto_cap->ht_su_bfmr =
492 (sw_cap->ht_su_bfmr && hw_cap->ht_su_bfmr) ? 1 : 0;
493
494 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
495 "rtw_hal_get_bf_proto_cap : proto_cap->he_su_bfmr = 0x%x \n",
496 proto_cap->he_su_bfmr);
497 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
498 "rtw_hal_get_bf_proto_cap : proto_cap->he_su_bfme = 0x%x \n",
499 proto_cap->he_su_bfme);
500 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
501 "rtw_hal_get_bf_proto_cap : proto_cap->he_mu_bfmr = 0x%x \n",
502 proto_cap->he_mu_bfmr);
503 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
504 "rtw_hal_get_bf_proto_cap : proto_cap->he_mu_bfme = 0x%x \n",
505 proto_cap->he_mu_bfme);
506 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
507 "rtw_hal_get_bf_proto_cap : proto_cap->non_trig_cqi_fb = 0x%x \n",
508 proto_cap->non_trig_cqi_fb);
509 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
510 "rtw_hal_get_bf_proto_cap : proto_cap->trig_cqi_fb = 0x%x \n",
511 proto_cap->trig_cqi_fb);
512 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
513 "rtw_hal_get_bf_proto_cap : proto_cap->vht_su_bfme = 0x%x \n",
514 proto_cap->vht_su_bfme);
515 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
516 "rtw_hal_get_bf_proto_cap : proto_cap->vht_su_bfmr = 0x%x \n",
517 proto_cap->vht_su_bfmr);
518 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
519 "rtw_hal_get_bf_proto_cap : proto_cap->vht_mu_bfme = 0x%x \n",
520 proto_cap->vht_mu_bfme);
521 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
522 "rtw_hal_get_bf_proto_cap : proto_cap->vht_mu_bfmr = 0x%x \n",
523 proto_cap->vht_mu_bfmr);
524 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
525 "rtw_hal_get_bf_proto_cap : proto_cap->ht_su_bfme = 0x%x \n",
526 proto_cap->ht_su_bfme);
527 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
528 "rtw_hal_get_bf_proto_cap : proto_cap->ht_su_bfmr = 0x%x \n",
529 proto_cap->ht_su_bfmr);
530 #endif
531 return RTW_HAL_STATUS_SUCCESS;
532 }
533
534
535 /**
536 * rtw_hal_get_stbc_proto_cap() - Get the intersection proto_cap of the proto_hw_cap and proto_sw_cap
537 * @phl_com: input, the pointer of phl_com (struct rtw_phl_com_t)
538 * @hal: input, the pointer of hal (struct hal_info_t)
539 * @band: input, the band index
540 * @proto_cap: input_output (struct protocol_cap_t)
541 * The variable pointer to save the ouput proto_cap results.
542 * Here, we update STBC cap into STBC fileds of proto_cap.
543 * Return: return the result of getting proto_cap (enum @rtw_hal_status)
544 */
545 enum rtw_hal_status
rtw_hal_get_stbc_proto_cap(struct rtw_phl_com_t * phl_com,void * hal,u8 band,struct protocol_cap_t * proto_cap)546 rtw_hal_get_stbc_proto_cap(struct rtw_phl_com_t *phl_com, void *hal,
547 u8 band, struct protocol_cap_t *proto_cap)
548 {
549 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
550 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
551 struct protocol_cap_t *hw_cap = NULL;
552 struct protocol_cap_t *sw_cap = NULL;
553
554 if (band >= HW_BAND_MAX) {
555 PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "rtw_hal_get_stbc_proto_cap : invalid band index \n");
556 return RTW_HAL_STATUS_FAILURE;
557 }
558 if (proto_cap == NULL) {
559 PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "rtw_hal_get_stbc_proto_cap : input proto_cap is NULL \n");
560 return RTW_HAL_STATUS_FAILURE;
561 }
562
563 hw_cap = &hal_com->proto_hw_cap[band];
564 sw_cap = &phl_com->proto_sw_cap[band];
565
566 proto_cap->stbc_tx =
567 (sw_cap->stbc_tx && hw_cap->stbc_tx) ? 1 : 0; /* Remove later */
568 proto_cap->stbc_ht_tx =
569 (sw_cap->stbc_ht_tx && hw_cap->stbc_ht_tx) ? 1 : 0;
570 proto_cap->stbc_vht_tx =
571 (sw_cap->stbc_vht_tx && hw_cap->stbc_vht_tx) ? 1 : 0;
572 proto_cap->stbc_he_tx =
573 (sw_cap->stbc_he_tx && hw_cap->stbc_he_tx) ? 1 : 0;
574 proto_cap->stbc_tx_greater_80mhz =
575 (sw_cap->stbc_tx_greater_80mhz && hw_cap->stbc_tx_greater_80mhz) ? 1 : 0;
576
577 proto_cap->stbc_ht_rx =
578 (sw_cap->stbc_ht_rx <= hw_cap->stbc_ht_rx) ?
579 sw_cap->stbc_ht_rx : hw_cap->stbc_ht_rx;
580 proto_cap->stbc_vht_rx =
581 (sw_cap->stbc_vht_rx <= hw_cap->stbc_vht_rx) ?
582 sw_cap->stbc_vht_rx : hw_cap->stbc_vht_rx;
583 proto_cap->stbc_he_rx =
584 (sw_cap->stbc_he_rx && hw_cap->stbc_he_rx) ? 1 : 0;
585 proto_cap->stbc_rx_greater_80mhz =
586 (sw_cap->stbc_rx_greater_80mhz && hw_cap->stbc_rx_greater_80mhz) ? 1 : 0;
587
588 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
589 "%s : proto_cap->stbc_tx = 0x%x \n",
590 __func__, proto_cap->stbc_tx); /* Remove later */
591 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
592 "%s : proto_cap->stbc_ht_tx = 0x%x \n",
593 __func__, proto_cap->stbc_ht_tx);
594 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
595 "%s : proto_cap->stbc_vht_tx = 0x%x \n",
596 __func__, proto_cap->stbc_vht_tx);
597 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
598 "%s : proto_cap->stbc_he_tx = 0x%x \n",
599 __func__, proto_cap->stbc_he_tx);
600 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
601 "%s : proto_cap->stbc_tx_greater_80mhz = 0x%x \n",
602 __func__, proto_cap->stbc_tx_greater_80mhz);
603 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
604 "%s : proto_cap->stbc_ht_rx = 0x%x \n",
605 __func__, proto_cap->stbc_ht_rx);
606 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
607 "%s : proto_cap->stbc_vht_rx = 0x%x \n",
608 __func__, proto_cap->stbc_vht_rx);
609 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
610 "%s : proto_cap->stbc_he_rx = 0x%x \n",
611 __func__, proto_cap->stbc_he_rx);
612 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
613 "%s : proto_cap->stbc_rx_greater_80mhz = 0x%x \n",
614 __func__, proto_cap->stbc_rx_greater_80mhz);
615
616 return RTW_HAL_STATUS_SUCCESS;
617 }
618