1 /****************************************************************************** 2 * 3 * Copyright(c) 2019 - 2021 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef _PHL_DEF_H_ 16 #define _PHL_DEF_H_ 17 18 enum phl_packet_type { 19 PACKET_NORMAL, 20 PACKET_DHCP, 21 PACKET_ARP, 22 PACKET_EAPOL, 23 PACKET_EAPOL_START, 24 PACKET_MAX 25 }; 26 27 /*HW_BAND0 - CMAC0 + PHY0 + S0*/ 28 /*HW_BAND1 - CMAC1 + PHY1 + S1*/ 29 /*wifi_role->hw_band*/ 30 enum phl_band_idx { 31 HW_BAND_0, 32 HW_BAND_1, 33 HW_BAND_MAX 34 }; 35 36 /*wifi_role->hw_port*/ 37 enum phl_hw_port { 38 HW_PORT0, 39 HW_PORT1, 40 HW_PORT2, 41 HW_PORT3, 42 HW_PORT4, 43 HW_PORT_MAX, 44 }; 45 46 #define RTW_MAX_TID_NUM 16 47 #define RTW_MAX_AC_QUEUE_NUM 4 48 enum phl_ac_queue { 49 PHL_BE_QUEUE_SEL = 0, 50 PHL_BK_QUEUE_SEL = 1, 51 PHL_VI_QUEUE_SEL = 2, 52 PHL_VO_QUEUE_SEL = 3, 53 PHL_AC_QUEUE_TOTAL 54 }; 55 56 enum phl_stat_info_query { 57 STAT_INFO_FA_ALL, 58 STAT_INFO_CCA_ALL, 59 }; 60 61 /** 62 * struct rtw_chan_def - channel defination 63 * @chan: the (control/primary) channel 64 * @center_ch: the center channel 65 * @bw: channel bandwidth 66 * @center_freq1: center frequency of first segment 67 * @center_freq2: center frequency of second segment 68 * (only with 80+80 MHz) 69 */ 70 71 struct rtw_chan_def { 72 enum band_type band; /* protocol -2.4G,5G,6G*/ 73 enum channel_width bw; 74 enum chan_offset offset; 75 u8 chan; /*primary channel*/ 76 u8 center_ch; 77 u16 hw_value; 78 u32 center_freq1; 79 u32 center_freq2; 80 }; 81 82 struct chg_opch_param { 83 struct rtw_wifi_role_t *wrole; 84 struct rtw_chan_def new_chdef; 85 struct rtw_chan_def ori_chdef; 86 enum rtw_phl_status cmd_start_sts; 87 void (*chg_opch_done)(void *priv, u8 ridx, enum rtw_phl_status status); 88 }; 89 90 /** 91 * struct rtw_chan_ctx - channel context 92 * @list: 93 * @chan_ctx_lock: 94 * @chan_def: 95 */ 96 struct rtw_chan_ctx { 97 _os_list list; 98 struct rtw_chan_def chan_def; 99 u8 role_map; /*used role_idx*/ 100 bool dfs_enabled; 101 }; 102 103 104 #ifdef CONFIG_PCI_HCI 105 struct rtw_pci_info { 106 u8 dummy; 107 }; 108 #endif 109 110 111 #ifdef CONFIG_USB_HCI 112 struct rtw_usb_info { 113 enum rtw_usb_speed usb_speed; /* USB 1.1, 2.0 or 3.0 */ 114 u16 usb_bulkout_size; 115 u8 outep_num; 116 u8 inep_num; 117 }; 118 119 enum phl_usb_rx_agg_mode { 120 PHL_RX_AGG_DISABLE, 121 PHL_RX_AGG_DEFAULT, 122 PHL_RX_AGG_SMALL_PKT, 123 PHL_RX_AGG_USER_DEFINE, 124 }; 125 /* 126 * refers to _usb.h 127 * #define SWITCHMODE 0x2 128 * #define FORCEUSB3MODE 0x1 129 * #define FORCEUSB2MODE 0x0 130 */ 131 enum rtw_usb_sw_ability { 132 RTW_USB2_ONLY = 0, 133 RTW_USB3_ONLY, 134 RTW_USB_SUPPORT_SWITCH, 135 RTW_USB_SUPPORT_MAX 136 }; 137 #endif 138 139 #ifdef CONFIG_SDIO_HCI 140 struct rtw_sdio_info { 141 unsigned int clock; 142 unsigned int timing; 143 u8 sd3_bus_mode; 144 u16 block_sz; 145 u16 io_align_sz; 146 u16 tx_align_sz; 147 bool tx_512_by_byte_mode; /* Send 512 bytes by cmd53 byte or */ 148 /* block mode. */ 149 }; 150 #endif 151 152 enum rtw_rx_status { 153 RTW_STATUS_RX_OK, 154 RTW_STATUS_RXDMA_HANG, 155 RTW_STATUS_RXFIFO_HANG 156 }; 157 158 struct rtw_ic_info { 159 enum rtl_ic_id ic_id; 160 enum rtw_hci_type hci_type; 161 #ifdef CONFIG_SDIO_HCI 162 struct rtw_sdio_info sdio_info; 163 #endif 164 165 #ifdef CONFIG_USB_HCI 166 struct rtw_usb_info usb_info; 167 #endif 168 169 #ifdef CONFIG_PCI_HCI 170 struct rtw_pci_info pci_info; 171 #endif 172 }; 173 174 enum rtw_proc_cmd_type { 175 RTW_PROC_CMD_UNKNOW, 176 RTW_PROC_CMD_BB, /* 1 */ 177 RTW_PROC_CMD_RF, /* 2 */ 178 RTW_PROC_CMD_MAC, /* 3 */ 179 RTW_PROC_CMD_PHL, /* 4 */ 180 RTW_PROC_CMD_CORE, /* 5 */ 181 RTW_PROC_CMD_BTC, /* 6 */ 182 RTW_PROC_CMD_EFUSE, /* 7 */ 183 RTW_PROC_CMD_MAX 184 }; 185 186 enum rtw_arg_type { 187 RTW_ARG_TYPE_UNKNOW, 188 RTW_ARG_TYPE_BUF, /* 1 */ 189 RTW_ARG_TYPE_ARRAY, /* 2 */ 190 RTW_ARG_TYPE_MAX 191 }; 192 193 #define MAX_ARGC 20 194 #define MAX_ARGV 16 195 196 197 struct rtw_proc_cmd { 198 enum rtw_arg_type in_type; 199 u32 in_cnt_len; 200 union { 201 char *buf; 202 char vector[MAX_ARGC][MAX_ARGV]; 203 }in; 204 }; 205 206 enum rtw_para_src { 207 RTW_PARA_SRC_INTNAL, /* 0 */ 208 RTW_PARA_SRC_EXTNAL, /* 1 */ 209 RTW_PARA_SRC_EXTNAL_BUF, /* 2 */ 210 RTW_PARA_SRC_CUSTOM, /* 3 */ 211 RTW_PARA_SRC_MAX 212 }; 213 214 struct rtw_para_info_t { 215 enum rtw_para_src para_src; 216 char para_path[256]; 217 char *hal_phy_folder; 218 char postfix[33]; 219 220 u8 *ext_para_file_buf; 221 u32 ext_para_file_buf_len; 222 u32 para_data_len; 223 u32 *para_data; 224 }; 225 226 #define regd_name_max_size 32 227 228 struct rtw_para_pwrlmt_info_t { 229 enum rtw_para_src para_src; 230 char para_path[256]; 231 char *hal_phy_folder; 232 char postfix[33]; 233 234 u8 *ext_para_file_buf; 235 u32 ext_para_file_buf_len; 236 u32 para_data_len; 237 u32 *para_data; 238 239 char ext_regd_name[regd_name_max_size][10]; 240 u16 ext_regd_arridx; 241 u16 ext_reg_map_num; 242 u8 *ext_reg_codemap; 243 }; 244 245 #define RTW_PHL_HANDLER_STATUS_INITIALIZED BIT0 246 #define RTW_PHL_HANDLER_STATUS_SET BIT1 247 #define RTW_PHL_HANDLER_STATUS_RELEASED BIT2 248 249 #define RTW_PHL_HANDLER_PRIO_HIGH 0 250 #define RTW_PHL_HANDLER_PRIO_NORMAL 1 251 #define RTW_PHL_HANDLER_PRIO_LOW 2 252 253 enum rtw_phl_evt { 254 RTW_PHL_EVT_RX = BIT0, 255 RTW_PHL_EVT_TX_RECYCLE = BIT1, 256 257 RTW_PHL_EVT_MAX = BIT31 258 }; 259 260 enum rtw_phl_config_int { 261 RTW_PHL_STOP_RX_INT, 262 RTW_PHL_RESUME_RX_INT, 263 RTW_PHL_SER_HANDSHAKE_MODE, 264 RTW_PHL_EN_HCI_INT, 265 RTW_PHL_DIS_HCI_INT, 266 RTW_PHL_CLR_HCI_INT, 267 RTW_PHL_CONFIG_INT_MAX 268 }; 269 270 /** 271 * phl_handler - scheduled by core layer or phl itself 272 * and the properties is assigned by different hanlder type 273 * @status: handler current status defined by RTW_PHL_HANDLER_STATUS_XXX 274 * @type: define different properties of handler - tasklet, thread, workitem 275 * @handle: store different type of handler structure 276 * @callback: handler callback function 277 * @context: context used in handler callback function 278 */ 279 struct rtw_phl_handler { 280 char status; 281 char type; 282 void *drv_priv; 283 struct _os_handler os_handler; 284 void (*callback)(void *context); 285 void *context; 286 }; 287 288 struct rtw_xmit_req; 289 struct rtw_aoac_report; 290 struct rtw_phl_evt_ops { 291 enum rtw_phl_status (*rx_process)(void *drv_priv); 292 enum rtw_phl_status (*tx_recycle)(void *drv_priv, struct rtw_xmit_req *txreq); 293 enum rtw_phl_status (*tx_test_recycle)(void *phl, struct rtw_xmit_req *txreq); 294 bool (*set_rf_state)(void *drv_priv, enum rtw_rf_state state_to_set); 295 void (*wow_handle_sec_info_update)(void *drv_priv, struct rtw_aoac_report *aoac_info, u8 aoac_report_get_ok, u8 phase); 296 void (*indicate_wake_rsn)(void *drv_priv, u8 rsn); 297 #ifdef CONFIG_SYNC_INTERRUPT 298 void (*interrupt_restore)(void *drv_priv, u8 rx); 299 void (*set_interrupt_caps)(void *drv_priv, u8 en); 300 #endif /* CONFIG_SYNC_INTERRUPT */ 301 void (*ap_ps_sta_ps_change)(void *drv_priv, u8 role_id, u8 *sta_mac, 302 int power_save); 303 u8 (*issue_null_data)(void *priv, u8 ridx, bool ps); 304 }; 305 306 /* 307 * PHL CMD support direct execution, no-wait: synchronization, wait:asynchronization 308 * PHL_CMD_CMD_DIRECTLY: call PHL API including I/O operation directly 309 * PHL_CMD_NO_WARIT: send phl cmd msg to cmd dispatcher and do not wait for completion 310 * PHL_CMD_WAIT: send phl cmd msg to cmd dispatcher and wait for completion 311 */ 312 enum phl_cmd_type { 313 PHL_CMD_DIRECTLY, 314 PHL_CMD_NO_WAIT, 315 PHL_CMD_WAIT, 316 PHL_CMD_MAX, 317 }; 318 319 enum role_type { 320 PHL_RTYPE_NONE, 321 PHL_RTYPE_STATION, 322 PHL_RTYPE_AP, 323 PHL_RTYPE_VAP, 324 PHL_RTYPE_ADHOC, 325 PHL_RTYPE_ADHOC_MASTER, 326 PHL_RTYPE_MESH, 327 PHL_RTYPE_MONITOR, 328 PHL_RTYPE_P2P_DEVICE, 329 PHL_RTYPE_P2P_GC, 330 PHL_RTYPE_P2P_GO, 331 PHL_RTYPE_TDLS, 332 PHL_RTYPE_NAN, 333 PHL_MLME_MAX 334 }; 335 336 enum role_state { 337 PHL_ROLE_START, /* 0 - PHL*/ 338 PHL_ROLE_STOP, /* 1 - PHL*/ 339 PHL_ROLE_CHG_TYPE, /* 2 - PHL*/ 340 PHL_ROLE_UPDATE_NOA, /* 3 - PHL*/ 341 PHL_ROLE_MSTS_STA_CONN_START, /*CORE*/ 342 PHL_ROLE_MSTS_STA_CONN_END,/*CORE*/ 343 PHL_ROLE_MSTS_STA_DIS_CONN,/*CORE*/ 344 PHL_ROLE_MSTS_AP_START,/*CORE*/ 345 PHL_ROLE_MSTS_AP_STOP,/*CORE*/ 346 PHL_ROLE_STATE_UNKNOWN, 347 }; 348 349 enum mlme_state { 350 MLME_NO_LINK, 351 MLME_LINKING, 352 MLME_LINKED 353 }; 354 enum wr_chg_id { 355 WR_CHG_TYPE, 356 WR_CHG_MADDR, 357 WR_CHG_AP_PARAM, 358 WR_CHG_EDCA_PARAM, 359 WR_CHG_MU_EDCA_PARAM, 360 WR_CHG_MU_EDCA_CFG, 361 WR_CHG_BSS_COLOR, 362 WR_CHG_RTS_TH, 363 WR_CHG_DFS_HE_TB_CFG, 364 WR_CHG_TRX_PATH, 365 WR_CHG_STBC_CFG, 366 WR_CHG_MAX, 367 }; 368 369 enum wr_status{ 370 WR_STATUS_PS_ANN = BIT0, 371 WR_STATUS_BCN_STOP = BIT1, 372 WR_STATUS_TSF_SYNC = BIT2, 373 WR_STATUS_MAX = BIT7 374 }; 375 376 enum rtw_cfg_type { /* sync with pcfg_type */ 377 CFG_TBTT_AGG, 378 CFG_TBTT_SHIFT, 379 CFG_HIQ_WIN, 380 CFG_HIQ_DTIM, 381 CFG_HIQ_MAX, 382 CFG_BCN_INTERVAL, /* Beacon Interval */ 383 CFG_BSS_CLR 384 }; 385 386 struct rtw_ap_param { 387 u32 cfg_id; 388 u32 value; 389 }; 390 391 struct rtw_edca_param { 392 /* Access Category, 0:BE, 1:BK, 2:VI, 3:VO */ 393 u8 ac; 394 /* 395 * EDCA parameter 396 * |31...16|15...12|11...8|7...0| 397 * | TXOP| CWMAX| CWMIN| AIFS| 398 */ 399 u32 param; 400 }; 401 402 struct rtw_mu_edca_param { 403 u8 ac; 404 u8 aifsn; 405 u8 cw; 406 u8 timer; 407 }; 408 409 struct rtw_trx_path_param { 410 enum rf_path tx; 411 enum rf_path rx; 412 u8 tx_nss; 413 u8 rx_nss; 414 }; 415 416 #define MAX_STORE_BCN_NUM 3 417 enum conf_lvl { 418 CONF_LVL_NONE = 0, 419 CONF_LVL_LOW, 420 CONF_LVL_MID, 421 CONF_LVL_HIGH 422 }; 423 424 struct rtw_bcn_offset { 425 u16 offset; /*TU*/ 426 enum conf_lvl conf_lvl; /*confidence level*/ 427 u16 cr_tbtt_shift; /* CR current setting */ 428 }; 429 430 /* 431 * Store rx bcn tsf info 432 * @num: the store noumber of "info" array 433 * @idx: store current index of "info" array 434 * @info: store array. info[0]: store tsf, info[1]: store mod(TU), info[2]: store hw rx time 435 * @offset_i: Bcn offset info. Dont't access directionly this variable for application. 436 You can get offset_i info from phl_get_sta_bcn_offset_info. 437 */ 438 struct rtw_rx_bcn_info { 439 u8 idx; 440 u8 num; 441 u64 info[3][MAX_STORE_BCN_NUM]; 442 struct rtw_bcn_offset offset_i; 443 }; 444 445 struct rtw_bcn_pkt_info { 446 struct rtw_phl_stainfo_t *sta; 447 u64 tsf; 448 u64 hw_tsf; 449 }; 450 451 struct rtw_rts_threshold { 452 u16 rts_time_th; 453 u16 rts_len_th; 454 }; 455 456 enum phl_module_id{ 457 /* 0 ~ 128 PHL background module starts from here*/ 458 /* 1,2,3 cmd controller section */ 459 PHL_BK_MDL_START = 0, 460 PHL_MDL_PHY_MGNT = 1, 461 PHL_MDL_TX = 2, 462 PHL_MDL_RX = 3, 463 464 /* above enum is fixed, add new module id from here*/ 465 /* 10 ~ 40 protocol, wifi role section*/ 466 PHL_BK_MDL_ROLE_START = 10, 467 PHL_MDL_MRC = 10, /* Multi-Role Controller intead of STA/P2P role /NAN/AP*/ 468 PHL_MDL_SOUND = 11, 469 470 PHL_BK_MDL_ROLE_END = 40, 471 472 /* 41 ~ 70 mandatory background module section*/ 473 PHL_BK_MDL_MDRY_START = 41, 474 PHL_MDL_POWER_MGNT = 41, 475 PHL_MDL_SER = 42, 476 477 PHL_BK_MDL_MDRY_END = 70, 478 479 /* 70 ~ 127 optional background module section*/ 480 PHL_BK_MDL_OPT_START = 71, 481 PHL_MDL_BTC = 71, 482 /*PHL_MDL_RSVD = 72,*/ 483 PHL_MDL_CUSTOM = 73, 484 PHL_MDL_WOW = 74, 485 PHL_MDL_PSTS = 75, 486 PHL_MDL_LED = 76, 487 PHL_MDL_GENERAL = 77, 488 PHL_MDL_REGU = 78, 489 490 PHL_BK_MDL_OPT_END = 127, 491 492 /* Fixed BK MDL Max Value*/ 493 PHL_BK_MDL_END = 128, 494 495 /* 129 ~ 256 PHL foreground module starts from here*/ 496 PHL_FG_MDL_START = 129, 497 PHL_FUNC_MDL_TEST_MODULE = 129, 498 PHL_FG_MDL_SCAN = 130, 499 PHL_FG_MDL_CONNECT = 131, 500 PHL_FG_MDL_DISCONNECT = 132, 501 PHL_FG_MDL_AP_START = 133, 502 PHL_FG_MDL_AP_STOP = 134, 503 PHL_FG_MDL_ECSA = 135, 504 PHL_FG_MDL_END = 254, 505 506 /* Fixed MDL Max Value*/ 507 PHL_MDL_ID_MAX = 255 508 }; 509 510 /* General phl event id shall share this common enum definition 511 * if definition of private events for a specific module is required, 512 * please be sure to start its enum from PRIVATE_EVT_START(0x8000) 513 */ 514 enum phl_msg_evt_id { 515 MSG_EVT_NONE = 0, 516 MSG_EVT_PHY_ON = 1, 517 MSG_EVT_PHY_IDLE = 2, 518 MSG_EVT_SCAN_START = 3, 519 MSG_EVT_SCAN_END = 4, 520 MSG_EVT_CONNECT_START = 5, 521 MSG_EVT_CONNECT_LINKED = 6, 522 MSG_EVT_CONNECT_END = 7, 523 MSG_EVT_SER_L1 = 8, 524 MSG_EVT_SER_L2 = 9, 525 MSG_EVT_FWDL_OK = 10, 526 MSG_EVT_FWDL_FAIL = 11, 527 MSG_EVT_HAL_INIT_OK = 12, 528 MSG_EVT_HAL_INIT_FAIL = 13, 529 MSG_EVT_MP_CMD_DONE = 14, 530 /* wow */ 531 MSG_EVT_WOW_ENTER = 15, 532 MSG_EVT_WOW_LEAVE = 16, 533 MSG_EVT_WOW_WAKE_RSN = 17, 534 MSG_EVT_BCN_RESEND = 18, 535 MSG_EVT_DUMP_PLE_BUFFER = 19, 536 MSG_EVT_MP_RX_PHYSTS = 20, 537 MSG_EVT_ROLE_NTFY = 21, 538 MSG_EVT_RX_PSTS = 22, 539 MSG_EVT_SWCH_START = 23, 540 MSG_EVT_SWCH_DONE = 24, 541 MSG_EVT_DISCONNECT_PREPARE = 25, 542 MSG_EVT_DISCONNECT = 26, 543 MSG_EVT_TSF_SYNC_DONE = 27, 544 MSG_EVT_TX_RESUME = 28, 545 MSG_EVT_AP_START_PREPARE =29, 546 MSG_EVT_AP_START = 30, 547 MSG_EVT_AP_START_END = 31, 548 MSG_EVT_AP_STOP_PREPARE = 32, 549 MSG_EVT_AP_STOP = 33, 550 MSG_EVT_PCIE_TRX_MIT = 34, 551 MSG_EVT_BTC_TMR = 35, 552 MSG_EVT_BTC_FWEVNT = 36, 553 MSG_EVT_BTC_REQ_BT_SLOT = 37, 554 MSG_EVT_BTC_PKT_EVT_NTFY = 38, 555 /* ser*/ 556 MSG_EVT_SER_L0_RESET = 39, /* L0 notify only */ 557 MSG_EVT_SER_M1_PAUSE_TRX = 40, 558 MSG_EVT_SER_IO_TIMER_EXPIRE = 41, 559 MSG_EVT_SER_FW_TIMER_EXPIRE = 42, 560 MSG_EVT_SER_M3_DO_RECOV = 43, 561 MSG_EVT_SER_M5_READY = 44, 562 MSG_EVT_SER_M9_L2_RESET = 45, 563 MSG_EVT_SER_EVENT_CHK = 46, 564 MSG_EVT_SER_POLLING_CHK = 47, 565 MSG_EVT_ECSA_START = 48, 566 MSG_EVT_ECSA_UPDATE_FIRST_BCN_DONE = 49, 567 MSG_EVT_ECSA_COUNT_DOWN = 50, 568 MSG_EVT_ECSA_SWITCH_START = 51, 569 MSG_EVT_ECSA_SWITCH_DONE = 52, 570 MSG_EVT_ECSA_CHECK_TX_RESUME = 53, 571 MSG_EVT_ECSA_DONE = 54, 572 MSG_EVT_LISTEN_STATE_EXPIRE = 55, 573 /* beamform */ 574 MSG_EVT_SET_VHT_GID = 56, 575 MSG_EVT_HW_WATCHDOG = 57, 576 MSG_EVT_DEV_CANNOT_IO = 58, 577 MSG_EVT_DEV_RESUME_IO = 59, 578 MSG_EVT_FORCE_USB_SW = 60, 579 MSG_EVT_GET_USB_SPEED = 61, 580 MSG_EVT_GET_USB_SW_ABILITY = 62, 581 MSG_EVT_CFG_AMPDU = 63, 582 MSG_EVT_DFS_PAUSE_TX = 64, 583 MSG_EVT_ROLE_RECOVER = 65, 584 MSG_EVT_ROLE_SUSPEND = 66, 585 MSG_EVT_HAL_SET_L2_LEAVE = 67, 586 MSG_EVT_NOTIFY_HAL = 68, 587 MSG_EVT_ISSUE_BCN = 69, 588 MSG_EVT_FREE_BCN = 70, 589 MSG_EVT_STOP_BCN = 71, 590 MSG_EVT_SEC_KEY = 72, 591 MSG_EVT_ROLE_START = 73, 592 MSG_EVT_ROLE_CHANGE = 74, 593 MSG_EVT_ROLE_STOP = 75, 594 MSG_EVT_STA_INFO_CTRL = 76, 595 MSG_EVT_STA_MEDIA_STATUS_UPT = 77, 596 MSG_EVT_CFG_CHINFO = 78, 597 MSG_EVT_STA_CHG_STAINFO = 79, 598 MSG_EVT_HW_TRX_RST_RESUME = 80, 599 MSG_EVT_HW_TRX_PAUSE = 81, 600 MSG_EVT_SW_TX_RESUME = 82, 601 MSG_EVT_SW_RX_RESUME = 83, 602 MSG_EVT_SW_TX_PAUSE = 84, 603 MSG_EVT_SW_RX_PAUSE = 85, 604 MSG_EVT_SW_TX_RESET = 86, 605 MSG_EVT_SW_RX_RESET = 87, 606 MSG_EVT_TRX_SW_PAUSE = 88, 607 MSG_EVT_TRX_SW_RESUME = 89, 608 MSG_EVT_TRX_PAUSE_W_RST = 90, 609 MSG_EVT_TRX_RESUME_W_RST = 91, 610 /* Regulation*/ 611 MSG_EVT_REGU_SET_DOMAIN = 92, 612 MSG_EVT_RF_ON = 93, 613 MSG_EVT_RF_OFF = 94, 614 MSG_EVT_WPS_PRESSED = 95, 615 MSG_EVT_WPS_RELEASED = 96, 616 MSG_EVT_SURPRISE_REMOVE = 97, 617 MSG_EVT_DATA_PATH_START = 98, 618 MSG_EVT_DATA_PATH_STOP = 99, 619 MSG_EVT_TRX_PWR_REQ = 100, 620 /* tdls */ 621 MSG_EVT_TDLS_SYNC = 101, 622 /* beamformee */ 623 MSG_EVT_SET_BFEE_AID = 102, 624 /* ccx */ 625 MSG_EVT_CCX_REPORT_TX_OK = 103, 626 MSG_EVT_CCX_REPORT_TX_FAIL = 104, 627 /* ps */ 628 MSG_EVT_PS_CAP_CHG = 105, 629 MSG_EVT_PS_PERIOD_CHK = 106, 630 MSG_EVT_PS_DBG_LPS_ENTER = 107, 631 MSG_EVT_PS_DBG_LPS_LEAVE = 108, 632 MSG_EVT_PS_DBG_IPS_ENTER = 109, 633 MSG_EVT_PS_DBG_IPS_LEAVE = 110, 634 /* Change operating ch def(ch / bw) */ 635 MSG_EVT_CHG_OP_CH_DEF_START = 111, 636 MSG_EVT_CHG_OP_CH_DEF_END = 112, 637 MSG_EVT_MDL_CHECK_STOP = 113, 638 MSG_EVT_HW_RF_CHG = 114, 639 640 MSG_EVT_TX_PKT_NTFY = 115, 641 MSG_EVT_SW_WATCHDOG = 116, 642 /* ltr */ 643 MSG_EVT_LTR_TX_DLY = 199, 644 /* dbg */ 645 MSG_EVT_DBG_SIP_REG_DUMP = 200, 646 MSG_EVT_DBG_FULL_REG_DUMP = 201, 647 MSG_EVT_DBG_L2_DIAGNOSE = 202, 648 MSG_EVT_DBG_RX_DUMP = 203, 649 MSG_EVT_DBG_TX_DUMP = 204, 650 /* dbg end */ 651 /* p2pps */ 652 MSG_EVT_TSF32_TOG = 205, 653 /* p2pps end */ 654 /*Add EVT-ID for linux core cmd temporality*/ 655 656 /* sub module IO */ 657 MSG_EVT_NOTIFY_BB = 300, 658 MSG_EVT_NOTIFY_RF = 301, 659 MSG_EVT_NOTIFY_MAC = 302, 660 /* sub module IO end*/ 661 662 MSG_EVT_LINUX_CMD_WRK = 888, 663 MSG_EVT_LINUX_CMD_WRK_TRI_PS = 889, 664 /* LED */ 665 MSG_EVT_LED_TICK = 5000, 666 MSG_EVT_LED_EVT_START = 5001, 667 MSG_EVT_LED_EVT_END = 5050, 668 MSG_EVT_MAX = 0x7fff 669 }; 670 671 672 673 enum phl_msg_recver_layer { 674 MSG_RECV_PHL = 0, 675 MSG_RECV_CORE = 1, 676 MSG_RECV_MAX 677 }; 678 679 enum phl_msg_indicator { 680 MSG_INDC_PRE_PHASE = BIT0, 681 MSG_INDC_FAIL = BIT1, 682 MSG_INDC_CANCEL = BIT2, 683 MSG_INDC_CANNOT_IO = BIT3 684 }; 685 686 enum phl_msg_opt { 687 MSG_OPT_SKIP_NOTIFY_OPT_MDL = BIT0, 688 MSG_OPT_BLIST_PRESENT = BIT1, 689 MSG_OPT_CLR_SNDR_MSG_IF_PENDING = BIT2, 690 MSG_OPT_SEND_IN_ABORT = BIT3, 691 MSG_OPT_PENDING_DURING_CANNOT_IO = BIT4, 692 }; 693 694 695 /* all module share this common enum definition */ 696 enum phy_bk_module_opcode { 697 BK_MODL_OP_NONE = 0, 698 BK_MODL_OP_CHK_NEW_MSG, 699 BK_MODL_OP_INPUT_CMD, 700 BK_MODL_OP_STATE, 701 BK_MODL_OP_CUS_SET_ROLE_CAP, 702 BK_MODL_OP_CUS_UPDATE_ROLE_CAP, 703 BK_MODL_OP_MAX 704 }; 705 706 /* Foreground cmd token opcode */ 707 enum phy_fg_cmd_req_opcode { 708 FG_REQ_OP_NONE = 0, 709 FG_REQ_OP_GET_ROLE, 710 FG_REQ_OP_GET_MDL_ID, 711 #ifdef RTW_WKARD_MRC_ISSUE_NULL_WITH_SCAN_OPS 712 FG_REQ_OP_GET_SCAN_PARAM, 713 FG_REQ_OP_GET_ISSUE_NULL_OPS, 714 #endif 715 #ifdef RTW_WKARD_CMD_SCAN_EXTEND_ACTIVE_SCAN 716 FG_REQ_OP_NOTIFY_BCN_RCV, 717 #endif 718 #ifdef RTW_WKARD_CMD_SCAN_EXTEND_ACTION_FRAME_TX 719 FG_REQ_OP_NOTIFY_ACTION_FRAME_TX, 720 #endif 721 FG_REQ_OP_MAX 722 }; 723 724 /* priority of phl background 725 module which would be considered when dispatching phl msg*/ 726 enum phl_bk_module_priority { 727 PHL_MDL_PRI_ROLE = 0, 728 PHL_MDL_PRI_OPTIONAL, 729 PHL_MDL_PRI_MANDATORY, 730 PHL_MDL_PRI_MAX 731 }; 732 733 enum phl_data_ctl_cmd { 734 PHL_DATA_CTL_HW_TRX_RST_RESUME = 1, 735 PHL_DATA_CTL_HW_TRX_PAUSE = 2, 736 PHL_DATA_CTL_SW_TX_RESUME = 3, 737 PHL_DATA_CTL_SW_RX_RESUME = 4, 738 PHL_DATA_CTL_SW_TX_PAUSE = 5, 739 PHL_DATA_CTL_SW_RX_PAUSE = 6, 740 PHL_DATA_CTL_SW_TX_RESET = 7, 741 PHL_DATA_CTL_SW_RX_RESET = 8, 742 PHL_DATA_CTL_TRX_SW_PAUSE = 9, 743 PHL_DATA_CTL_TRX_SW_RESUME = 10, 744 PHL_DATA_CTL_TRX_PAUSE_W_RST = 11, 745 PHL_DATA_CTL_TRX_RESUME_W_RST = 12, 746 PHL_DATA_CTL_MAX = 0xFF 747 }; 748 749 /** 750 * phl_msg - define a general msg format for PHL/CORE layer module to handle 751 * one can easily extend additional mgnt info by encapsulating inside a file 752 * refer to 753 * struct phl_msg_ex in phl_msg_hub.c 754 * struct phl_dispr_msg_ex in phl_cmd_dispatcher.c 755 * 756 * @msg_id: indicate msg source & msg type 757 * BYTE 3: RSVD 758 * BYTE 2: PHL Module ID, refer to enum phl_module_id 759 * BYTE 0-1: event id, refer to enum phl_msg_evt_id 760 * @inbuf: input buffer that sent along with msg 761 * @inlen: input buffer length 762 * @outbuf: output buffer that returned after all phl modules have recved msg. 763 * @outlen: output buffer length 764 * @band_idx: index of Band(PHY) which associate to this msg 765 766 * @rsvd: feature reserved, passing object pointer. 767 * For example, 768 * - cmd_scan : [0]: wifi_role. 769 * - CANNOT_IO error: [0]: mdl handle. 770 */ 771 struct phl_msg{ 772 u32 msg_id; 773 enum phl_band_idx band_idx; 774 u8* inbuf; 775 u8* outbuf; 776 u32 inlen; 777 u32 outlen; 778 void *rsvd[4]; 779 }; 780 781 struct msg_notify_map { 782 u8* id_arr; 783 u8 len; 784 }; 785 struct msg_dispatch_seq { 786 struct msg_notify_map map[PHL_MDL_PRI_MAX]; 787 }; 788 struct msg_self_def_seq { 789 struct msg_dispatch_seq pre_prot_phase; 790 struct msg_dispatch_seq post_prot_phase; 791 }; 792 struct msg_completion_routine { 793 void* priv; 794 void (*completion)(void* priv, struct phl_msg* msg); 795 }; 796 /** 797 * phl_msg_attribute: used in phl_disp_eng_send_msg 798 * @opt: refers to enum phl_msg_opt. 799 * @notify: input id array (refer to enum phl_module_id) 800 * for indicating additional dependency 801 * @completion: completion routine 802 */ 803 struct phl_msg_attribute { 804 u8 opt; 805 struct msg_notify_map notify; 806 struct msg_completion_routine completion; 807 #ifdef CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ 808 void *dispr_attr; 809 #endif 810 }; 811 812 /** 813 * phl_module_op_info - set by core layer or phl itself, 814 * op code process is an synchronous process. 815 * which would be handled directly by module handler 816 * @op_code: refer to enum phy_module_opcode 817 * @inbuf: input buffer that sent along with msg 818 * @inlen: input buffer length 819 * @outbuf: output buffer that returned after all phy modules have recved msg. 820 * @outlen: output buffer length 821 */ 822 struct phl_module_op_info{ 823 u32 op_code; 824 u8* inbuf; 825 u8* outbuf; 826 u32 inlen; 827 u32 outlen; 828 }; 829 830 /** 831 * phl_cmd_token_req - request foramt for applying token of a specific cmd 832 * dispatcher. 833 * cmd token request is regarded as foreground module, thus, 834 * need to contend for cmd token. 835 * Normally, these req would be linked to a specific wifi role 836 * and acquiring RF resource for a specific task. 837 * 838 * @module_id: starting from PHL_FG_MDL_START 839 * @priv: private context from requestor 840 * @role: designated role info associated with current request. 841 * ----------------------------------------- 842 * regarding on "return code" for following ops, refer to enum phl_mdl_ret_code 843 * ----------------------------------------- 844 * @acquired: notify requestor when cmd token has acquired for this cmd and 845 cannot have any I/O operation. 846 * @abort: notify requestor when cmd has been canceled 847 after calling rtw_phl_phy_cancel_token_req and 848 cannot have any I/O operation. 849 * @msg_hdlr: notify requestor about incoming msg. 850 * @set_info: notify requestor to handle specific op code. 851 * @query_info: notify requestor to handle specific op code. 852 */ 853 854 struct phl_cmd_token_req{ 855 u8 module_id; 856 void* priv; 857 void* role; 858 enum phl_mdl_ret_code (*acquired)(void* dispr, void* priv); 859 enum phl_mdl_ret_code (*abort)(void* dispr, void* priv); 860 enum phl_mdl_ret_code (*msg_hdlr)(void* dispr, void* priv, 861 struct phl_msg* msg); 862 enum phl_mdl_ret_code (*set_info)(void* dispr, void* priv, 863 struct phl_module_op_info* info); 864 enum phl_mdl_ret_code (*query_info)(void* dispr, void* priv, 865 struct phl_module_op_info* info); 866 }; 867 /** 868 * phl_module_ops - standard interface for interacting with a cmd dispatcher. 869 * ----------------------------------------- 870 * regarding on "return code" for following ops, refer to enum phl_mdl_ret_code 871 * ----------------------------------------- 872 * @init: notify module for initialization. 873 * @deinit: notify module for de-initialization. 874 * @start: notify module to start. 875 * @stop: notify module to stop. 876 * @msg_hdlr: notify module about incoming msg. 877 * @set_info: notify module to handle specific op code. 878 * @query_info: notify module to handle specific op code. 879 */ 880 struct phl_bk_module_ops { 881 enum phl_mdl_ret_code (*init)(void* phl_info, void* dispr, void** priv); 882 void (*deinit)(void* dispr, void* priv); 883 enum phl_mdl_ret_code (*start)(void* dispr, void* priv); 884 enum phl_mdl_ret_code (*stop)(void* dispr, void* priv); 885 enum phl_mdl_ret_code (*msg_hdlr)(void* dispr, void* priv, 886 struct phl_msg* msg); 887 enum phl_mdl_ret_code (*set_info)(void* dispr, void* priv, 888 struct phl_module_op_info* info); 889 enum phl_mdl_ret_code (*query_info)(void* dispr, void* priv, 890 struct phl_module_op_info* info); 891 }; 892 893 /** 894 * phl_data_ctl_t - datapath control parameters for dispatcher controller 895 * @cmd: data path control command 896 * @id: module id which request data path control 897 */ 898 struct phl_data_ctl_t { 899 enum phl_data_ctl_cmd cmd; 900 enum phl_module_id id; 901 }; 902 903 #define MSG_MDL_ID_FIELD(_msg_id) (((_msg_id) >> 16) & 0xFF) 904 #define MSG_EVT_ID_FIELD(_msg_id) ((_msg_id) & 0xFFFF) 905 #define MSG_INDC_FIELD(_msg_id) (((_msg_id) >> 24) & 0xFF) 906 #define IS_PRIVATE_MSG(_msg_id) ((_msg_id) & PRIVATE_EVT_START) 907 #define IS_MSG_FAIL(_msg_id) ((_msg_id) & ( MSG_INDC_FAIL << 24)) 908 #define IS_MSG_IN_PRE_PHASE(_msg_id) ((_msg_id) & ( MSG_INDC_PRE_PHASE << 24)) 909 #define IS_MSG_CANCEL(_msg_id) ((_msg_id) & ( MSG_INDC_CANCEL << 24)) 910 #define IS_MSG_CANNOT_IO(_msg_id) ((_msg_id) & ( MSG_INDC_CANNOT_IO << 24)) 911 #define SET_MSG_MDL_ID_FIELD(_msg_id, _id) \ 912 ((_msg_id) = (((_msg_id) & 0xFF00FFFF) | ((u32)(_id) << 16))) 913 #define SET_MSG_EVT_ID_FIELD(_msg_id, _id) \ 914 ((_msg_id) = (((_msg_id) & 0xFFFF0000) | (_id))) 915 #define SET_MSG_INDC_FIELD(_msg_id, _indc) \ 916 ((_msg_id) = (((_msg_id) & ~((u32)(_indc) << 24))|((u32)(_indc) << 24))) 917 #define CLEAR_MSG_INDC_FIELD(_msg_id, _indc) ((_msg_id) &= ~((_indc) << 24)) 918 919 #ifdef CONFIG_PHL_REDUCE_MEM 920 #define RTW_MAX_FW_SIZE 0x100000 921 #else 922 #define RTW_MAX_FW_SIZE 0x400000 923 #endif 924 925 enum rtw_fw_src { 926 RTW_FW_SRC_INTNAL, /* 0 */ 927 RTW_FW_SRC_EXTNAL, /* 1 */ 928 RTW_FW_SRC_MAX 929 }; 930 931 enum rtw_fw_rsn { 932 RTW_FW_RSN_INIT, /* 0 */ 933 RTW_FW_RSN_SPIC, /* 1 */ 934 RTW_FW_RSN_LPS, /* 2 */ 935 RTW_FW_RSN_MCC, /* 3 */ 936 RTW_FW_RSN_WOW, /* 4 */ 937 RTW_FW_RSN_MAX 938 }; 939 940 struct rtw_fw_cap_t { 941 enum rtw_fw_src fw_src; 942 u32 offload_cap; 943 u8 dlram_en; 944 u8 dlrom_en; 945 }; 946 947 #define INVALID_WIFI_ROLE_IDX MAX_WIFI_ROLE_NUMBER 948 #define UNSPECIFIED_ROLE_ID 0xFF 949 #define MAX_SECCAM_NUM_PER_ENTRY 7 950 951 /* Role hw TX CAP*/ 952 struct role_cap_t { 953 enum wlan_mode wmode; 954 enum channel_width bw; 955 u8 rty_lmt; /* retry limit for DATA frame, 0xFF: invalid */ 956 u8 rty_lmt_rts; /* retry limit for RTS frame, 0xFF: invalid */ 957 958 u8 tx_num_ampdu; 959 u8 tx_amsdu_in_ampdu; /*from SW & HW*/ 960 u8 tx_ampdu_len_exp; /*from SW & HW*/ 961 u8 tx_htc; 962 u8 tx_sgi; 963 964 u8 tx_ht_ldpc:1; 965 u8 tx_vht_ldpc:1; 966 u8 tx_he_ldpc:1; 967 u8 tx_ht_stbc:1; 968 u8 tx_vht_stbc:1; 969 u8 tx_he_stbc:1; 970 971 u8 supported_rates[12]; 972 }; 973 974 struct role_sw_cap_t { 975 u16 bf_cap; /* use define : HW_CAP_BFER_XX_XX */ 976 u16 stbc_cap;/* use define: HW_CAP_STBC_XX */ 977 }; 978 979 /* 980 Protocol - RX CAP from 80211 PKT, 981 driver TX related function need to 982 reference __rx__ of rtw_phl_stainfo_t->asoc_cap 983 */ 984 struct protocol_cap_t { 985 /* MAC related */ 986 u16 bcn_interval; /* beacon interval */ 987 u8 num_ampdu; 988 u8 ampdu_density:3; /* rx ampdu cap */ 989 u8 ampdu_len_exp; /* rx ampdu cap */ 990 u8 amsdu_in_ampdu:1; /* rx ampdu cap */ 991 u8 max_amsdu_len:2; /* 0: 4k, 1: 8k, 2: 11k */ 992 u8 htc_rx:1; 993 u8 sm_ps:2; 994 u8 trig_padding:2; 995 u8 twt:6; 996 u8 all_ack:1; 997 u8 a_ctrl:4; 998 u8 ops:1; 999 u8 ht_vht_trig_rx:1; 1000 u8 bsscolor; 1001 u16 rts_th:10; 1002 1003 u8 short_slot:1; /* Short Slot Time */ 1004 1005 u8 preamble:1; /* Preamble, 0: long, 1: short */ 1006 u8 sgi_20:1; /* HT Short GI for 20 MHz */ 1007 u8 sgi_40:1; /* HT Short GI for 40 MHz */ 1008 u8 sgi_80:1; /* VHT Short GI for 80 MHz */ 1009 u8 sgi_160:1; /* VHT Short GI for 160/80+80 MHz */ 1010 struct rtw_edca_param edca[4]; /* Access Category, 0:BE, 1:BK, 2:VI, 3:VO */ 1011 u8 mu_qos_info; 1012 struct rtw_mu_edca_param mu_edca[4]; 1013 1014 /* BB related */ 1015 u8 ht_ldpc:1; 1016 u8 vht_ldpc:1; 1017 u8 he_ldpc:1; 1018 u8 he_su_bfmr:1; 1019 u8 he_su_bfme:1; 1020 u8 he_mu_bfmr:1; 1021 u8 he_mu_bfme:1; 1022 u8 bfme_sts:3; 1023 u8 num_snd_dim:3; 1024 1025 u8 ht_su_bfmr:1; 1026 u8 ht_su_bfme:1; 1027 u8 vht_su_bfmr:1; 1028 u8 vht_su_bfme:1; 1029 u8 vht_mu_bfmr:1; 1030 u8 vht_mu_bfme:1; 1031 u8 ht_vht_ng:2; 1032 u8 ht_vht_cb:2; 1033 /* 1034 * supported_rates: Supported data rate of CCK/OFDM. 1035 * The rate definition follow Wi-Fi spec, unit is 500kb/s, 1036 * and the MSB(bit 7) represent basic rate. 1037 * ex. CCK 2Mbps not basic rate is encoded as 0x04, 1038 * and OFDM 6M basic rate is encoded as 0x8c. 1039 * Suppose rates come from Supported Rates and Extended Supported 1040 * Rates IE. 1041 * Value 0 means it is end of array, and no more valid data rate follow. 1042 */ 1043 u8 supported_rates[12]; 1044 u8 ht_rx_mcs[4]; 1045 u8 ht_tx_mcs[4]; 1046 u8 ht_basic_mcs[4]; /* Basic rate of HT */ 1047 u8 vht_rx_mcs[2]; 1048 u8 vht_tx_mcs[2]; 1049 u8 vht_basic_mcs[2]; /* Basic rate of VHT */ 1050 u8 he_rx_mcs[6];/*80,160,80+80*/ 1051 u8 he_tx_mcs[6];/*80,160,80+80*/ 1052 u8 he_basic_mcs[2]; /* Basic rate of HE */ 1053 u8 stbc_ht_rx:2; 1054 u8 stbc_vht_rx:3; 1055 u8 stbc_he_rx:1; 1056 u8 stbc_tx:1; 1057 u8 stbc_ht_tx:1; 1058 u8 stbc_vht_tx:1; 1059 u8 stbc_he_tx:1; 1060 u8 ltf_gi; 1061 u8 doppler_tx:1; 1062 u8 doppler_rx:1; 1063 u8 dcm_max_const_tx:2; 1064 u8 dcm_max_nss_tx:1; 1065 u8 dcm_max_const_rx:2; 1066 u8 dcm_max_nss_rx:1; 1067 u8 partial_bw_su_in_mu:1; 1068 u8 bfme_sts_greater_80mhz:3; 1069 u8 num_snd_dim_greater_80mhz:3; 1070 u8 stbc_tx_greater_80mhz:1; 1071 u8 stbc_rx_greater_80mhz:1; 1072 u8 ng_16_su_fb:1; 1073 u8 ng_16_mu_fb:1; 1074 u8 cb_sz_su_fb:1; 1075 u8 cb_sz_mu_fb:1; 1076 u8 trig_su_bfm_fb:1; 1077 u8 trig_mu_bfm_fb:1; 1078 u8 trig_cqi_fb:1; 1079 u8 partial_bw_su_er:1; 1080 u8 pkt_padding:2; 1081 u8 ppe_thr[8][4]; 1082 u8 pwr_bst_factor:1; 1083 u8 max_nc:3; 1084 u8 dcm_max_ru:2; 1085 u8 long_sigb_symbol:1; 1086 u8 non_trig_cqi_fb:1; 1087 u8 tx_1024q_ru:1; 1088 u8 rx_1024q_ru:1; 1089 u8 fbw_su_using_mu_cmprs_sigb:1; 1090 u8 fbw_su_using_mu_non_cmprs_sigb:1; 1091 u8 er_su:1; 1092 u8 tb_pe:3; 1093 u16 txop_du_rts_th; 1094 u8 he_rx_ndp_4x32:1; 1095 1096 /* RF related */ 1097 u8 nss_tx:3; 1098 u8 nss_rx:3; 1099 1100 u8 num_ampdu_bk; 1101 u8 cap_option; 1102 }; 1103 1104 #define EXT_CAP_LIMIT_2G_RX_STBC BIT0 1105 1106 1107 #define LOAD_MAC_REG_FILE BIT0 1108 #define LOAD_BB_PHY_REG_FILE BIT1 1109 #define LOAD_BB_PHY_REG_MP_FILE BIT2 1110 #define LOAD_RF_RADIO_FILE BIT3 1111 #define LOAD_RF_TXPWR_BY_RATE BIT4 1112 #define LOAD_RF_TXPWR_TRACK_FILE BIT5 1113 #define LOAD_RF_TXPWR_LMT_FILE BIT6 1114 #define LOAD_RF_TXPWR_LMT_RU_FILE BIT7 1115 #define LOAD_BB_PHY_REG_GAIN_FILE BIT8 1116 1117 #define PHL_UNDEFINED_SW_CAP 0xFF 1118 1119 struct rtw_pcie_ltr_lat_ctrl { 1120 enum rtw_pcie_bus_func_cap_t ctrl; 1121 u32 val; 1122 }; 1123 1124 enum rtw_pcie_ltr_state { 1125 RTW_PCIE_LTR_SW_ACT = 1, 1126 RTW_PCIE_LTR_SW_IDLE = 2 1127 }; 1128 1129 struct rtw_pcie_trx_mit_info_t { 1130 u32 tx_timer; 1131 u8 tx_counter; 1132 u32 rx_timer; 1133 u8 rx_counter; 1134 u8 fixed_mitigation; /*no watchdog dynamic setting*/ 1135 void *priv; 1136 }; 1137 1138 struct bus_sw_cap_t { 1139 #ifdef CONFIG_PCI_HCI 1140 enum rtw_pcie_bus_func_cap_t l0s_ctrl; 1141 enum rtw_pcie_bus_func_cap_t l1_ctrl; 1142 enum rtw_pcie_bus_func_cap_t l1ss_ctrl; 1143 enum rtw_pcie_bus_func_cap_t wake_ctrl; 1144 enum rtw_pcie_bus_func_cap_t crq_ctrl; 1145 u32 txbd_num; 1146 u32 rxbd_num; 1147 u32 rpbd_num; 1148 u32 rxbuf_num; 1149 u32 rpbuf_num; 1150 u32 read_txbd_lvl; /* 0: always read, 1: < 1/2 tx res, 2: < 1/4 tx res */ 1151 struct rtw_pcie_trx_mit_info_t mit_ctl; 1152 u8 clkdly_ctrl; 1153 u8 l0sdly_ctrl; 1154 u8 l1dly_ctrl; 1155 struct rtw_pcie_ltr_lat_ctrl ltr_act; 1156 struct rtw_pcie_ltr_lat_ctrl ltr_idle; 1157 u8 ltr_init_state; 1158 u16 ltr_sw_ctrl_thre; /* [15:8] tx [7:0] rx */ 1159 u8 ltr_sw_ctrl; 1160 u8 ltr_hw_ctrl; 1161 u32 ltr_last_trigger_time; 1162 u32 ltr_sw_act_tri_cnt; 1163 u32 ltr_sw_idle_tri_cnt; 1164 u8 ltr_cur_state; 1165 #ifdef RTW_WKARD_GET_PROCESSOR_ID 1166 u64 proc_id; /* processor id */ 1167 #endif 1168 #elif defined (CONFIG_USB_HCI) 1169 u32 tx_buf_size; 1170 u32 tx_buf_num; 1171 u32 tx_mgnt_buf_size; 1172 u32 tx_mgnt_buf_num; 1173 u32 tx_h2c_buf_num; 1174 u32 rx_buf_size; 1175 u32 rx_buf_num; 1176 u32 in_token_num; 1177 #elif defined(CONFIG_SDIO_HCI) 1178 u32 tx_buf_size; 1179 u32 tx_buf_num; 1180 u32 tx_mgnt_buf_size; 1181 u32 tx_mgnt_buf_num; 1182 u32 rx_buf_size; 1183 u32 rx_buf_num; 1184 #else 1185 u8 temp_for_struct_empty; /* for undefined interface */ 1186 #endif 1187 }; 1188 struct bus_cap_t { 1189 #ifdef CONFIG_PCI_HCI 1190 enum rtw_pcie_bus_func_cap_t l0s_ctrl; 1191 enum rtw_pcie_bus_func_cap_t l1_ctrl; 1192 enum rtw_pcie_bus_func_cap_t l1ss_ctrl; 1193 enum rtw_pcie_bus_func_cap_t wake_ctrl; 1194 enum rtw_pcie_bus_func_cap_t crq_ctrl; 1195 u32 txbd_num; 1196 u32 rxbd_num; 1197 u32 rpbd_num; 1198 u32 rxbuf_num; 1199 u32 rpbuf_num; 1200 u32 read_txbd_th; 1201 u8 clkdly_ctrl; 1202 u8 l0sdly_ctrl; 1203 u8 l1dly_ctrl; 1204 struct rtw_pcie_ltr_lat_ctrl ltr_act; 1205 struct rtw_pcie_ltr_lat_ctrl ltr_idle; 1206 u8 ltr_init_state; 1207 u8 ltr_sw_ctrl; 1208 u8 ltr_hw_ctrl; 1209 #ifdef RTW_WKARD_GET_PROCESSOR_ID 1210 u64 proc_id; /* processor id */ 1211 #endif 1212 #elif defined (CONFIG_USB_HCI) 1213 u32 tx_buf_size; 1214 u32 tx_buf_num; 1215 u32 tx_mgnt_buf_size; 1216 u32 tx_mgnt_buf_num; 1217 u32 tx_h2c_buf_num; 1218 u32 rx_buf_size; 1219 u32 rx_buf_num; 1220 u32 in_token_num; 1221 #elif defined(CONFIG_SDIO_HCI) 1222 u32 tx_buf_size; 1223 u32 tx_buf_num; 1224 u32 tx_mgnt_buf_size; 1225 u32 tx_mgnt_buf_num; 1226 u32 rx_buf_size; 1227 u32 rx_buf_num; 1228 #else 1229 u8 temp_for_struct_empty; /* for undefined interface */ 1230 #endif 1231 }; 1232 1233 #ifdef CONFIG_PHL_TWT 1234 1235 #define DELETE_ALL 0xFF 1236 #define IGNORE_CFG_ID 0xFF 1237 #define IGNORE_MACID 0xFF 1238 1239 enum rtw_phl_twt_sup_cap { 1240 RTW_PHL_TWT_REQ_SUP = BIT(0), /* REQUESTER */ 1241 RTW_PHL_TWT_RSP_SUP = BIT(1)/* RESPONDER */ 1242 }; 1243 1244 enum rtw_phl_nego_type { 1245 RTW_PHL_INDIV_TWT = 0, /*individual TWT*/ 1246 RTW_PHL_WAKE_TBTT_INR = 1, /*wake TBTT and wake interval*/ 1247 RTW_PHL_BCAST_TWT = 2, /*Broadcast TWT*/ 1248 RTW_PHL_MANAGE_BCAST_TWT = 3 /*Manage memberships in broadcast TWT schedules*/ 1249 }; 1250 1251 enum rtw_phl_wake_dur_unit{ /*wake duration unit*/ 1252 RTW_PHL_WAKE_256US = 0, 1253 RTW_PHL_WAKE_1TU = 1 1254 }; 1255 1256 enum rtw_phl_setup_cmd{ 1257 RTW_PHL_REQUEST_TWT = 0, 1258 RTW_PHL_SUGGEST_TWT = 1, 1259 RTW_PHL_DEMAND_TWT = 2, 1260 RTW_PHL_TWT_GROUPING = 3, 1261 RTW_PHL_ACCEPT_TWT = 4, 1262 RTW_PHL_ALTERNATE_TWT = 5, 1263 RTW_PHL_DICTATE_TWT = 6, 1264 RTW_PHL_REJECT_TWT = 7 1265 }; 1266 1267 enum rtw_phl_flow_type{ 1268 RTW_PHL_ANNOUNCED_TWT = 0, 1269 RTW_PHL_UNANNOUNCED_TWT = 1 1270 }; 1271 1272 enum rtw_phl_twt_sta_action { 1273 TWT_STA_NONE = 0, 1274 TWT_STA_ADD_MACID = 1, 1275 TWT_STA_DEL_MACID = 2, 1276 TWT_STA_TETMINATW_SP = 3, 1277 TWT_STA_SUSPEND_TWT = 4, 1278 TWT_STA_RESUME_TWT = 5 1279 }; 1280 1281 enum rtw_phl_twt_cfg_action { 1282 TWT_CFG_ADD = 0, 1283 TWT_CFG_DELETE = 1, 1284 TWT_CFG_MODIFY = 2 1285 }; 1286 1287 struct rtw_phl_twt_flow_type01 { 1288 u8 twt_flow_id; 1289 u8 teardown_all; 1290 }; 1291 1292 struct rtw_phl_twt_flow_type2 { 1293 u8 reserved; 1294 }; 1295 1296 struct rtw_phl_twt_flow_type3 { 1297 u8 bcast_twt_id; 1298 u8 teardown_all; 1299 }; 1300 1301 struct rtw_phl_twt_flow_field{ 1302 enum rtw_phl_nego_type nego_type; 1303 union { 1304 struct rtw_phl_twt_flow_type01 twt_flow01; 1305 struct rtw_phl_twt_flow_type2 twt_flow2; 1306 struct rtw_phl_twt_flow_type3 twt_flow3; 1307 } info; 1308 }; 1309 1310 /*phl_twt_setup_info Start*/ 1311 1312 /*Broadcast TWT Parameter Set field*/ 1313 struct rtw_phl_bcast_twt_para_set{ 1314 u8 reserved; /*todo*/ 1315 }; 1316 1317 /*Individual TWT Parameter Set field*/ 1318 struct rtw_phl_twt_group_asgmt{ 1319 u8 reserved; /*todo*/ 1320 }; 1321 1322 struct rtw_phl_req_type_indiv{ 1323 enum rtw_phl_setup_cmd twt_setup_cmd; /*twt setup command*/ 1324 enum rtw_phl_flow_type flow_type; 1325 u8 twt_request; 1326 u8 trigger; 1327 u8 implicit; 1328 u8 twt_flow_id; 1329 u8 twt_wake_int_exp;/*twt wake interval exponent*/ 1330 u8 twt_protection; 1331 }; 1332 1333 struct rtw_phl_indiv_twt_para_set{ 1334 struct rtw_phl_req_type_indiv req_type; 1335 struct rtw_phl_twt_group_asgmt twt_group_asgmt; /* twt group assignment*/ 1336 u32 target_wake_t_h; /* if contain twt_group_assignment then don't contain target_wake_time*/ 1337 u32 target_wake_t_l; 1338 u16 twt_wake_int_mantissa; /*twt wake interval mantissa*/ 1339 u8 nom_min_twt_wake_dur; /*nominal minimum twt wake duration*/ 1340 u8 twt_channel; 1341 }; 1342 1343 struct rtw_phl_twt_control{ 1344 enum rtw_phl_nego_type nego_type; /*negotiation type*/ 1345 enum rtw_phl_wake_dur_unit wake_dur_unit; /*wake duration unit*/ 1346 u8 ndp_paging_indic; /*ndp paging indicator*/ 1347 u8 responder_pm_mode; 1348 u8 twt_info_frame_disable; /*twt information frame disable*/ 1349 }; 1350 struct rtw_phl_twt_element{ 1351 /* element info*/ 1352 /*control filed*/ 1353 struct rtw_phl_twt_control twt_ctrl; 1354 /*twt para info*/ 1355 union { 1356 struct rtw_phl_indiv_twt_para_set i_twt_para_set; 1357 struct rtw_phl_bcast_twt_para_set b_twt_para_set; 1358 } info; 1359 }; 1360 1361 struct rtw_phl_twt_setup_info{ 1362 struct rtw_phl_twt_element twt_element; 1363 //struct rtw_phl_stainfo_t *phl_sta; //sta entry 1364 u8 dialog_token; 1365 }; 1366 /*phl_twt_setup_info End*/ 1367 1368 1369 /*phl_twt_info Start*/ 1370 struct rtw_twt_sta_info{ 1371 _os_list list; 1372 struct rtw_phl_stainfo_t *phl_sta; /*sta entry*/ 1373 u8 id; /*twt_flow_identifier or broadcast_twt_id*/ 1374 }; 1375 1376 struct rtw_phl_twt_info{ 1377 enum rtw_phl_wake_dur_unit wake_dur_unit; 1378 enum rtw_phl_nego_type nego_type; 1379 enum rtw_phl_flow_type flow_type; 1380 u8 twt_id; /*config id*/ 1381 u8 bcast_twt_id; /*ignore in individual TWT*/ 1382 u8 twt_action; 1383 u8 responder_pm_mode; 1384 u8 trigger; 1385 u8 implicit_lastbcast; /*implicit or lastbroadcast*/ 1386 u8 twt_protection; 1387 u8 twt_wake_int_exp; 1388 u8 nom_min_twt_wake_dur; 1389 u16 twt_wake_int_mantissa; 1390 u32 target_wake_time_h; 1391 u32 target_wake_time_l; 1392 }; 1393 1394 1395 #endif /* CONFIG_PHL_TWT */ 1396 1397 1398 enum rtw_lps_listen_bcn_mode { 1399 RTW_LPS_RLBM_MIN = 0, 1400 RTW_LPS_RLBM_MAX = 1, 1401 RTW_LPS_RLBM_USERDEFINE = 2, 1402 RTW_LPS_LISTEN_BCN_MAX, 1403 }; 1404 1405 enum rtw_lps_smart_ps_mode { 1406 RTW_LPS_LEGACY_PWR1 = 0, 1407 RTW_LPS_TRX_PWR0 = 1, 1408 RTW_LPS_SMART_PS_MAX, 1409 }; 1410 1411 struct rtw_wow_cap_t { 1412 u8 magic_sup; 1413 u8 pattern_sup; 1414 u8 ping_pattern_wake_sup; 1415 u8 arp_ofld_sup; 1416 u8 ns_oflod_sup; 1417 u8 gtk_ofld_sup; 1418 u8 nlo_sup; 1419 }; 1420 1421 /** 1422 * enum phl_ps_leave_fail_act decide the action when leave ps fail 1423 * BIT 0 : reject all subsequent power request 1424 * BIT 1 : trigger L2 reset 1425 */ 1426 enum phl_ps_leave_fail_act { 1427 PS_LEAVE_FAIL_ACT_REJ_PWR = BIT0, 1428 PS_LEAVE_FAIL_ACT_L2 = BIT1 1429 }; 1430 #define PS_LEAVE_FAIL_ACT_NONE 0 1431 1432 enum phl_ps_operation_mode { 1433 PS_OP_MODE_DISABLED = 0, 1434 PS_OP_MODE_FORCE_ENABLED = 1, 1435 PS_OP_MODE_AUTO = 2 1436 }; 1437 1438 enum phl_ps_pwr_lvl { 1439 PS_PWR_LVL_PWROFF = 0, /* hal deinit */ 1440 PS_PWR_LVL_PWR_GATED = 1, /* FW control*/ 1441 PS_PWR_LVL_CLK_GATED = 2, /* FW control*/ 1442 PS_PWR_LVL_RF_OFF = 3, /* FW control*/ 1443 PS_PWR_LVL_PWRON = 4, /* hal init */ 1444 PS_PWR_LVL_MAX 1445 }; 1446 1447 /** 1448 * enum phl_stop_rson record the reason to stop power saving 1449 * BIT 0 : by core initialization setting 1450 * BIT 1 : by debug flow setting 1451 * BIT 2 : by battery change 1452 */ 1453 enum phl_ps_rt_rson { 1454 PS_RT_DEBUG = BIT0, 1455 PS_RT_CORE_INIT = BIT1, 1456 PS_RT_BATTERY_CHG = BIT2, 1457 }; 1458 #define PS_RT_RSON_NONE 0 1459 1460 #define PS_CAP_PWRON BIT0 1461 #define PS_CAP_RF_OFF BIT1 1462 #define PS_CAP_CLK_GATED BIT2 1463 #define PS_CAP_PWR_GATED BIT3 1464 #define PS_CAP_PWR_OFF BIT4 1465 1466 /** 1467 * ips_en/lps_en 1468 * refs. structure "phl_ps_operation_mode" 1469 * 0: disable -> disable all ps mechanism 1470 * 1: force enable -> ignore all other condition, force enter ps 1471 * 2: auto -> will be affected by runtime capability set by core 1472 * 1473 * ips_cap/ips_wow_cap/lps_cap/lps_wow_cap are bit defined 1474 * corresponding bit is set if specific power level is supported 1475 * BIT0: Power on 1476 * BIT1: Rf off 1477 * BIT2: Clock gating 1478 * BIT3: Power gating 1479 * BIT4: Power off 1480 */ 1481 struct rtw_ps_cap_t { 1482 /* rf state */ 1483 enum rtw_rf_state init_rf_state; 1484 u8 init_rt_stop_rson; 1485 u8 leave_fail_act; /* action when leave ps fail */ 1486 /* ips */ 1487 u8 ips_en; 1488 u8 ips_cap; 1489 u8 ips_wow_en; 1490 u8 ips_wow_cap; 1491 /* lps */ 1492 u8 lps_en; 1493 u8 lps_cap; 1494 u8 lps_awake_interval; 1495 enum rtw_lps_listen_bcn_mode lps_listen_bcn_mode; 1496 enum rtw_lps_smart_ps_mode lps_smart_ps_mode; 1497 u8 lps_rssi_enter_threshold; 1498 u8 lps_rssi_leave_threshold; 1499 u8 lps_rssi_diff_threshold; 1500 bool lps_pause_tx; 1501 /* wow lps */ 1502 u8 lps_wow_en; 1503 u8 lps_wow_cap; 1504 u8 lps_wow_awake_interval; 1505 enum rtw_lps_listen_bcn_mode lps_wow_listen_bcn_mode; 1506 enum rtw_lps_smart_ps_mode lps_wow_smart_ps_mode; 1507 }; 1508 1509 struct rtw_edcca_cap_t { 1510 u8 edcca_adap_th_2g; 1511 u8 edcca_adap_th_5g; 1512 1513 u8 edcca_carrier_sense_th; 1514 }; 1515 1516 struct phy_sw_cap_t { 1517 struct rtw_para_info_t mac_reg_info; 1518 struct rtw_para_info_t bb_phy_reg_info; 1519 struct rtw_para_info_t bb_phy_reg_mp_info; 1520 struct rtw_para_info_t bb_phy_reg_gain_info; 1521 1522 struct rtw_para_info_t rf_radio_a_info; 1523 struct rtw_para_info_t rf_radio_b_info; 1524 struct rtw_para_info_t rf_txpwr_byrate_info; 1525 struct rtw_para_info_t rf_txpwrtrack_info; 1526 1527 struct rtw_para_pwrlmt_info_t rf_txpwrlmt_info; 1528 struct rtw_para_pwrlmt_info_t rf_txpwrlmt_ru_info; 1529 1530 u8 proto_sup; 1531 u8 band_sup; 1532 u8 bw_sup; 1533 u8 txss; 1534 u8 rxss; 1535 u16 hw_rts_time_th; 1536 u16 hw_rts_len_th; 1537 bool bfreed_para; 1538 }; 1539 1540 /* final capability of phy */ 1541 struct phy_cap_t { 1542 u8 proto_sup; 1543 u8 band_sup; 1544 u8 bw_sup; 1545 u8 txss; 1546 u8 rxss; 1547 u16 hw_rts_time_th; 1548 u16 hw_rts_len_th; 1549 }; 1550 1551 /* final capability of device */ 1552 struct dev_cap_t { 1553 u64 hw_sup_flags;/*hw's feature support flags*/ 1554 #ifdef RTW_WKARD_LAMODE 1555 bool la_mode; 1556 #endif 1557 u8 pkg_type; 1558 u8 rfe_type; 1559 u8 bypass_rfe_chk; 1560 u8 xcap; 1561 struct rtw_fw_cap_t fw_cap; 1562 #ifdef CONFIG_MCC_SUPPORT 1563 bool mcc_sup; 1564 #endif 1565 #ifdef CONFIG_DBCC_SUPPORT 1566 bool dbcc_sup; 1567 #endif 1568 #ifdef CONFIG_PHL_TWT 1569 u8 twt_sup; 1570 #endif /* CONFIG_PHL_TWT */ 1571 1572 struct rtw_wow_cap_t wow_cap; 1573 struct rtw_ps_cap_t ps_cap; 1574 u8 hw_hdr_conv; 1575 u8 domain; 1576 u8 btc_mode; 1577 u8 ap_ps; /* support for AP mode PS in PHL */ 1578 u8 pwrbyrate_off; 1579 u8 pwrlmt_type; 1580 u8 rf_board_opt; 1581 u8 sta_ulru; /* support UL OFDAM for STA mode (reply trigger frame) */ 1582 #ifdef RTW_WKARD_BB_DISABLE_STA_2G40M_ULOFDMA 1583 u8 sta_ulru_2g40mhz; /* when "sta_ulru" is enabled, support UL OFDAM on 2.4G 40MHz ? */ 1584 #endif 1585 u8 tx_mu_ru; 1586 struct rtw_edcca_cap_t edcca_cap; 1587 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE 1588 bool bfree_para_info; /* keep load file para info buf,default 0*/ 1589 #endif 1590 u8 hw_stype_cap; 1591 u8 wl_func_cap; 1592 u8 rpq_agg_num; /* 0: no adjust, use mac default size: 121 */ 1593 bool quota_turbo; 1594 }; 1595 1596 #ifdef RTW_PHL_BCN //phl def 1597 1598 #define BCN_ID_MAX (0xFF) 1599 #define MAX_BCN_SIZE 1000 1600 1601 enum bcn_offload_flags{ 1602 BCN_HW_SEQ = 0, 1603 BCN_HW_TIM, 1604 1605 BCN_HW_MAX = 32, 1606 }; 1607 1608 struct rtw_bcn_info_cmn { 1609 u8 role_idx; 1610 u8 bcn_id; 1611 u8 bcn_added; 1612 1613 u8 bssid[6]; 1614 u32 bcn_interval; 1615 1616 u8 bcn_buf[MAX_BCN_SIZE]; 1617 u32 bcn_length; 1618 u32 bcn_rate; 1619 1620 u32 bcn_dtim; 1621 u32 ie_offset_tim; 1622 1623 u32 bcn_offload; 1624 }; 1625 1626 struct rtw_bcn_info_hw { 1627 u8 band; 1628 u8 port; 1629 u8 mbssid; 1630 u8 mac_id; 1631 }; 1632 1633 struct rtw_bcn_entry { 1634 _os_list list; 1635 struct rtw_bcn_info_cmn *bcn_cmn; //fill by core 1636 struct rtw_bcn_info_hw bcn_hw; //fill by phl //?? void mapping ?? for 8852, 8834 ...blabla 1637 }; 1638 #endif 1639 1640 struct rtw_phl_com_t; 1641 1642 struct phl_msg_receiver { 1643 void* priv; 1644 void (*incoming_evt_notify)(void* priv, struct phl_msg *msg); 1645 }; 1646 1647 #ifdef CONFIG_PHL_P2PPS 1648 1649 #define MAX_NOA_DESC 5 1650 #define NOAID_NONE 0xFF 1651 1652 enum p2pps_trig_tag { 1653 P2PPS_TRIG_GO = 0, 1654 P2PPS_TRIG_GC = 1, 1655 P2PPS_TRIG_GC_255 = 2, 1656 P2PPS_TRIG_MCC = 3, 1657 P2PPS_TRIG_2G_SCC_1AP_1STA_BT = 4, 1658 P2PPS_TRIG_MAX = MAX_NOA_DESC 1659 }; 1660 1661 struct rtw_phl_noa_desc { 1662 u8 enable; /*false=disable, true=enable*/ 1663 struct rtw_wifi_role_t *w_role; 1664 enum p2pps_trig_tag tag; 1665 u32 start_t_h; 1666 u32 start_t_l; 1667 u32 interval; 1668 u32 duration; 1669 u8 count; 1670 u8 noa_id; /*filed by phl noa module*/ 1671 }; 1672 1673 struct rtw_phl_opps_desc { 1674 u16 ctw; 1675 u8 all_slep; 1676 }; 1677 1678 struct rtw_phl_tsf32_tog_rpt{ 1679 u8 band; 1680 u8 port; 1681 u8 valid; 1682 u16 early; 1683 u16 status; 1684 u32 tsf_l; 1685 u32 tsf_h; 1686 }; 1687 1688 struct rtw_phl_p2pps_ops { 1689 void *priv; /* ops private, define by core layer*/ 1690 void (*tsf32_tog_update_noa)(void *priv, struct rtw_wifi_role_t *w_role, 1691 struct rtw_phl_tsf32_tog_rpt *rpt); 1692 void (*tsf32_tog_update_single_noa)(void *priv, 1693 struct rtw_wifi_role_t *w_role, 1694 struct rtw_phl_noa_desc *desc); 1695 }; 1696 1697 1698 #endif 1699 1700 struct rtw_wifi_role_t { 1701 struct rtw_phl_com_t *phl_com;/*point to phl_com*/ 1702 #ifdef RTW_WKARD_ROLE_TYPE 1703 enum role_type real_type; 1704 #endif /* RTW_WKARD_ROLE_TYPE */ 1705 enum role_type type;/*will mapping to net type*/ 1706 enum role_type target_type; 1707 #ifdef RTW_WKARD_PHL_NTFY_MEDIA_STS 1708 bool is_gc; 1709 #endif 1710 enum mlme_state mstate; 1711 bool active; 1712 enum wr_status status; 1713 u8 id;/* recode role_idx in phl_com */ 1714 u8 hw_wmm; /*HW EDCA - wmm0 or wmm1*/ 1715 #ifdef RTW_WKARD_HW_WMM_ALLOCATE 1716 _os_atomic hw_wmm0_ref_cnt; 1717 #endif 1718 u8 mac_addr[MAC_ALEN]; 1719 u8 hw_band; /*MAC Band0 or Band1*/ 1720 u8 hw_port; /*MAC HW Port*/ 1721 /* 1722 * final protocol capability of role from intersection of 1723 * sw role cap, sw protocol cap and hw protocol cap 1724 */ 1725 struct protocol_cap_t proto_role_cap; 1726 1727 /* 1728 * final capability of role from intersection of 1729 * sw role cap, final phy cap and final dev cap 1730 */ 1731 struct role_cap_t cap; 1732 1733 /*#ifdef CONFIG_AP*/ 1734 #ifdef RTW_PHL_BCN 1735 struct rtw_bcn_info_cmn bcn_cmn; //todo: ieee mbssid case & multi-bcn (in one iface) case 1736 u8 hw_mbssid; 1737 #endif 1738 u8 dtim_period; 1739 u8 mbid_num; 1740 u32 hiq_win; 1741 /*#endif CONFIG_AP*/ 1742 1743 struct rtw_chan_def chandef; 1744 struct rtw_chan_ctx *chanctx;/*point to chanctx*/ 1745 1746 struct phl_queue assoc_sta_queue; 1747 1748 #ifdef CONFIG_PHL_TWT 1749 struct rtw_phl_twt_setup_info twt_setup_info; 1750 #endif /* CONFIG_PHL_TWT */ 1751 1752 #ifdef CONFIG_PHL_P2PPS 1753 struct rtw_phl_noa_desc noa_desc[MAX_NOA_DESC]; 1754 #endif 1755 1756 void *core_data; /* Track back to counter part in core layer */ 1757 #ifdef RTW_WKARD_BFEE_SET_AID 1758 u16 last_set_aid; 1759 #endif 1760 }; 1761 1762 #define TXTP_CALC_DIFF_MS 1000 1763 #define RXTP_CALC_DIFF_MS 1000 1764 1765 #define TX_ULTRA_LOW_TP_THRES_KBPS 100 1766 #define RX_ULTRA_LOW_TP_THRES_KBPS 100 1767 #define TX_LOW_TP_THRES_MBPS 2 1768 #define RX_LOW_TP_THRES_MBPS 2 1769 #define TX_MID_TP_THRES_MBPS 10 1770 #define RX_MID_TP_THRES_MBPS 10 1771 #define TX_HIGH_TP_THRES_MBPS 50 1772 #define RX_HIGH_TP_THRES_MBPS 50 1773 1774 1775 enum rtw_tfc_lvl { 1776 RTW_TFC_IDLE = 0, 1777 RTW_TFC_ULTRA_LOW = 1, 1778 RTW_TFC_LOW = 2, 1779 RTW_TFC_MID = 3, 1780 RTW_TFC_HIGH = 4, 1781 RTW_TFC_LVL_MAX = 0xFF 1782 }; 1783 1784 enum rtw_tfc_sts { 1785 TRAFFIC_CHANGED = BIT0, 1786 TRAFFIC_INCREASE = BIT1, 1787 TRAFFIC_DECREASE = BIT2, 1788 TRAFFIC_STS_MAX = BIT7 1789 }; 1790 1791 struct rtw_traffic_t { 1792 enum rtw_tfc_lvl lvl; 1793 enum rtw_tfc_sts sts; 1794 }; 1795 1796 struct rtw_stats_tp { 1797 u64 last_calc_bits; 1798 u32 last_calc_time_ms; 1799 }; 1800 /*statistic*/ 1801 struct rtw_stats { 1802 u64 tx_byte_uni;/*unicast tx byte*/ 1803 u64 rx_byte_uni;/*unicast rx byte*/ 1804 u64 tx_byte_total; 1805 u64 rx_byte_total; 1806 u32 tx_tp_kbits; 1807 u32 rx_tp_kbits; 1808 u16 tx_moving_average_tp; /* tx average MBps*/ 1809 u16 rx_moving_average_tp; /* rx average MBps*/ 1810 u32 last_tx_time_ms; 1811 u32 last_rx_time_ms; 1812 u32 txreq_num; 1813 u32 rx_rate; 1814 u32 rx_rate_nmr[RTW_DATA_RATE_HE_NSS4_MCS11 +1]; 1815 u64 ser_event[8]; /* RTW_PHL_SER_MAX */ 1816 struct rtw_stats_tp txtp; 1817 struct rtw_stats_tp rxtp; 1818 struct rtw_traffic_t tx_traffic; 1819 struct rtw_traffic_t rx_traffic; 1820 u32 rx_tf_cnt; /* rx trigger frame number (accumulated, only reset in disconnect) */ 1821 u32 pre_rx_tf_cnt; /* last record rx trigger frame number from BB */ 1822 }; 1823 enum sta_chg_id { 1824 STA_CHG_BW, 1825 STA_CHG_NSS, 1826 STA_CHG_RAMASK, 1827 STA_CHG_SEC_MODE, 1828 STA_CHG_MBSSID, 1829 STA_CHG_RA_GILTF, 1830 STA_CHG_MAX 1831 }; 1832 1833 enum phl_upd_mode { 1834 PHL_UPD_ROLE_CREATE, 1835 PHL_UPD_ROLE_REMOVE, 1836 PHL_UPD_ROLE_TYPE_CHANGE, 1837 PHL_UPD_ROLE_INFO_CHANGE, 1838 PHL_UPD_STA_INFO_CHANGE, 1839 PHL_UPD_STA_CON_DISCONN, 1840 PHL_UPD_ROLE_MAX 1841 }; 1842 1843 #ifdef CONFIG_PHL_TXSC 1844 #define PHL_TXSC_ENTRY_NUM 8 1845 #define MAX_WD_SIZE 128 1846 1847 struct phl_txsc_entry { 1848 bool txsc_wd_cached; 1849 u8 txsc_wd_cache[MAX_WD_SIZE]; 1850 u8 txsc_wd_len; 1851 u32 txsc_cache_hit; 1852 }; 1853 #endif 1854 1855 struct rtw_hal_stainfo_t; 1856 struct rtw_phl_stainfo_t { 1857 _os_list list; 1858 struct rtw_wifi_role_t *wrole; 1859 #ifdef RTW_WKARD_CHECK_STAINFO_DOUBLE_DEL 1860 bool allocated; 1861 #endif 1862 bool active; 1863 u16 aid; 1864 u16 macid; 1865 u8 mac_addr[MAC_ALEN]; 1866 1867 struct rtw_chan_def chandef; 1868 struct rtw_stats stats; 1869 enum wlan_mode wmode; 1870 1871 /*mlme protocol or MAC related CAP*/ 1872 u8 bcn_hit_cond; 1873 u8 hit_rule; 1874 u8 tf_trs; 1875 u8 tgt_ind; 1876 u8 frm_tgt_ind; 1877 u8 addr_sel; 1878 u8 addr_msk; 1879 1880 /* rx agg */ 1881 struct phl_tid_ampdu_rx *tid_rx[RTW_MAX_TID_NUM]; /* TID_MAX_NUM */ 1882 _os_lock tid_rx_lock; /* guarding @tid_rx */ 1883 _os_event comp_sync; /* reorder timer completion event */ 1884 _os_timer reorder_timer; /* reorder timer for all @tid_rx of the 1885 * stainfo */ 1886 /* TODO: add missing part */ 1887 1888 /*mlme protocol or PHY related CAP*/ 1889 struct protocol_cap_t asoc_cap; 1890 enum rtw_protect_mode protect; 1891 1892 /*security related*/ 1893 u8 wapi; 1894 u8 sec_mode; 1895 1896 /* 1897 * STA powersave, those could be implemented as bit flags but there's no 1898 * corresponding atomic bit operations available on Windows. 1899 */ 1900 _os_atomic ps_sta; /* the sta is in PS mode or not */ 1901 1902 struct rtw_hal_stainfo_t *hal_sta; 1903 1904 #ifdef CONFIG_PHL_TXSC 1905 struct phl_txsc_entry phl_txsc[PHL_TXSC_ENTRY_NUM]; 1906 #endif 1907 struct rtw_rx_bcn_info bcn_i; 1908 void *core_data; /* Track back to counter part in core layer */ 1909 }; 1910 1911 1912 1913 1914 #define WL_FUNC_P2P BIT0 1915 #define WL_FUNC_MIRACAST BIT1 1916 #define WL_FUNC_TDLS BIT2 1917 #define WL_FUNC_FTM BIT3 1918 #define WL_FUNC_BIT_NUM 4 1919 1920 1921 /* HW MAC capability*/ 1922 #define HW_SUP_DBCC BIT0 1923 #define HW_SUP_AMSDU BIT1 1924 #define HW_SUP_TCP_TX_CHKSUM BIT2 1925 #define HW_SUP_TCP_RX_CHKSUM BIT3 1926 #define HW_SUP_TXPKT_CONVR BIT4 1927 #define HW_SUP_RXPKT_CONVR BIT5 1928 #define HW_SUP_MULTI_BSSID BIT6 1929 #define HW_SUP_OFDMA BIT7 1930 #define HW_SUP_CHAN_INFO BIT8 1931 #define HW_SUP_TSSI BIT9 1932 #define HW_SUP_TANK_K BIT10 1933 1934 /*BUS Section CAP */ 1935 #define HW_SUP_PCIE_PLFH BIT20 /*payload from host*/ 1936 #define HW_SUP_USB_MULTI_FUN BIT21 1937 #define HW_SUP_SDIO_MULTI_FUN BIT22 1938 1939 /* Beamform CAP */ 1940 #define HW_CAP_BF_NON_SUPPORT 0 1941 #define HW_CAP_BFEE_HT_SU BIT(0) 1942 #define HW_CAP_BFER_HT_SU BIT(1) 1943 #define HW_CAP_BFEE_VHT_SU BIT(2) 1944 #define HW_CAP_BFER_VHT_SU BIT(3) 1945 #define HW_CAP_BFEE_VHT_MU BIT(4) 1946 #define HW_CAP_BFER_VHT_MU BIT(5) 1947 #define HW_CAP_BFEE_HE_SU BIT(6) 1948 #define HW_CAP_BFER_HE_SU BIT(7) 1949 #define HW_CAP_BFEE_HE_MU BIT(8) 1950 #define HW_CAP_BFER_HE_MU BIT(9) 1951 #define HW_CAP_HE_NON_TB_CQI BIT(10) 1952 #define HW_CAP_HE_TB_CQI BIT(11) 1953 1954 #define RTW_HW_CAP_ULRU_AUTO 0 1955 #define RTW_HW_CAP_ULRU_DISABLE 1 1956 #define RTW_HW_CAP_ULRU_ENABLE 2 1957 1958 /* STBC CAP */ 1959 #define HW_CAP_STBC_HT_TX BIT(0) 1960 #define HW_CAP_STBC_VHT_TX BIT(1) 1961 #define HW_CAP_STBC_HE_TX BIT(2) 1962 #define HW_CAP_STBC_HE_TX_GT_80M BIT(3) 1963 #define HW_CAP_STBC_HT_RX BIT(4) 1964 #define HW_CAP_STBC_VHT_RX BIT(5) 1965 #define HW_CAP_STBC_HE_RX BIT(6) 1966 #define HW_CAP_STBC_HE_RX_GT_80M BIT(7) 1967 1968 struct hal_spec_t { 1969 char *ic_name; 1970 u16 macid_num; 1971 1972 u8 sec_cam_ent_num; 1973 u8 sec_cap; 1974 u8 wow_cap; 1975 1976 u8 rfpath_num_2g:4; /* used for tx power index path */ 1977 u8 rfpath_num_5g:4; /* used for tx power index path */ 1978 u8 rf_reg_path_num; 1979 u8 max_tx_cnt; 1980 1981 u8 band_cap; /* value of BAND_CAP_XXX */ 1982 u8 bw_cap; /* value of BW_CAP_XXX */ 1983 u8 port_num; 1984 u8 wmm_num; 1985 u8 proto_cap; /* value of PROTO_CAP_XXX */ 1986 u8 wl_func; /* value of WL_FUNC_XXX */ 1987 1988 /********* xmit ************/ 1989 1990 1991 /********* recv ************/ 1992 u8 rx_bd_info_sz; 1993 1994 u16 rx_tag[2]; 1995 #ifdef CONFIG_USB_HCI 1996 u8 max_bulkin_num; 1997 u8 max_bulkout_num; 1998 #endif 1999 #ifdef CONFIG_PCI_HCI 2000 u16 txbd_multi_tag; 2001 u8 txbd_upd_lmt; 2002 #ifdef RTW_WKARD_BUSCAP_IN_HALSPEC 2003 u8 phyaddr_num; 2004 #endif 2005 #endif 2006 u8 cts2_thres_en; 2007 u16 cts2_thres; 2008 /********* beamformer ************/ 2009 u8 max_csi_buf_su_nr; 2010 u8 max_csi_buf_mu_nr; 2011 u8 max_bf_ent_nr; 2012 u8 max_su_sta_nr; 2013 u8 max_mu_sta_nr; 2014 2015 }; 2016 2017 #define phl_get_hci_type(_phlcom) (_phlcom->hci_type) 2018 #define phl_get_ic_spec(_phlcom) (&_phlcom->hal_spec) 2019 #define phl_get_fw_buf(_phlcom) (_phlcom->fw_info.ram_buff) 2020 #define phl_get_fw_size(_phlcom) (_phlcom->fw_info.ram_size) 2021 2022 enum rtw_drv_mode { 2023 RTW_DRV_MODE_NORMAL = 0, 2024 RTW_DRV_MODE_EQC = 1, 2025 RTW_DRV_MODE_HIGH_THERMAL = 2, 2026 2027 /* 11~20 for MP submodule section*/ 2028 RTW_DRV_MODE_MP_SMDL_START = 11, 2029 RTW_DRV_MODE_MP = 11, 2030 RTW_DRV_MODE_HOMOLOGATION = 12, 2031 RTW_DRV_MODE_MP_SMDL_END = 20, 2032 2033 /* 21~30 for FPGA submodule section*/ 2034 RTW_DRV_MODE_FPGA_SMDL_START = 21, 2035 RTW_DRV_MODE_FPGA_SMDL_END = 30, 2036 2037 /* 31~60 for VERIFY submodule section*/ 2038 RTW_DRV_MODE_VERIFY_SMDL_START = 31, 2039 RTW_DRV_MODE_VERIFY_SMDL_END = 60, 2040 2041 /* 61~80 for TOOL submodule section*/ 2042 RTW_DRV_MODE_TOOL_SMDL_START = 61, 2043 RTW_DRV_MODE_TOOL_SMDL_END = 80, 2044 2045 /* Fixed Max Value*/ 2046 RTW_DRV_MODE_MAX = 255 2047 }; 2048 2049 struct rtw_evt_info_t { 2050 _os_lock evt_lock; 2051 enum rtw_phl_evt evt_bitmap; 2052 }; 2053 2054 // WiFi FW 2055 struct rtw_fw_info_t { 2056 u8 fw_en; 2057 u8 fw_src; 2058 u8 fw_type; 2059 u8 dlram_en; 2060 u8 dlrom_en; 2061 u8 *rom_buff; 2062 u32 rom_addr; 2063 u32 rom_size; 2064 char rom_path[256]; 2065 u8 *ram_buff; 2066 u32 ram_size; 2067 char ram_path[256]; 2068 u8 *buf; 2069 u32 buf_size; 2070 u8 *wow_buf; 2071 u32 wow_buf_size; 2072 u8 *sym_buf; 2073 u32 sym_buf_size; 2074 }; 2075 2076 enum rtw_fw_status { 2077 RTW_FW_STATUS_OK, 2078 RTW_FW_STATUS_NOFW, 2079 RTW_FW_STATUS_ASSERT, 2080 RTW_FW_STATUS_EXCEP, 2081 RTW_FW_STATUS_RXI300, 2082 RTW_FW_STATUS_HANG 2083 }; 2084 2085 #ifdef CONFIG_PHL_DFS 2086 enum dfs_regd_t { 2087 DFS_REGD_UNKNOWN = 0, 2088 DFS_REGD_FCC = 1, 2089 DFS_REGD_JAP = 2, 2090 DFS_REGD_ETSI = 3, 2091 }; 2092 struct rtw_dfs_t { 2093 u8 region_domain; 2094 bool dfs_enabled; 2095 }; 2096 #endif 2097 2098 #ifdef CONFIG_PHL_CHANNEL_INFO 2099 2100 #define CHAN_INFO_MAX_SIZE 65535 2101 #define MAX_CHAN_INFO_PKT_KEEP 2 2102 #define CHAN_INFO_PKT_TOTAL MAX_CHAN_INFO_PKT_KEEP + 1 2103 2104 struct csi_header_t { 2105 u8 mac_addr[6]; /* mdata: u8 ta[6]? */ 2106 u32 hw_assigned_timestamp; /* mdata: u32 freerun_cnt */ 2107 u8 channel; /* Drv define */ 2108 u8 bandwidth; /* mdata: u8 bw */ 2109 u16 rx_data_rate; /* mdata: u16 rx_rate */ 2110 u8 nc; /* ch_rpt_hdr_info */ 2111 u8 nr; /* ch_rpt_hdr_info */ 2112 u16 num_sub_carrier; /* Drv define*/ 2113 u8 num_bit_per_tone; /* Drv define per I/Q */ 2114 u8 avg_idle_noise_pwr; /* ch_rpt_hdr_info */ 2115 u8 evm[2]; /* ch_rpt_hdr_info */ 2116 u8 rssi[2]; /* phy_info_rpt */ 2117 u32 csi_data_length; /* ch_rpt_hdr_info */ 2118 u8 rxsc; /* phy_info_rpt */ 2119 u8 ch_matrix_report; /* mdata: u8 get_ch_info */ 2120 u8 csi_valid; /* ch_rpt_hdr_info */ 2121 }; 2122 2123 struct chan_info_t { 2124 _os_list list; 2125 u8* chan_info_buffer; 2126 u32 length; 2127 struct csi_header_t csi_header; 2128 }; 2129 2130 struct rx_chan_info_pool { 2131 struct chan_info_t channl_info_pkt[CHAN_INFO_PKT_TOTAL]; 2132 _os_list idle; 2133 _os_list busy; 2134 _os_lock idle_lock; /* spinlock */ 2135 _os_lock busy_lock; /* spinlock */ 2136 u32 idle_cnt; 2137 u32 busy_cnt; 2138 }; 2139 2140 #endif /* CONFIG_PHL_CHANNEL_INFO */ 2141 2142 #ifdef CONFIG_MCC_SUPPORT 2143 #define BT_SEG_NUM 2 2144 #define SLOT_NUM 4 2145 #define MIN_TDMRA_SLOT_NUM 2 2146 #define NONSPECIFIC_SETTING 0xff 2147 2148 /*Export to core layer. Phl get the judgement of slot mode*/ 2149 enum rtw_phl_mcc_coex_mode { 2150 RTW_PHL_MCC_COEX_MODE_NONE = 0, 2151 RTW_PHL_MCC_COEX_MODE_BT_MASTER, 2152 RTW_PHL_MCC_COEX_MODE_WIFI_MASTER, 2153 RTW_PHL_MCC_COEX_MODE_BT_WIFI_BALANCE 2154 }; 2155 2156 enum rtw_phl_tdmra_wmode { 2157 RTW_PHL_TDMRA_WMODE_NONE = 0, 2158 RTW_PHL_TDMRA_AP_CLIENT_WMODE, 2159 RTW_PHL_TDMRA_2CLIENTS_WMODE, 2160 RTW_PHL_TDMRA_AP_WMODE, 2161 RTW_PHL_TDMRA_UNKNOWN_WMODE 2162 }; 2163 2164 enum rtw_phl_mcc_dbg_type { 2165 MCC_DBG_NONE = 0, 2166 MCC_DBG_STATE, 2167 MCC_DBG_OP_MODE, 2168 MCC_DBG_COEX_MODE, 2169 MCC_DBG_BT_INFO, 2170 MCC_DBG_EN_INFO 2171 }; 2172 2173 enum rtw_phl_mcc_state { 2174 MCC_NONE = 0, 2175 MCC_CFG_EN_INFO, 2176 MCC_TRIGGER_FW_EN, 2177 MCC_FW_EN_FAIL, 2178 MCC_RUNING, 2179 MCC_TRIGGER_FW_DIS, 2180 MCC_FW_DIS_FAIL, 2181 MCC_STOP 2182 }; 2183 2184 enum rtw_phl_mcc_dur_lim_tag { 2185 RTW_MCC_DUR_LIM_NONE = 0, 2186 RTW_MCC_DUR_LIM_NOA 2187 }; 2188 2189 /*Export to core layer and hal layyer. Phl get the c2h report mode and config to halmac*/ 2190 enum rtw_phl_mcc_rpt { 2191 RTW_MCC_RPT_OFF = 0, 2192 RTW_MCC_RPT_FAIL_ONLY, 2193 RTW_MCC_RPT_ALL 2194 }; 2195 2196 /*Export to core layer. Phl get switch ch setting of role from core layer*/ 2197 struct rtw_phl_mcc_setting_info { 2198 struct rtw_wifi_role_t *wrole; 2199 u8 role_map;/*the wifi role map in operating mcc */ 2200 u8 tx_null_early; 2201 u16 dur; /*core specific duration in a period of 100 ms */ 2202 bool en_fw_mcc_log; 2203 u8 fw_mcc_log_lv;/* fw mcc log level */ 2204 }; 2205 2206 /*Export to core layer. Core get NOA info to update p2p beacon*/ 2207 struct rtw_phl_mcc_noa { 2208 struct rtw_wifi_role_t *wrole; 2209 u32 start_t_h; 2210 u32 start_t_l; 2211 u16 dur; 2212 u16 interval; 2213 u8 cnt; 2214 }; 2215 2216 struct rtw_phl_mcc_ops { 2217 void *priv; /* ops private, define by core layer*/ 2218 int (*mcc_update_noa)(void *priv, struct rtw_phl_mcc_noa *param); 2219 int (*mcc_get_setting)(void *priv, struct rtw_phl_mcc_setting_info *param); 2220 }; 2221 2222 /* 2223 * Export to phl layer and hal layer. 2224 * Record the debug info. 2225 */ 2226 struct rtw_phl_mcc_dbg_slot_info { 2227 bool bt_role; 2228 u16 dur; 2229 u16 ch; 2230 u16 macid; 2231 }; 2232 2233 struct rtw_phl_mcc_dbg_hal_info { 2234 u8 slot_num; 2235 struct rtw_phl_mcc_dbg_slot_info dbg_slot_i[SLOT_NUM]; 2236 bool btc_in_group; 2237 }; 2238 2239 struct rtw_phl_mcc_macid_bitmap { 2240 u32 *bitmap; 2241 u8 len; 2242 }; 2243 2244 struct rtw_phl_mcc_sync_tsf_info { 2245 u8 sync_en; 2246 u16 source; 2247 u16 target; 2248 u16 offset; 2249 }; 2250 2251 struct rtw_phl_mcc_dur_lim_info { 2252 bool enable; 2253 enum rtw_phl_mcc_dur_lim_tag tag; 2254 u16 max_tob; 2255 u16 max_toa; 2256 u16 max_dur; 2257 }; 2258 2259 struct rtw_phl_mcc_dur_info { 2260 u16 dur; 2261 struct rtw_phl_mcc_dur_lim_info dur_limit; 2262 }; 2263 2264 struct rtw_phl_mcc_policy_info { 2265 u8 c2h_rpt; 2266 u8 tx_null_early; 2267 u8 dis_tx_null; 2268 u8 in_curr_ch; 2269 u8 dis_sw_retry; 2270 u8 sw_retry_count; 2271 struct rtw_phl_mcc_dur_info dur_info; 2272 u8 rfk_chk; 2273 u8 protect_bcn; 2274 u8 courtesy_en; 2275 u8 courtesy_num; 2276 u8 courtesy_target; 2277 }; 2278 2279 struct rtw_phl_mcc_role { 2280 struct rtw_wifi_role_t *wrole; 2281 struct rtw_phl_mcc_macid_bitmap used_macid; 2282 struct rtw_chan_def *chandef; 2283 struct rtw_phl_mcc_policy_info policy; 2284 u16 macid; 2285 u16 bcn_intvl; 2286 bool bt_role; 2287 u8 group; 2288 }; 2289 2290 /* 2291 * @c_en: Enable courtesy function 2292 * @c_num: the time slot of src_role replace by tgt_role 2293 */ 2294 struct rtw_phl_mcc_courtesy { 2295 bool c_en; 2296 bool c_num; 2297 struct rtw_phl_mcc_role *src_role; 2298 struct rtw_phl_mcc_role *tgt_role; 2299 }; 2300 2301 /* 2302 * @slot: duration, unit: TU 2303 * @bt_role: True: bt role, False: Wifi role 2304 * @mrole: mcc role info for Wifi Role 2305 */ 2306 struct rtw_phl_mcc_slot_info { 2307 u16 slot; 2308 bool bt_role; 2309 struct rtw_phl_mcc_role *mrole; 2310 }; 2311 2312 /* 2313 * @slot_num: total slot num(Wifi+BT) 2314 * @bt_slot_num: total BT slot num 2315 * | Dur1 | Dur2 | 2316 * bcn bcn 2317 * |tob_r | toa_r|tob_a | toa_a| 2318 */ 2319 struct rtw_phl_mcc_pattern { 2320 u8 slot_num; 2321 u8 bt_slot_num; 2322 struct rtw_phl_mcc_role *role_ref; 2323 struct rtw_phl_mcc_role *role_ano; 2324 s16 tob_r; 2325 s16 toa_r; 2326 s16 tob_a; 2327 s16 toa_a; 2328 u16 bcns_offset; 2329 2330 u16 calc_fail; 2331 /** 2332 * |tob_r|toa_r| 2333 * -----------<d_r_d_a_spacing>----------- 2334 * |tob_a|toa_a| 2335 **/ 2336 u16 d_r_d_a_spacing_max; 2337 struct rtw_phl_mcc_courtesy courtesy_i; 2338 /*record slot order for X wifi slot + Y bt slot*/ 2339 struct rtw_phl_mcc_slot_info slot_order[SLOT_NUM]; 2340 }; 2341 2342 /* 2343 * Enable info for mcc 2344 * @ref_role_idx: the index of reference role 2345 * @mrole_map: use mcc role num 2346 * @mrole_num: use mcc role num 2347 * @group: assigned by halmac mcc, the group resource of fw feture, phl layer ignore it 2348 * fw mcc can handle differenec slot pattern, and the group is the id of slot pattern. 2349 * @tsf_high, tsf_low: Start TSF 2350 * @tsf_high_l, tsf_low_l: Limitation of Start TSF 2351 * @dbg_hal_i: Debug info for hal mcc 2352 */ 2353 struct rtw_phl_mcc_en_info { 2354 struct rtw_phl_mcc_role mcc_role[MCC_ROLE_NUM]; 2355 struct rtw_phl_mcc_sync_tsf_info sync_tsf_info; 2356 struct rtw_phl_mcc_pattern m_pattern; 2357 u8 ref_role_idx; 2358 u8 mrole_map; 2359 u8 mrole_num; 2360 u8 group; 2361 u16 mcc_intvl; 2362 u32 tsf_high; 2363 u32 tsf_low; 2364 u32 tsf_high_l; 2365 u32 tsf_low_l; 2366 struct rtw_phl_mcc_dbg_hal_info dbg_hal_i; 2367 }; 2368 2369 /* 2370 * Bt info 2371 * @bt_dur: bt slot 2372 * @bt_seg: segment bt slot 2373 * @bt_seg_num: segment num 2374 * @add_bt_role: if add_bt_role = true, we need to add bt slot to fw 2375 */ 2376 struct rtw_phl_mcc_bt_info { 2377 u16 bt_dur; 2378 u16 bt_seg[BT_SEG_NUM]; 2379 u8 bt_seg_num; 2380 bool add_bt_role; 2381 }; 2382 2383 enum rtw_phl_mcc_chk_inprocess_type { 2384 RTW_PHL_MCC_CHK_INPROGRESS = 0, 2385 RTW_PHL_MCC_CHK_INPROGRESS_SINGLE_CH, 2386 RTW_PHL_MCC_CHK_INPROGRESS_MULTI_CH, 2387 RTW_PHL_MCC_CHK_MAX, 2388 }; 2389 2390 enum mr_coex_trigger { 2391 MR_COEX_TRIG_BY_BT, 2392 MR_COEX_TRIG_BY_LINKING, 2393 MR_COEX_TRIG_BY_DIS_LINKING, 2394 MR_COEX_TRIG_BY_CHG_SLOT, 2395 MR_COEX_TRIG_BY_SCAN, 2396 MR_COEX_TRIG_BY_ECSA, 2397 MR_COEX_TRIG_BY_CHG_OP_CHDEF, 2398 MR_COEX_TRIG_MAX, 2399 }; 2400 2401 #endif /* CONFIG_MCC_SUPPORT */ 2402 2403 /*multi-roles control components*/ 2404 enum mr_op_mode { 2405 MR_OP_NON, 2406 MR_OP_SCC, 2407 MR_OP_MCC, 2408 MR_OP_MAX, 2409 }; 2410 2411 enum mr_op_type { 2412 MR_OP_TYPE_NONE, 2413 MR_OP_TYPE_STATION_ONLY, 2414 MR_OP_TYPE_AP_ONLY, 2415 MR_OP_TYPE_STATION_AP, 2416 MR_OP_TYPE_MAX, 2417 }; 2418 2419 struct mr_info { 2420 u8 sta_num; 2421 u8 ld_sta_num; 2422 u8 lg_sta_num; /* WIFI_STATION_STATE && WIFI_UNDER_LINKING */ 2423 2424 u8 ap_num; 2425 u8 ld_ap_num; /*&& asoc_sta_count > 2*/ 2426 u8 monitor_num; 2427 2428 u8 p2p_device_num; 2429 u8 p2p_gc_num; 2430 u8 p2p_go_num; 2431 2432 #ifdef CONFIG_PHL_TDLS 2433 u8 ld_tdls_num; /* phl_role->type == PHL_RTYPE_TDLS */ 2434 #endif 2435 2436 #if 0 2437 #ifdef CONFIG_AP_MODE 2438 u8 starting_ap_num; /*WIFI_FW_AP_STATE*/ 2439 #endif 2440 u8 adhoc_num; /* (WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) && WIFI_ASOC_STATE */ 2441 u8 ld_adhoc_num; /* (WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) && WIFI_ASOC_STATE && asoc_sta_count > 2 */ 2442 #ifdef CONFIG_RTW_MESH 2443 u8 mesh_num; /* WIFI_MESH_STATE && WIFI_ASOC_STATE */ 2444 u8 ld_mesh_num; /* WIFI_MESH_STATE && WIFI_ASOC_STATE && asoc_sta_count > 2 */ 2445 #endif 2446 #endif 2447 }; 2448 2449 enum mr_coex_mode { 2450 MR_COEX_MODE_NONE = 0, 2451 MR_COEX_MODE_2GSCC_1AP_1STA_BTC = 1, 2452 MR_COEX_MODE_TDMRA = 2 2453 }; 2454 2455 /*export to core layer*/ 2456 struct mr_query_info { 2457 struct mr_info cur_info; 2458 enum mr_op_mode op_mode; 2459 enum mr_op_type op_type; 2460 }; 2461 2462 struct hw_band_ctl_t { 2463 _os_lock lock; 2464 u8 id; 2465 u8 port_map; /*used port_idx*/ 2466 u8 role_map; /*used role_idx*/ 2467 u8 wmm_map; 2468 struct mr_info cur_info; 2469 enum mr_op_mode op_mode; 2470 enum mr_op_type op_type; 2471 enum phl_hw_port tsf_sync_port; 2472 struct phl_queue chan_ctx_queue;/*struct rtw_chan_ctx*/ 2473 enum mr_coex_mode coex_mode; 2474 #ifdef CONFIG_MCC_SUPPORT 2475 void *mcc_info; /*struct phl_mcc_info*/ 2476 #endif 2477 }; 2478 2479 #define MAX_BAND_NUM 2 2480 struct rtw_hal_com_t; 2481 2482 #ifdef CONFIG_PHL_P2PPS 2483 struct rtw_phl_noa { 2484 struct rtw_wifi_role_t *wrole; 2485 enum p2pps_trig_tag tag; 2486 u32 start_t_h; 2487 u32 start_t_l; 2488 u16 dur; 2489 u8 cnt; 2490 u16 interval; 2491 }; 2492 #endif 2493 2494 struct rtw_phl_mr_ops { 2495 void *priv; /* ops private, define by core layer*/ 2496 #ifdef CONFIG_PHL_P2PPS 2497 int (*phl_mr_update_noa)(void *priv, struct rtw_phl_noa *param); 2498 #endif 2499 #ifdef CONFIG_MCC_SUPPORT 2500 struct rtw_phl_mcc_ops *mcc_ops; 2501 #endif 2502 }; 2503 2504 struct mr_ctl_t { 2505 struct rtw_hal_com_t *hal_com; 2506 _os_lock lock; 2507 struct hw_band_ctl_t band_ctrl[MAX_BAND_NUM]; 2508 struct phl_bk_module_ops bk_ops; 2509 u8 role_map; 2510 bool is_sb; 2511 struct rtw_phl_mr_ops mr_ops; 2512 #ifdef CONFIG_MCC_SUPPORT 2513 u8 init_mcc; 2514 void *com_mcc;/*struct phl_com_mcc_info*/ 2515 #endif 2516 }; 2517 2518 enum rtw_rssi_type { 2519 RTW_RSSI_DATA_ACAM, 2520 RTW_RSSI_DATA_ACAM_A1M, 2521 RTW_RSSI_DATA_OTHER, 2522 RTW_RSSI_CTRL_ACAM, 2523 RTW_RSSI_CTRL_ACAM_A1M, 2524 RTW_RSSI_CTRL_OTHER, 2525 RTW_RSSI_MGNT_ACAM, 2526 RTW_RSSI_MGNT_ACAM_A1M, 2527 RTW_RSSI_MGNT_OTHER, 2528 RTW_RSSI_UNKNOWN, 2529 RTW_RSSI_TYPE_MAX 2530 }; 2531 2532 #define PHL_MAX_RSSI 110 2533 #define PHL_RSSI_MAVG_NUM 16 2534 #define UPDATE_MA_RSSI(_RSSI, _TYPE, _VAL) \ 2535 do { \ 2536 u8 oldest_rssi = 0; \ 2537 if(_RSSI->ma_rssi_ele_idx[_TYPE] < PHL_RSSI_MAVG_NUM) { \ 2538 oldest_rssi = _RSSI->ma_rssi_ele[_TYPE][\ 2539 _RSSI->ma_rssi_ele_idx[_TYPE]]; \ 2540 _RSSI->ma_rssi_ele[_TYPE][_RSSI->ma_rssi_ele_idx[_TYPE]] = \ 2541 ((_VAL > PHL_MAX_RSSI) ? PHL_MAX_RSSI : _VAL ); \ 2542 } else { \ 2543 _RSSI->ma_rssi_ele_idx[_TYPE] = 0; \ 2544 oldest_rssi = _RSSI->ma_rssi_ele[_TYPE][0]; \ 2545 _RSSI->ma_rssi_ele[_TYPE][0] = \ 2546 ((_VAL > PHL_MAX_RSSI) ? PHL_MAX_RSSI : _VAL ); \ 2547 } \ 2548 _RSSI->ma_rssi_ele_sum[_TYPE] -= oldest_rssi;\ 2549 _RSSI->ma_rssi_ele_sum[_TYPE] += \ 2550 ((_VAL > PHL_MAX_RSSI) ? PHL_MAX_RSSI : _VAL ); \ 2551 _RSSI->ma_rssi_ele_idx[_TYPE]++; \ 2552 if(_RSSI->ma_rssi_ele_cnt[_TYPE] < PHL_RSSI_MAVG_NUM) \ 2553 _RSSI->ma_rssi_ele_cnt[_TYPE]++; \ 2554 _RSSI->ma_rssi[_TYPE] = (u8)(_RSSI->ma_rssi_ele_sum[_TYPE] / \ 2555 _RSSI->ma_rssi_ele_cnt[_TYPE]);\ 2556 } while (0) 2557 2558 #define PHL_TRANS_2_RSSI(X) (X >> 1) 2559 2560 struct rtw_phl_rssi_stat { 2561 _os_lock lock; 2562 u8 ma_rssi_ele_idx[RTW_RSSI_TYPE_MAX]; 2563 u8 ma_rssi_ele_cnt[RTW_RSSI_TYPE_MAX]; /* maximum : PHL_RSSI_MAVG_NUM */ 2564 u8 ma_rssi_ele[RTW_RSSI_TYPE_MAX][PHL_RSSI_MAVG_NUM]; /* rssi element for moving average */ 2565 u32 ma_rssi_ele_sum[RTW_RSSI_TYPE_MAX]; 2566 u8 ma_rssi[RTW_RSSI_TYPE_MAX]; /* moving average : 0~PHL_MAX_RSSI (dBm = rssi - PHL_MAX_RSSI) */ 2567 }; 2568 2569 #define PHL_MAX_PPDU_CNT 8 2570 #define PHL_MAX_PPDU_STA_NUM 4 2571 struct rtw_phl_ppdu_sts_sta_ent { 2572 u8 vld; 2573 /*u8 rssi;*/ 2574 u16 macid; 2575 }; 2576 struct rtw_phl_ppdu_phy_info { 2577 bool is_valid; 2578 u8 rssi; /*signal power : 0 - PHL_MAX_RSSI, rssi dbm = PHL_MAX_RSSI - value*/ 2579 u8 rssi_path[RTW_PHL_MAX_RF_PATH];/*PATH A, PATH B ... PATH D*/ 2580 u8 ch_idx; 2581 u8 tx_bf; 2582 u8 frame_type; /* type + subtype */ 2583 }; 2584 #ifdef CONFIG_PHY_INFO_NTFY 2585 struct rtw_phl_ppdu_sts_ntfy { 2586 bool vld; 2587 u8 frame_type; 2588 u8 src_mac_addr[MAC_ADDRESS_LENGTH]; 2589 struct rtw_phl_ppdu_phy_info phy_info; 2590 }; 2591 #endif 2592 struct rtw_phl_ppdu_sts_ent { 2593 /* from normal data */ 2594 u8 frame_type; 2595 u8 addr_cam_vld; 2596 u8 crc32; 2597 u8 ppdu_type; 2598 u16 rx_rate; 2599 u8 src_mac_addr[MAC_ADDRESS_LENGTH]; 2600 2601 /* from ppdu status */ 2602 bool valid; 2603 bool phl_done; 2604 u8 usr_num; 2605 u32 freerun_cnt; 2606 struct rtw_phl_ppdu_phy_info phy_info; 2607 struct rtw_phl_ppdu_sts_sta_ent sta[PHL_MAX_PPDU_STA_NUM]; 2608 #ifdef CONFIG_PHL_RX_PSTS_PER_PKT 2609 /* for ppdu status per pkt */ 2610 struct phl_queue frames; 2611 #endif 2612 }; 2613 struct rtw_phl_ppdu_sts_info { 2614 struct rtw_phl_ppdu_sts_ent sts_ent[HW_BAND_MAX][PHL_MAX_PPDU_CNT]; 2615 u8 cur_rx_ppdu_cnt[HW_BAND_MAX]; 2616 bool en_ppdu_sts[HW_BAND_MAX]; 2617 bool latest_rx_is_psts[HW_BAND_MAX]; 2618 #ifdef CONFIG_PHL_RX_PSTS_PER_PKT 2619 bool en_psts_per_pkt; 2620 bool psts_ampdu; 2621 #define RTW_PHL_PSTS_FLTR_MGNT BIT(RTW_FRAME_TYPE_MGNT) 2622 #define RTW_PHL_PSTS_FLTR_CTRL BIT(RTW_FRAME_TYPE_CTRL) 2623 #define RTW_PHL_PSTS_FLTR_DATA BIT(RTW_FRAME_TYPE_DATA) 2624 #define RTW_PHL_PSTS_FLTR_EXT_RSVD BIT(RTW_FRAME_TYPE_EXT_RSVD) 2625 u8 ppdu_sts_filter; 2626 u8 en_fake_psts; 2627 u8 cur_ppdu_cnt[HW_BAND_MAX]; 2628 #endif 2629 #ifdef CONFIG_PHY_INFO_NTFY 2630 #define MAX_PSTS_MSG_AGGR_NUM 10 2631 struct rtw_phl_ppdu_sts_ntfy msg_aggr_buf[MAX_PSTS_MSG_AGGR_NUM]; 2632 u8 msg_aggr_cnt; 2633 #endif 2634 }; 2635 2636 struct rtw_phl_gid_pos_tbl { 2637 #define RTW_VHT_GID_MGNT_FRAME_GID_SZ 8 2638 #define RTW_VHT_GID_MGNT_FRAME_POS_SZ 16 2639 u8 gid_vld[RTW_VHT_GID_MGNT_FRAME_GID_SZ]; /* from 0 - 63 */ 2640 u8 pos[RTW_VHT_GID_MGNT_FRAME_POS_SZ]; /* 0 - 63, per 2 bit*/ 2641 }; 2642 2643 2644 struct rtw_iot_t { 2645 u32 id; 2646 }; 2647 2648 #ifdef CONFIG_PHL_THERMAL_PROTECT 2649 enum phl_thermal_protect_action{ 2650 PHL_THERMAL_PROTECT_ACTION_NONE = 0, 2651 PHL_THERMAL_PROTECT_ACTION_LEVEL1 = 1, 2652 PHL_THERMAL_PROTECT_ACTION_LEVEL2 = 2, 2653 }; 2654 #endif 2655 2656 struct rtw_phl_evt_ops; 2657 struct rtw_phl_com_t { 2658 struct rtw_wifi_role_t wifi_roles[MAX_WIFI_ROLE_NUMBER]; 2659 struct mr_ctl_t mr_ctrl; /*multi wifi_role control module*/ 2660 struct rtw_phl_evt_ops evt_ops; 2661 enum rtw_hci_type hci_type; 2662 enum rtw_drv_mode drv_mode;/*normal or mp mode*/ 2663 enum rtw_dev_state dev_state; 2664 2665 struct hal_spec_t hal_spec; 2666 2667 struct role_sw_cap_t role_sw_cap; /* SW control capability of role for any purpose */ 2668 struct protocol_cap_t proto_sw_cap[2]; /* SW control wifi protocol capability for any purpose */ 2669 struct phy_sw_cap_t phy_sw_cap[2]; /* SW control phy capability for any purpose */ 2670 struct phy_cap_t phy_cap[2]; /* final capability of phy (intersection of sw/hw) */ 2671 2672 struct dev_cap_t dev_sw_cap; 2673 struct dev_cap_t dev_cap; /* final capability of device (intersection of sw/hw) */ 2674 2675 struct bus_sw_cap_t bus_sw_cap; /* SW controlled bus capability */ 2676 2677 struct rtw_fw_info_t fw_info; 2678 struct rtw_evt_info_t evt_info; 2679 struct rtw_stats phl_stats; 2680 #ifdef CONFIG_PHL_DFS 2681 struct rtw_dfs_t dfs_info; 2682 #endif 2683 struct rtw_iot_t id; 2684 /* Flags to control/check RX packets */ 2685 bool append_fcs; 2686 bool accept_icv_err; 2687 2688 u8 rf_type; /*enum rf_type , is RF_PATH - GET_HAL_RFPATH*/ 2689 u8 rf_path_num; /*GET_HAL_RFPATH_NUM*/ 2690 u8 regulation; /*regulation*/ 2691 u8 edcca_mode; 2692 2693 #ifdef CONFIG_PHL_CHANNEL_INFO 2694 struct rx_chan_info_pool *chan_info_pool; 2695 struct chan_info_t *chan_info; /* Handle channel info packet */ 2696 #endif /* CONFIG_PHL_CHANNEL_INFO */ 2697 void *p2pps_info; 2698 2699 struct rtw_phl_ppdu_sts_info ppdu_sts_info; 2700 struct rtw_phl_rssi_stat rssi_stat; 2701 #ifdef CONFIG_PHL_THERMAL_PROTECT 2702 enum phl_thermal_protect_action thermal_protect_action; 2703 #endif 2704 void *test_mgnt; 2705 2706 void *phl_priv; /* pointer to phl_info */ 2707 void *drv_priv; 2708 #ifdef RTW_WKARD_BFEE_SET_AID 2709 u8 is_in_lps; 2710 #endif 2711 }; 2712 2713 struct phl_sec_param_h { 2714 u8 keyid; 2715 u8 enc_type; 2716 u8 key_type; 2717 u8 key_len; 2718 u8 spp; 2719 }; 2720 2721 #define PHL_MAX_AGG_WSIZE 32 2722 2723 struct mp_usr_sw_tx_gen_in { 2724 u32 data_rate : 9; 2725 u32 mcs : 6; 2726 u32 mpdu_len : 14; 2727 u32 n_mpdu : 9; 2728 u32 fec : 1; 2729 u32 dcm : 1; 2730 u32 rsvd0 : 1; 2731 u32 aid : 12; 2732 u32 scrambler_seed : 8; // rand (1~255) 2733 u32 random_init_seed : 8; // rand (1~255) 2734 u32 rsvd1 : 4; 2735 u32 apep : 22; 2736 u32 ru_alloc : 8; 2737 u32 rsvd2 : 2; 2738 u32 nss : 4; 2739 u32 txbf : 1; 2740 u32 pwr_boost_db : 5; 2741 u32 rsvd3 : 22; 2742 }; 2743 2744 2745 struct mp_sw_tx_param_t { 2746 u32 dbw : 2; //0:BW20, 1:BW40, 2:BW80, 3:BW160/BW80+80 2747 u32 source_gen_mode : 2; 2748 u32 locked_clk : 1; 2749 u32 dyn_bw : 1; 2750 u32 ndp_en : 1; 2751 u32 long_preamble_en : 1; //bmode 2752 u32 stbc : 1; 2753 u32 gi : 2; //0:0.4,1:0.8,2:1.6,3:3.2 2754 u32 tb_l_len : 12; 2755 u32 tb_ru_tot_sts_max : 3; 2756 u32 vht_txop_not_allowed : 1; 2757 u32 tb_disam : 1; 2758 u32 doppler : 2; 2759 u32 he_ltf_type : 2;//0:1x,1:2x,2:4x 2760 2761 u32 ht_l_len : 12; 2762 u32 preamble_puncture : 1; 2763 u32 he_mcs_sigb : 3;//0~5 2764 u32 he_dcm_sigb : 1; 2765 u32 he_sigb_compress_en : 1; 2766 u32 max_tx_time_0p4us : 14; 2767 2768 2769 u32 ul_flag : 1; 2770 u32 tb_ldpc_extra : 1; 2771 u32 bss_color : 6; 2772 u32 sr : 4; 2773 u32 beamchange_en : 1; 2774 u32 he_er_u106ru_en : 1; 2775 u32 ul_srp1 : 4; 2776 u32 ul_srp2 : 4; 2777 u32 ul_srp3 : 4; 2778 u32 ul_srp4 : 4; 2779 u32 mode : 2; 2780 2781 u32 group_id : 6; 2782 u32 ppdu_type : 4;//0: bmode,1:Legacy,2:HT_MF,3:HT_GF,4:VHT,5:HE_SU,6:HE_ER_SU,7:HE_MU,8:HE_TB 2783 u32 txop : 7; 2784 u32 tb_strt_sts : 3; 2785 u32 tb_pre_fec_padding_factor : 2; 2786 u32 cbw : 2; 2787 u32 txsc : 4; 2788 u32 tb_mumimo_mode_en : 1; 2789 u32 rsvd1 : 3; 2790 2791 u8 nominal_t_pe : 2; // def = 2 2792 u8 ness : 2; // def = 0 2793 u8 rsvd2 : 4; 2794 2795 u8 n_user; 2796 u16 tb_rsvd : 9;//def = 0 2797 u16 rsvd3 : 7; 2798 2799 struct mp_usr_sw_tx_gen_in usr[4]; 2800 }; 2801 2802 struct mp_usr_plcp_gen_in { 2803 u32 mcs : 6; 2804 u32 mpdu_len : 14; 2805 u32 n_mpdu : 9; 2806 u32 fec : 1; 2807 u32 dcm : 1; 2808 u32 rsvd0 : 1; 2809 u32 aid : 12; 2810 u32 scrambler_seed : 8; // rand (1~255) 2811 u32 random_init_seed : 8; // rand (1~255) 2812 u32 rsvd1 : 4; 2813 u32 apep : 22; 2814 u32 ru_alloc : 8; 2815 u32 rsvd2 : 2; 2816 u32 nss : 4; 2817 u32 txbf : 1; 2818 u32 pwr_boost_db : 5; 2819 u32 rsvd3 : 22; 2820 }; 2821 2822 enum pkt_ofld_type { 2823 PKT_TYPE_PROBE_RSP = 0, 2824 PKT_TYPE_PS_POLL = 1, 2825 PKT_TYPE_NULL_DATA = 2, 2826 PKT_TYPE_QOS_NULL = 3, 2827 PKT_TYPE_CTS2SELF = 4, 2828 PKT_TYPE_ARP_RSP = 5, 2829 PKT_TYPE_NDP = 6, 2830 PKT_TYPE_EAPOL_KEY = 7, 2831 PKT_TYPE_SA_QUERY = 8, 2832 PKT_TYPE_REALWOW_KAPKT = 9, /* RealWoW Keep Alive Packet */ 2833 PKT_TYPE_REALWOW_ACK = 10, /* RealWoW Ack Patten */ 2834 PKT_TYPE_REALWOW_WP = 11, /* RealWoW Wakeup Patten */ 2835 PKT_TYPE_PROBE_REQ = 12, 2836 PKT_OFLD_TYPE_MAX, 2837 }; 2838 2839 struct scan_ofld_ch_info { 2840 u8 center_chan; 2841 u8 chan; /* primary channel */ 2842 u8 bw; 2843 u8 period; 2844 bool tx_pkt; /* 1:probe request will be sent */ 2845 bool tx_data_pause; /* 1:no data will be sent during fw scanning */ 2846 }; 2847 2848 enum SCAN_OFLD_OP { 2849 SCAN_OFLD_OP_STOP, 2850 SCAN_OFLD_OP_START, 2851 SCAN_OFLD_OP_SET 2852 }; 2853 2854 enum SCAN_OFLD_MD { 2855 /* scan once */ 2856 SCAN_OFLD_MD_ONCE, 2857 /** 2858 * normal period repeatd 2859 * e.g., period = 2s 2860 * scan - 2s - scan - 2s -.... 2861 */ 2862 2863 SCAN_OFLD_MD_PD, 2864 /** 2865 * slow period repeat 2866 * e.g., period = 2s, cycle = 2, slow period = 3s 2867 * scan - 2s - scan - 2s - scan - 3s - scan - 3s 2868 */ 2869 SCAN_OFLD_MD_PD_SLOW, 2870 /** 2871 * seamless 2872 * scan - scan - scan - scan - scan -.... 2873 */ 2874 SCAN_OFLD_MD_SEEMLESS, 2875 }; 2876 2877 struct scan_ofld_info { 2878 enum SCAN_OFLD_OP operation; 2879 enum SCAN_OFLD_MD mode; 2880 /* destinated tsf to start scanning, set 0 for both to scan immediately*/ 2881 u32 tsf_low; 2882 u32 tsf_high; 2883 u32 probe_req_pkt_id; 2884 u32 period; /* SCAN_OFLD_MD_PD & SCAN_OFLD_MD_PD_SLOW */ 2885 u8 cycle; /* SCAN_OFLD_MD_PD & SCAN_OFLD_MD_PD_SLOW*/ 2886 u32 slow_period; /* SCAN_OFLD_MD_PD_SLOW */ 2887 }; 2888 2889 struct mp_plcp_param_t { 2890 u32 dbw : 2; //0:BW20, 1:BW40, 2:BW80, 3:BW160/BW80+80 2891 u32 source_gen_mode : 2; 2892 u32 locked_clk : 1; 2893 u32 dyn_bw : 1; 2894 u32 ndp_en : 1; 2895 u32 long_preamble_en : 1; //bmode 2896 u32 stbc : 1; 2897 u32 gi : 2; //0:0.4,1:0.8,2:1.6,3:3.2 2898 u32 tb_l_len : 12; 2899 u32 tb_ru_tot_sts_max : 3; 2900 u32 vht_txop_not_allowed : 1; 2901 u32 tb_disam : 1; 2902 u32 doppler : 2; 2903 u32 he_ltf_type : 2;//0:1x,1:2x,2:4x 2904 2905 u32 ht_l_len : 12; 2906 u32 preamble_puncture : 1; 2907 u32 he_mcs_sigb : 3;//0~5 2908 u32 he_dcm_sigb : 1; 2909 u32 he_sigb_compress_en : 1; 2910 u32 max_tx_time_0p4us : 14; 2911 2912 2913 u32 ul_flag : 1; 2914 u32 tb_ldpc_extra : 1; 2915 u32 bss_color : 6; 2916 u32 sr : 4; 2917 u32 beamchange_en : 1; 2918 u32 he_er_u106ru_en : 1; 2919 u32 ul_srp1 : 4; 2920 u32 ul_srp2 : 4; 2921 u32 ul_srp3 : 4; 2922 u32 ul_srp4 : 4; 2923 u32 mode : 2; 2924 2925 u32 group_id : 6; 2926 u32 ppdu_type : 4;//0: bmode,1:Legacy,2:HT_MF,3:HT_GF,4:VHT,5:HE_SU,6:HE_ER_SU,7:HE_MU,8:HE_TB 2927 u32 txop : 7; 2928 u32 tb_strt_sts : 3; 2929 u32 tb_pre_fec_padding_factor : 2; 2930 u32 cbw : 2; 2931 u32 txsc : 4; 2932 u32 tb_mumimo_mode_en : 1; 2933 u32 rsvd1 : 3; 2934 2935 u8 nominal_t_pe : 2; // def = 2 2936 u8 ness : 2; // def = 0 2937 u8 rsvd2 : 4; 2938 2939 u8 n_user; 2940 u16 tb_rsvd : 9;//def = 0 2941 u16 rsvd3 : 7; 2942 2943 struct mp_usr_plcp_gen_in usr[4]; 2944 }; 2945 2946 2947 2948 #define MP_MAC_AX_MAX_RU_NUM 4 2949 2950 struct mp_mac_ax_tf_depend_user_para { 2951 u8 pref_AC: 2; 2952 u8 rsvd: 6; 2953 }; 2954 2955 struct mp_mac_ax_tf_user_para { 2956 u16 aid12: 12; 2957 u16 ul_mcs: 4; 2958 u8 macid; 2959 u8 ru_pos; 2960 2961 u8 ul_fec_code: 1; 2962 u8 ul_dcm: 1; 2963 u8 ss_alloc: 6; 2964 u8 ul_tgt_rssi: 7; 2965 u8 rsvd: 1; 2966 u16 rsvd2; 2967 }; 2968 2969 2970 struct mp_mac_ax_tf_pkt_para { 2971 u8 ul_bw: 2; 2972 u8 gi_ltf: 2; 2973 u8 num_he_ltf: 3; 2974 u8 ul_stbc: 1; 2975 u8 doppler: 1; 2976 u8 ap_tx_power: 6; 2977 u8 rsvd0: 1; 2978 u8 user_num: 3; 2979 u8 pktnum: 3; 2980 u8 rsvd1: 2; 2981 u8 pri20_bitmap; 2982 2983 struct mp_mac_ax_tf_user_para user[MP_MAC_AX_MAX_RU_NUM]; 2984 struct mp_mac_ax_tf_depend_user_para dep_user[MP_MAC_AX_MAX_RU_NUM]; 2985 }; 2986 2987 struct mp_mac_ax_tf_wd_para { 2988 u16 datarate: 9; 2989 u16 mulport_id: 3; 2990 u16 pwr_ofset: 3; 2991 u16 rsvd: 1; 2992 }; 2993 2994 struct mp_mac_ax_f2p_test_para { 2995 struct mp_mac_ax_tf_pkt_para tf_pkt; 2996 struct mp_mac_ax_tf_wd_para tf_wd; 2997 u8 mode: 2; 2998 u8 frexch_type: 6; 2999 u8 sigb_len; 3000 }; 3001 3002 struct mp_mac_ax_f2p_wd { 3003 /* dword 0 */ 3004 u32 cmd_qsel:6; 3005 u32 rsvd0:2; 3006 u32 rsvd1:2; 3007 u32 ls:1; 3008 u32 fs:1; 3009 u32 total_number:4; 3010 u32 seq:8; 3011 u32 length:8; 3012 /* dword 1 */ 3013 u32 rsvd2; 3014 }; 3015 3016 struct mp_mac_ax_f2p_tx_cmd { 3017 /* dword 0 */ 3018 u32 cmd_type:8; 3019 u32 cmd_sub_type:8; 3020 u32 dl_user_num:5; 3021 u32 bw:2; 3022 u32 tx_power:9; 3023 /* dword 1 */ 3024 u32 fw_define:16; 3025 u32 ss_sel_mode:2; 3026 u32 next_qsel:6; 3027 u32 twt_group:4; 3028 u32 dis_chk_slp:1; 3029 u32 ru_mu_2_su:1; 3030 u32 dl_t_pe:2; 3031 /* dword 2 */ 3032 u32 sigb_ch1_len:8; 3033 u32 sigb_ch2_len:8; 3034 u32 sigb_sym_num:6; 3035 u32 sigb_ch2_ofs:5; 3036 u32 dis_htp_ack:1; 3037 u32 tx_time_ref:2; 3038 u32 pri_user_idx:2; 3039 /* dword 3 */ 3040 u32 ampdu_max_txtime:14; 3041 u32 rsvd0:2; 3042 u32 group_id:6; 3043 u32 rsvd1:2; 3044 u32 rsvd2:4; 3045 u32 twt_chk_en:1; 3046 u32 twt_port_id:3; 3047 /* dword 4 */ 3048 u32 twt_start_time:32; 3049 /* dword 5 */ 3050 u32 twt_end_time:32; 3051 /* dword 6 */ 3052 u32 apep_len:12; 3053 u32 tri_pad:2; 3054 u32 ul_t_pe:2; 3055 u32 rf_gain_idx:10; 3056 u32 fixed_gain_en:1; 3057 u32 ul_gi_ltf:3; 3058 u32 ul_doppler:1; 3059 u32 ul_stbc:1; 3060 /* dword 7 */ 3061 u32 ul_mid_per:1; 3062 u32 ul_cqi_rrp_tri:1; 3063 u32 rsvd3:6; 3064 u32 rsvd4:8; 3065 u32 sigb_dcm:1; 3066 u32 sigb_comp:1; 3067 u32 doppler:1; 3068 u32 stbc:1; 3069 u32 mid_per:1; 3070 u32 gi_ltf_size:3; 3071 u32 sigb_mcs:3; 3072 u32 rsvd5:5; 3073 /* dword 8 */ 3074 u32 macid_u0:8; 3075 u32 ac_type_u0:2; 3076 u32 mu_sta_pos_u0:2; 3077 u32 dl_rate_idx_u0:9; 3078 u32 dl_dcm_en_u0:1; 3079 u32 rsvd6:2; 3080 u32 ru_alo_idx_u0:8; 3081 /* dword 9 */ 3082 u32 pwr_boost_u0:5; 3083 u32 agg_bmp_alo_u0:3; 3084 u32 ampdu_max_txnum_u0:8; 3085 u32 user_define_u0:8; 3086 u32 user_define_ext_u0:8; 3087 /* dword 10 */ 3088 u32 ul_addr_idx_u0:8; 3089 u32 ul_dcm_u0:1; 3090 u32 ul_fec_cod_u0:1; 3091 u32 ul_ru_rate_u0:7; 3092 u32 rsvd8:7; 3093 u32 ul_ru_alo_idx_u0:8; 3094 /* dword 11 */ 3095 u32 rsvd9:32; 3096 /* dword 12 */ 3097 u32 macid_u1:8; 3098 u32 ac_type_u1:2; 3099 u32 mu_sta_pos_u1:2; 3100 u32 dl_rate_idx_u1:9; 3101 u32 dl_dcm_en_u1:1; 3102 u32 rsvd10:2; 3103 u32 ru_alo_idx_u1:8; 3104 /* dword 13 */ 3105 u32 pwr_boost_u1:5; 3106 u32 agg_bmp_alo_u1:3; 3107 u32 ampdu_max_txnum_u1:8; 3108 u32 user_define_u1:8; 3109 u32 user_define_ext_u1:8; 3110 /* dword 14 */ 3111 u32 ul_addr_idx_u1:8; 3112 u32 ul_dcm_u1:1; 3113 u32 ul_fec_cod_u1:1; 3114 u32 ul_ru_rate_u1:7; 3115 u32 rsvd12:7; 3116 u32 ul_ru_alo_idx_u1:8; 3117 /* dword 15 */ 3118 u32 rsvd13:32; 3119 /* dword 16 */ 3120 u32 macid_u2:8; 3121 u32 ac_type_u2:2; 3122 u32 mu_sta_pos_u2:2; 3123 u32 dl_rate_idx_u2:9; 3124 u32 dl_dcm_en_u2:1; 3125 u32 rsvd14:2; 3126 u32 ru_alo_idx_u2:8; 3127 /* dword 17 */ 3128 u32 pwr_boost_u2:5; 3129 u32 agg_bmp_alo_u2:3; 3130 u32 ampdu_max_txnum_u2:8; 3131 u32 user_define_u2:8; 3132 u32 user_define_ext_u2:8; 3133 /* dword 18 */ 3134 u32 ul_addr_idx_u2:8; 3135 u32 ul_dcm_u2:1; 3136 u32 ul_fec_cod_u2:1; 3137 u32 ul_ru_rate_u2:7; 3138 u32 rsvd16:7; 3139 u32 ul_ru_alo_idx_u2:8; 3140 /* dword 19 */ 3141 u32 rsvd17:32; 3142 /* dword 20 */ 3143 u32 macid_u3:8; 3144 u32 ac_type_u3:2; 3145 u32 mu_sta_pos_u3:2; 3146 u32 dl_rate_idx_u3:9; 3147 u32 dl_dcm_en_u3:1; 3148 u32 rsvd18:2; 3149 u32 ru_alo_idx_u3:8; 3150 /* dword 21 */ 3151 u32 pwr_boost_u3:5; 3152 u32 agg_bmp_alo_u3:3; 3153 u32 ampdu_max_txnum_u3:8; 3154 u32 user_define_u3:8; 3155 u32 user_define_ext_u3:8; 3156 /* dword 22 */ 3157 u32 ul_addr_idx_u3:8; 3158 u32 ul_dcm_u3:1; 3159 u32 ul_fec_cod_u3:1; 3160 u32 ul_ru_rate_u3:7; 3161 u32 rsvd20:7; 3162 u32 ul_ru_alo_idx_u3:8; 3163 /* dword 23 */ 3164 u32 rsvd21:32; 3165 /* dword 24 */ 3166 u32 pkt_id_0:12; 3167 u32 rsvd22:3; 3168 u32 valid_0:1; 3169 u32 ul_user_num_0:4; 3170 u32 rsvd23:12; 3171 /* dword 25 */ 3172 u32 pkt_id_1:12; 3173 u32 rsvd24:3; 3174 u32 valid_1:1; 3175 u32 ul_user_num_1:4; 3176 u32 rsvd25:12; 3177 /* dword 26 */ 3178 u32 pkt_id_2:12; 3179 u32 rsvd26:3; 3180 u32 valid_2:1; 3181 u32 ul_user_num_2:4; 3182 u32 rsvd27:12; 3183 /* dword 27 */ 3184 u32 pkt_id_3:12; 3185 u32 rsvd28:3; 3186 u32 valid_3:1; 3187 u32 ul_user_num_3:4; 3188 u32 rsvd29:12; 3189 /* dword 28 */ 3190 u32 pkt_id_4:12; 3191 u32 rsvd30:3; 3192 u32 valid_4:1; 3193 u32 ul_user_num_4:4; 3194 u32 rsvd31:12; 3195 /* dword 29 */ 3196 u32 pkt_id_5:12; 3197 u32 rsvd32:3; 3198 u32 valid_5:1; 3199 u32 ul_user_num_5:4; 3200 u32 rsvd33:12; 3201 }; 3202 3203 u8 mp_start(void *priv); 3204 3205 #ifdef CONFIG_DBCC_SUPPORT 3206 enum dbcc_test_id { 3207 DBCC_PRE_CFG, 3208 DBCC_CFG, 3209 DBCC_CLEAN_TXQ, 3210 }; 3211 #endif 3212 3213 struct rtw_role_cmd { 3214 struct rtw_wifi_role_t *wrole; 3215 enum role_state rstate; 3216 }; 3217 3218 enum phl_btc_pkt_evt_type { 3219 BTC_PKT_EVT_NORMAL, 3220 BTC_PKT_EVT_DHCP, 3221 BTC_PKT_EVT_ARP, 3222 BTC_PKT_EVT_EAPOL, 3223 BTC_PKT_EVT_EAPOL_START, 3224 BTC_PKT_EVT_ADD_KEY, 3225 BTC_PKT_EVT_MAX 3226 }; 3227 3228 struct rtw_pkt_evt_ntfy { 3229 struct rtw_wifi_role_t *wrole; 3230 enum phl_btc_pkt_evt_type type; 3231 }; 3232 3233 struct role_ntfy_info { 3234 u8 role_id; 3235 u16 macid; 3236 enum role_state rstate; 3237 }; 3238 3239 struct battery_chg_ntfy_info { 3240 bool ips_allow; 3241 bool lps_allow; 3242 }; 3243 3244 struct ps_ntfy_info { 3245 bool sync; 3246 void *ctx; 3247 void (*cb)(void *phl, void *hdl, void *ctx, enum rtw_phl_status stat); 3248 }; 3249 3250 struct set_rf_ntfy_info { 3251 enum rtw_rf_state state_to_set; 3252 _os_event done; 3253 }; 3254 3255 3256 /** 3257 * rtw_phl_rainfo - structure use to query RA information 3258 * from hal layer to core/phl layer 3259 * @rate: current rate selected by RA, define by general definition enum rtw_data_rate 3260 * @bw: current BW, define by general definition enum channel_width 3261 * @gi_ltf: current gi_ltf, define by general definition enum rtw_gi_ltf 3262 */ 3263 struct rtw_phl_rainfo { 3264 enum rtw_data_rate rate; 3265 enum channel_width bw; 3266 enum rtw_gi_ltf gi_ltf; 3267 }; 3268 3269 struct rtw_env_report { 3270 bool rpt_status; /*1 means CCX_SUCCESS,0 means fail*/ 3271 u8 clm_ratio; 3272 u8 nhm_ratio; 3273 u8 nhm_tx_ratio; 3274 u8 nhm_pwr; 3275 u8 nhm_cca_ratio; 3276 }; 3277 3278 enum rtw_phl_ser_lv1_recv_step { 3279 RTW_PHL_SER_LV1_RCVY_STEP_1 = 0, 3280 RTW_PHL_SER_LV1_SER_RCVY_STEP_2, 3281 3282 /* keep last */ 3283 RTW_PHL_SER_LV1_RCVY_STEP_LAST, 3284 RTW_PHL_SER_LV1_RCVY_STEP_MAX = RTW_PHL_SER_LV1_RCVY_STEP_LAST, 3285 RTW_PHL_SER_LV1_RCVY_STEP_INVALID = RTW_PHL_SER_LV1_RCVY_STEP_LAST, 3286 }; 3287 3288 #endif /*_PHL_DEF_H_*/ 3289