1 /******************************************************************************
2 *
3 * Copyright(c) 2019 - 2021 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #include "hal_headers.h"
16
_hal_bus_cap_pre_decision(struct rtw_phl_com_t * phl_com,void * hal)17 static void _hal_bus_cap_pre_decision(struct rtw_phl_com_t *phl_com,
18 void *hal)
19 {
20 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
21 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
22 struct bus_sw_cap_t *bus_sw = &phl_com->bus_sw_cap;
23 struct bus_hw_cap_t *bus_hw = &hal_com->bus_hw_cap;
24 struct bus_cap_t *bus_cap = &hal_com->bus_cap;
25
26 #ifdef CONFIG_PCI_HCI
27 bus_cap->l0s_ctrl = bus_sw->l0s_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
28 bus_hw->l0s_ctrl : bus_sw->l0s_ctrl;
29 bus_cap->l1_ctrl = bus_sw->l1_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
30 bus_hw->l1_ctrl : bus_sw->l1_ctrl;
31 bus_cap->l1ss_ctrl = bus_sw->l1ss_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
32 bus_hw->l1ss_ctrl : bus_sw->l1ss_ctrl;
33 bus_cap->wake_ctrl = bus_sw->wake_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
34 bus_hw->wake_ctrl : bus_sw->wake_ctrl;
35 bus_cap->crq_ctrl = bus_sw->crq_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
36 bus_hw->crq_ctrl : bus_sw->crq_ctrl;
37
38
39 bus_cap->l0sdly_ctrl = bus_sw->l0sdly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ?
40 bus_hw->l0sdly_ctrl : bus_sw->l0sdly_ctrl;
41 bus_cap->l1dly_ctrl = bus_sw->l1dly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ?
42 bus_hw->l1dly_ctrl : bus_sw->l1dly_ctrl;
43 bus_cap->clkdly_ctrl = bus_sw->clkdly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ?
44 bus_hw->clkdly_ctrl : bus_sw->clkdly_ctrl;
45
46
47 bus_cap->txbd_num = (bus_sw->txbd_num) ?
48 ((bus_sw->txbd_num > bus_hw->max_txbd_num) ?
49 bus_hw->max_txbd_num : bus_sw->txbd_num) :
50 bus_hw->max_txbd_num;
51 bus_cap->rxbd_num = (bus_sw->rxbd_num) ?
52 ((bus_sw->rxbd_num > bus_hw->max_rxbd_num) ?
53 bus_hw->max_rxbd_num : bus_sw->rxbd_num) :
54 bus_hw->max_rxbd_num;
55 bus_cap->rpbd_num = (bus_sw->rpbd_num) ?
56 ((bus_sw->rpbd_num > bus_hw->max_rpbd_num) ?
57 bus_hw->max_rpbd_num : bus_sw->rpbd_num) :
58 bus_hw->max_rpbd_num;
59
60 /* rx buffer number must be larger or equal to rx bd number */
61 bus_cap->rxbuf_num = (bus_sw->rxbuf_num < bus_cap->rxbd_num) ?
62 bus_cap->rxbd_num : bus_sw->rxbuf_num;
63 bus_cap->rpbuf_num = (bus_sw->rpbuf_num < bus_cap->rpbd_num) ?
64 bus_cap->rpbd_num : bus_sw->rpbuf_num;
65
66 bus_cap->ltr_act.ctrl = bus_sw->ltr_act.ctrl;
67 bus_cap->ltr_act.val = bus_sw->ltr_act.val;
68 bus_cap->ltr_idle.ctrl = bus_sw->ltr_idle.ctrl;
69 bus_cap->ltr_idle.val = bus_sw->ltr_idle.val;
70 bus_cap->ltr_init_state = bus_sw->ltr_init_state;
71 bus_cap->ltr_sw_ctrl = bus_hw->ltr_sw_ctrl ?
72 (bus_sw->ltr_sw_ctrl ? true : false) : false;
73 bus_cap->ltr_hw_ctrl = bus_hw->ltr_hw_ctrl ?
74 (bus_sw->ltr_hw_ctrl ? true : false) : false;
75 #elif defined (CONFIG_USB_HCI)
76 bus_cap->tx_buf_size = (bus_sw->tx_buf_size) ?
77 ((bus_sw->tx_buf_size < bus_hw->tx_buf_size) ?
78 bus_sw->tx_buf_size : bus_hw->tx_buf_size) :
79 bus_hw->tx_buf_size;
80 bus_cap->tx_buf_num = (bus_sw->tx_buf_num) ?
81 ((bus_sw->tx_buf_num < bus_hw->tx_buf_num) ?
82 bus_sw->tx_buf_num : bus_hw->tx_buf_num) :
83 bus_hw->tx_buf_num;
84 bus_cap->tx_mgnt_buf_size = (bus_sw->tx_mgnt_buf_size) ?
85 ((bus_sw->tx_mgnt_buf_size < bus_hw->tx_mgnt_buf_size) ?
86 bus_sw->tx_mgnt_buf_size : bus_hw->tx_mgnt_buf_size) :
87 bus_hw->tx_mgnt_buf_size;
88 bus_cap->tx_mgnt_buf_num = (bus_sw->tx_mgnt_buf_num) ?
89 ((bus_sw->tx_mgnt_buf_num < bus_hw->tx_mgnt_buf_num) ?
90 bus_sw->tx_mgnt_buf_num : bus_hw->tx_mgnt_buf_num) :
91 bus_hw->tx_mgnt_buf_num;
92 bus_cap->tx_h2c_buf_num = (bus_sw->tx_h2c_buf_num) ?
93 ((bus_sw->tx_h2c_buf_num < bus_hw->tx_h2c_buf_num) ?
94 bus_sw->tx_h2c_buf_num : bus_hw->tx_h2c_buf_num) :
95 bus_hw->tx_h2c_buf_num;
96 bus_cap->rx_buf_size = (bus_sw->rx_buf_size) ?
97 ((bus_sw->rx_buf_size < bus_hw->rx_buf_size) ?
98 bus_sw->rx_buf_size : bus_hw->rx_buf_size) :
99 bus_hw->rx_buf_size;
100 bus_cap->rx_buf_num = (bus_sw->rx_buf_num) ?
101 ((bus_sw->rx_buf_num < bus_hw->rx_buf_num) ?
102 bus_sw->rx_buf_num : bus_hw->rx_buf_num) :
103 bus_hw->rx_buf_num;
104 bus_cap->in_token_num = (bus_sw->in_token_num) ?
105 ((bus_sw->in_token_num < bus_hw->in_token_num) ?
106 bus_sw->in_token_num : bus_hw->in_token_num) :
107 bus_hw->in_token_num;
108 #elif defined(CONFIG_SDIO_HCI)
109 bus_cap->tx_buf_retry_lmt = bus_sw->tx_buf_retry_lmt;
110 bus_cap->tx_buf_size = bus_sw->tx_buf_size ?
111 bus_sw->tx_buf_size : bus_hw->tx_buf_size;
112 bus_cap->tx_buf_num = bus_sw->tx_buf_num ?
113 bus_sw->tx_buf_num : bus_hw->tx_buf_num;
114 bus_cap->tx_mgnt_buf_size = bus_sw->tx_mgnt_buf_size ?
115 bus_sw->tx_mgnt_buf_size : bus_hw->tx_mgnt_buf_size;
116 bus_cap->tx_mgnt_buf_num = bus_sw->tx_mgnt_buf_num ?
117 bus_sw->tx_mgnt_buf_num : bus_hw->tx_mgnt_buf_num;
118 bus_cap->rx_buf_size = bus_sw->rx_buf_size ?
119 bus_sw->rx_buf_size : bus_hw->rx_buf_size;
120 bus_cap->rx_buf_num = bus_sw->rx_buf_num ?
121 bus_sw->rx_buf_num : bus_hw->rx_buf_num;
122 #endif
123 }
124
125 #ifdef CONFIG_PCI_HCI
_hal_bus_final_cap_decision(struct rtw_phl_com_t * phl_com,struct rtw_hal_com_t * hal_com)126 static void _hal_bus_final_cap_decision(struct rtw_phl_com_t *phl_com,
127 struct rtw_hal_com_t *hal_com)
128 {
129 struct bus_sw_cap_t *bus_sw = &phl_com->bus_sw_cap;
130 struct bus_hw_cap_t *bus_hw = &hal_com->bus_hw_cap;
131 struct bus_cap_t *bus_cap = &hal_com->bus_cap;
132
133 bus_cap->l0s_ctrl = bus_sw->l0s_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
134 bus_hw->l0s_ctrl : bus_sw->l0s_ctrl;
135 bus_cap->l1_ctrl = bus_sw->l1_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
136 bus_hw->l1_ctrl : bus_sw->l1_ctrl;
137 bus_cap->l1ss_ctrl = bus_sw->l1ss_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
138 bus_hw->l1ss_ctrl : bus_sw->l1ss_ctrl;
139 bus_cap->wake_ctrl = bus_sw->wake_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
140 bus_hw->wake_ctrl : bus_sw->wake_ctrl;
141 bus_cap->crq_ctrl = bus_sw->crq_ctrl >= RTW_PCIE_BUS_FUNC_DEFAULT ?
142 bus_hw->crq_ctrl : bus_sw->crq_ctrl;
143
144 bus_cap->l0sdly_ctrl = bus_sw->l0sdly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ?
145 bus_hw->l0sdly_ctrl : bus_sw->l0sdly_ctrl;
146 bus_cap->l1dly_ctrl = bus_sw->l1dly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ?
147 bus_hw->l1dly_ctrl : bus_sw->l1dly_ctrl;
148 bus_cap->clkdly_ctrl = bus_sw->clkdly_ctrl == RTW_PCIE_BUS_ASPM_DLY_IGNORE ?
149 bus_hw->clkdly_ctrl : bus_sw->clkdly_ctrl;
150
151
152 bus_cap->txbd_num = (bus_sw->txbd_num) ?
153 ((bus_sw->txbd_num > bus_hw->max_txbd_num) ?
154 bus_hw->max_txbd_num : bus_sw->txbd_num) :
155 bus_hw->max_txbd_num;
156 bus_cap->rxbd_num = (bus_sw->rxbd_num) ?
157 ((bus_sw->rxbd_num > bus_hw->max_rxbd_num) ?
158 bus_hw->max_rxbd_num : bus_sw->rxbd_num) :
159 bus_hw->max_rxbd_num;
160 bus_cap->rpbd_num = (bus_sw->rpbd_num) ?
161 ((bus_sw->rpbd_num > bus_hw->max_rpbd_num) ?
162 bus_hw->max_rpbd_num : bus_sw->rpbd_num) :
163 bus_hw->max_rpbd_num;
164
165 bus_cap->ltr_act.ctrl = bus_sw->ltr_act.ctrl;
166 bus_cap->ltr_act.val = bus_sw->ltr_act.val;
167 bus_cap->ltr_idle.ctrl = bus_sw->ltr_idle.ctrl;
168 bus_cap->ltr_idle.val = bus_sw->ltr_idle.val;
169 bus_cap->ltr_init_state = bus_sw->ltr_init_state;
170 bus_cap->ltr_sw_ctrl = bus_hw->ltr_sw_ctrl ?
171 (bus_sw->ltr_sw_ctrl ? true : false) : false;
172 bus_cap->ltr_hw_ctrl = bus_hw->ltr_hw_ctrl ?
173 (bus_sw->ltr_hw_ctrl ? true : false) : false;
174 }
175 #endif
176
_hal_ps_final_cap_decision(struct rtw_phl_com_t * phl_com,struct rtw_hal_com_t * hal_com)177 static void _hal_ps_final_cap_decision(struct rtw_phl_com_t *phl_com,
178 struct rtw_hal_com_t *hal_com)
179 {
180 struct rtw_ps_cap_t *ps_cap = &phl_com->dev_cap.ps_cap;
181 struct rtw_ps_cap_t *ps_sw_cap = &phl_com->dev_sw_cap.ps_cap;
182 struct rtw_ps_cap_t *ps_hw_cap = &hal_com->dev_hw_cap.ps_cap;
183
184 /* sw */
185 ps_cap->init_rf_state = ps_sw_cap->init_rf_state;
186 ps_cap->init_rt_stop_rson = ps_sw_cap->init_rt_stop_rson;
187 ps_cap->leave_fail_act = ps_sw_cap->leave_fail_act;
188 ps_cap->ips_en = ps_sw_cap->ips_en;
189 ps_cap->ips_wow_en = ps_sw_cap->ips_wow_en;
190 ps_cap->lps_en = ps_sw_cap->lps_en;
191 ps_cap->lps_awake_interval = ps_sw_cap->lps_awake_interval;
192 ps_cap->lps_listen_bcn_mode = ps_sw_cap->lps_listen_bcn_mode;
193 ps_cap->lps_smart_ps_mode = ps_sw_cap->lps_smart_ps_mode;
194 ps_cap->lps_rssi_enter_threshold = ps_sw_cap->lps_rssi_enter_threshold;
195 ps_cap->lps_rssi_leave_threshold = ps_sw_cap->lps_rssi_leave_threshold;
196 ps_cap->lps_rssi_diff_threshold = ps_sw_cap->lps_rssi_diff_threshold;
197 ps_cap->lps_wow_en = ps_sw_cap->lps_wow_en;
198 ps_cap->lps_wow_awake_interval = ps_sw_cap->lps_wow_awake_interval;
199 ps_cap->lps_wow_listen_bcn_mode = ps_sw_cap->lps_wow_listen_bcn_mode;
200 ps_cap->lps_wow_smart_ps_mode = ps_sw_cap->lps_wow_smart_ps_mode;
201 /* hw */
202 ps_cap->lps_pause_tx = ps_hw_cap->lps_pause_tx;
203 /* sw & hw */
204 ps_cap->ips_cap = (ps_sw_cap->ips_cap & ps_hw_cap->ips_cap);
205 ps_cap->ips_wow_cap = (ps_sw_cap->ips_wow_cap & ps_hw_cap->ips_wow_cap);
206 ps_cap->lps_cap = (ps_sw_cap->lps_cap & ps_hw_cap->lps_cap);
207 ps_cap->lps_wow_cap = (ps_sw_cap->lps_wow_cap & ps_hw_cap->lps_wow_cap);
208 }
209
_hal_edcca_final_cap_decision(struct rtw_phl_com_t * phl_com,struct rtw_hal_com_t * hal_com)210 static void _hal_edcca_final_cap_decision(struct rtw_phl_com_t *phl_com,
211 struct rtw_hal_com_t *hal_com)
212 {
213 struct rtw_edcca_cap_t *edcca_cap = &phl_com->dev_cap.edcca_cap;
214 struct rtw_edcca_cap_t *edcca_sw_cap = &phl_com->dev_sw_cap.edcca_cap;
215 struct rtw_edcca_cap_t *edcca_hw_cap = &hal_com->dev_hw_cap.edcca_cap;
216
217 edcca_cap->edcca_adap_th_2g = (edcca_sw_cap->edcca_adap_th_2g)?
218 (edcca_sw_cap->edcca_adap_th_2g):
219 (edcca_hw_cap->edcca_adap_th_2g);
220 edcca_cap->edcca_adap_th_5g = (edcca_sw_cap->edcca_adap_th_5g)?
221 (edcca_sw_cap->edcca_adap_th_5g):
222 (edcca_hw_cap->edcca_adap_th_5g);
223
224 edcca_cap->edcca_carrier_sense_th = (edcca_sw_cap->edcca_carrier_sense_th)?
225 (edcca_sw_cap->edcca_carrier_sense_th):
226 (edcca_hw_cap->edcca_carrier_sense_th);
227 }
228
rtw_hal_fw_cap_pre_config(struct rtw_phl_com_t * phl_com,void * hal)229 void rtw_hal_fw_cap_pre_config(struct rtw_phl_com_t *phl_com, void *hal)
230 {
231
232 struct dev_cap_t *dev_cap = &phl_com->dev_cap;
233 struct dev_cap_t *dev_sw_cap = &phl_com->dev_sw_cap;
234
235 /* leaving for fw hw cap
236 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
237 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
238 struct dev_cap_t *dev_hw_cap = &hal_com->dev_hw_cap;
239 */
240
241 dev_cap->fw_cap.fw_src = dev_sw_cap->fw_cap.fw_src;
242 dev_cap->fw_cap.dlram_en = dev_sw_cap->fw_cap.dlram_en;
243 dev_cap->fw_cap.dlrom_en = dev_sw_cap->fw_cap.dlrom_en;
244 }
245
rtw_hal_bus_cap_pre_config(struct rtw_phl_com_t * phl_com,void * hal)246 void rtw_hal_bus_cap_pre_config(struct rtw_phl_com_t *phl_com, void *hal)
247 {
248 _hal_bus_cap_pre_decision(phl_com, hal);
249 }
250
251
252
rtw_hal_fw_final_cap_config(struct rtw_phl_com_t * phl_com,void * hal)253 void rtw_hal_fw_final_cap_config(struct rtw_phl_com_t *phl_com, void *hal)
254 {
255
256 struct dev_cap_t *dev_cap = &phl_com->dev_cap;
257 struct dev_cap_t *dev_sw_cap = &phl_com->dev_sw_cap;
258
259 /* leaving for fw hw cap
260 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
261 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
262 struct dev_cap_t *dev_hw_cap = &hal_com->dev_hw_cap;
263 */
264
265 dev_cap->fw_cap.fw_src = dev_sw_cap->fw_cap.fw_src;
266 dev_cap->fw_cap.dlram_en = dev_sw_cap->fw_cap.dlram_en;
267 dev_cap->fw_cap.dlrom_en = dev_sw_cap->fw_cap.dlrom_en;
268 }
269
rtw_hal_final_cap_decision(struct rtw_phl_com_t * phl_com,void * hal)270 void rtw_hal_final_cap_decision(struct rtw_phl_com_t *phl_com, void *hal)
271 {
272 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
273 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
274 struct phy_hw_cap_t *phy_hw = hal_com->phy_hw_cap;
275 struct phy_sw_cap_t *phy_sw = phl_com->phy_sw_cap;
276 struct phy_cap_t *phy_cap = phl_com->phy_cap;
277
278 struct dev_cap_t *dev_cap = &phl_com->dev_cap;
279 struct dev_cap_t *dev_sw_cap = &phl_com->dev_sw_cap;
280 struct dev_cap_t *dev_hw_cap = &hal_com->dev_hw_cap;
281
282 #ifdef RTW_WKARD_PHY_CAP
283 phy_cap[0].proto_sup = phy_sw[0].proto_sup;
284 phy_cap[1].proto_sup = phy_sw[1].proto_sup;
285 phy_cap[0].band_sup = phy_sw[0].band_sup;
286 phy_cap[1].band_sup = phy_sw[1].band_sup;
287 phy_cap[0].bw_sup = phy_sw[0].bw_sup;
288 phy_cap[1].bw_sup = phy_sw[1].bw_sup;
289
290 phy_cap[0].txss = (phy_sw[0].txss)?((phy_sw[0].txss > phy_hw[0].tx_num)?
291 phy_hw[0].tx_num:phy_sw[0].txss):phy_hw[0].tx_num;
292 phy_cap[0].rxss = (phy_sw[0].rxss)?((phy_sw[0].rxss > phy_hw[0].rx_num)?
293 phy_hw[0].rx_num:phy_sw[0].rxss):phy_hw[0].rx_num;
294 phy_cap[1].txss = (phy_sw[1].txss)?((phy_sw[1].txss > phy_hw[1].tx_num)?
295 phy_hw[1].tx_num:phy_sw[1].txss):phy_hw[1].tx_num;
296 phy_cap[1].rxss = (phy_sw[1].rxss)?((phy_sw[1].rxss > phy_hw[1].rx_num)?
297 phy_hw[1].rx_num:phy_sw[1].rxss):phy_hw[1].rx_num;
298 phy_cap[0].hw_rts_time_th = (phy_sw[0].hw_rts_time_th)?
299 phy_sw[0].hw_rts_time_th:phy_hw[0].hw_rts_time_th;
300 phy_cap[1].hw_rts_time_th = (phy_sw[1].hw_rts_time_th)?
301 phy_sw[1].hw_rts_time_th:phy_hw[1].hw_rts_time_th;
302 phy_cap[0].hw_rts_len_th = (phy_sw[0].hw_rts_len_th)?
303 phy_sw[0].hw_rts_len_th:phy_hw[0].hw_rts_len_th;
304 phy_cap[1].hw_rts_len_th = (phy_sw[1].hw_rts_len_th)?
305 phy_sw[1].hw_rts_len_th:phy_hw[1].hw_rts_len_th;
306 /* fw */
307 rtw_hal_fw_final_cap_config(phl_com,hal);
308 #endif
309
310 #ifdef RTW_WKARD_LAMODE
311 if (dev_sw_cap->la_mode && dev_hw_cap->la_mode)
312 dev_cap->la_mode = true;
313 #endif
314
315 /* wow, to be refined along with hw cap */
316 dev_cap->wow_cap.magic_sup = dev_sw_cap->wow_cap.magic_sup;
317 dev_cap->wow_cap.pattern_sup = dev_sw_cap->wow_cap.pattern_sup;
318 dev_cap->wow_cap.arp_ofld_sup = dev_sw_cap->wow_cap.arp_ofld_sup;
319 dev_cap->wow_cap.ns_oflod_sup = dev_sw_cap->wow_cap.ns_oflod_sup;
320 dev_cap->wow_cap.gtk_ofld_sup = dev_sw_cap->wow_cap.gtk_ofld_sup;
321 dev_cap->wow_cap.ping_pattern_wake_sup = dev_sw_cap->wow_cap.ping_pattern_wake_sup;
322 dev_cap->wow_cap.nlo_sup = dev_sw_cap->wow_cap.nlo_sup;
323
324 if (dev_sw_cap->pkg_type != 0xFF)
325 dev_cap->pkg_type = dev_sw_cap->pkg_type;
326 else
327 dev_cap->pkg_type = dev_hw_cap->pkg_type;
328
329 if (dev_sw_cap->rfe_type != 0xFF)
330 dev_cap->rfe_type = dev_sw_cap->rfe_type;
331 else
332 dev_cap->rfe_type = dev_hw_cap->rfe_type;
333
334 dev_cap->bypass_rfe_chk = dev_sw_cap->bypass_rfe_chk;
335
336 hal_com->dbcc_en = false;/*init default value*/
337 #ifdef CONFIG_DBCC_SUPPORT
338 if (dev_sw_cap->dbcc_sup && dev_hw_cap->dbcc_sup)
339 dev_cap->dbcc_sup = true;
340 /*TODO - update dbcc_en from sw & hw cap
341 if (dev_cap->dbcc_sup && dft->dbcc_en)
342 hal_com->dbcc_en = true;
343 */
344 #endif
345
346 #ifdef CONFIG_MCC_SUPPORT
347 if (dev_sw_cap->mcc_sup && dev_hw_cap->mcc_sup)
348 dev_cap->mcc_sup = true;
349 #endif /*CONFIG_MCC_SUPPORT*/
350
351 #ifdef CONFIG_PHL_TWT
352 dev_cap->twt_sup = (dev_sw_cap->twt_sup & dev_hw_cap->twt_sup);
353 #endif /*CONFIG_PHL_TWT*/
354
355 if (dev_sw_cap->hw_hdr_conv && dev_hw_cap->hw_hdr_conv)
356 dev_cap->hw_hdr_conv = true;
357 if (dev_sw_cap->tx_mu_ru && dev_hw_cap->tx_mu_ru)
358 dev_cap->tx_mu_ru = true;
359
360 dev_cap->xcap = dev_hw_cap->xcap;
361 dev_cap->domain = dev_hw_cap->domain;
362 dev_cap->btc_mode = dev_sw_cap->btc_mode;
363
364 #ifdef CONFIG_PCI_HCI
365 _hal_bus_final_cap_decision(phl_com, hal_com);
366 #endif
367
368 if (dev_sw_cap->pwrbyrate_off != 0xFF)
369 dev_cap->pwrbyrate_off = dev_sw_cap->pwrbyrate_off;
370 else
371 dev_cap->pwrbyrate_off = PW_BY_RATE_ON;
372
373 if (dev_sw_cap->pwrlmt_type != 0xFF)
374 dev_cap->pwrlmt_type = dev_sw_cap->pwrlmt_type;
375 else
376 dev_cap->pwrlmt_type = PWLMT_BY_EFUSE;
377
378 if (dev_sw_cap->rf_board_opt != 0xFF)
379 dev_cap->rf_board_opt = dev_sw_cap->rf_board_opt;
380 else
381 dev_cap->rf_board_opt = dev_hw_cap->rf_board_opt;
382
383 if (RTW_HW_CAP_ULRU_AUTO == dev_sw_cap->sta_ulru) {
384 /* auto : use hw default setting */
385 dev_cap->sta_ulru = dev_hw_cap->sta_ulru;
386 } else {
387 /* forced use sw settings */
388 dev_cap->sta_ulru = dev_sw_cap->sta_ulru;
389 }
390 PHL_INFO("sta_ulru final : 0x%x ; sw 0x%x ; hw 0x%x\n",
391 dev_cap->sta_ulru, dev_sw_cap->sta_ulru, dev_hw_cap->sta_ulru);
392
393 #ifdef RTW_WKARD_BB_DISABLE_STA_2G40M_ULOFDMA
394 /* 2.4G 40MHz UL OFDAM : bb ask to disable */
395 if (RTW_HW_CAP_ULRU_AUTO == dev_sw_cap->sta_ulru_2g40mhz) {
396 /* auto : use hw default setting */
397 dev_cap->sta_ulru_2g40mhz = dev_hw_cap->sta_ulru_2g40mhz;
398 } else {
399 /* forced use sw settings */
400 dev_cap->sta_ulru_2g40mhz = dev_sw_cap->sta_ulru_2g40mhz;
401 }
402 PHL_INFO("sta_ulru_2g40mhz final : 0x%x ; sw 0x%x ; hw 0x%x\n",
403 dev_cap->sta_ulru_2g40mhz, dev_sw_cap->sta_ulru_2g40mhz, dev_hw_cap->sta_ulru_2g40mhz);
404 #endif
405
406 _hal_ps_final_cap_decision(phl_com, hal_com);
407
408 _hal_edcca_final_cap_decision(phl_com, hal_com);
409
410 if (dev_hw_cap->hw_stype_cap != EFUSE_HW_STYPE_GENERAL)
411 dev_cap->hw_stype_cap = dev_hw_cap->hw_stype_cap;
412 else
413 dev_cap->hw_stype_cap = EFUSE_HW_STYPE_NONE;
414
415 if (dev_hw_cap->wl_func_cap != EFUSE_WL_FUNC_GENERAL)
416 dev_cap->wl_func_cap = dev_hw_cap->wl_func_cap;
417 else
418 dev_cap->wl_func_cap = EFUSE_WL_FUNC_NONE;
419
420 dev_cap->rpq_agg_num = dev_sw_cap->rpq_agg_num ?
421 dev_sw_cap->rpq_agg_num : dev_hw_cap->rpq_agg_num;
422
423 /* MAC_AX_QTA_SCC_TURBO, decide by sw, need to be refined after we have hw cap */
424 dev_cap->quota_turbo = dev_sw_cap->quota_turbo;
425 }
426
427 /**
428 * rtw_hal_get_bf_proto_cap
429 * input:
430 * @phl: (struct phl_info_t *phl_info)
431 * @band:
432 * input_output:
433 * @proto_cap: (struct protocol_cap_t *proto_cap) the variable to save the bf_cap result.
434 * return:
435 * @rtw_hal_status:
436 */
437 enum rtw_hal_status
rtw_hal_get_bf_proto_cap(struct rtw_phl_com_t * phl_com,void * hal,u8 band,struct protocol_cap_t * proto_cap)438 rtw_hal_get_bf_proto_cap(struct rtw_phl_com_t *phl_com, void *hal,
439 u8 band, struct protocol_cap_t *proto_cap)
440 {
441 #ifdef RTW_WKARD_PHY_CAP
442 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
443 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
444 struct protocol_cap_t *hw_cap = NULL;
445 struct protocol_cap_t *sw_cap = NULL;
446
447 if (band >= HW_BAND_MAX) {
448 PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "rtw_hal_get_bf_proto_cap : invalid band index \n");
449 return RTW_HAL_STATUS_FAILURE;
450 }
451 if (proto_cap == NULL) {
452 PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "rtw_hal_get_bf_proto_cap : input proto_cap is NULL \n");
453 return RTW_HAL_STATUS_FAILURE;
454 }
455
456
457 hw_cap = &hal_com->proto_hw_cap[band];
458 sw_cap = &phl_com->proto_sw_cap[band];
459
460 proto_cap->he_su_bfmr =
461 (sw_cap->he_su_bfmr && hw_cap->he_su_bfmr) ? 1 : 0;
462 proto_cap->he_su_bfme =
463 (sw_cap->he_su_bfme && hw_cap->he_su_bfme) ? 1 : 0;
464 proto_cap->he_mu_bfmr =
465 (sw_cap->he_mu_bfmr && hw_cap->he_mu_bfmr) ? 1 : 0;
466 proto_cap->he_mu_bfme =
467 (sw_cap->he_mu_bfme && hw_cap->he_mu_bfme) ? 1 : 0;
468 proto_cap->non_trig_cqi_fb =
469 (sw_cap->non_trig_cqi_fb && hw_cap->non_trig_cqi_fb) ? 1 : 0;
470 proto_cap->trig_cqi_fb =
471 (sw_cap->trig_cqi_fb && hw_cap->trig_cqi_fb) ? 1 : 0;
472
473 proto_cap->vht_su_bfme =
474 (sw_cap->vht_su_bfme && hw_cap->vht_su_bfme) ? 1 : 0;
475 proto_cap->vht_su_bfmr =
476 (sw_cap->vht_su_bfmr && hw_cap->vht_su_bfmr) ? 1 : 0;
477 proto_cap->vht_mu_bfme =
478 (sw_cap->vht_mu_bfme && hw_cap->vht_mu_bfme) ? 1 : 0;
479 proto_cap->vht_mu_bfmr =
480 (sw_cap->vht_mu_bfmr && hw_cap->vht_mu_bfmr) ? 1 : 0;
481
482 proto_cap->ht_su_bfme =
483 (sw_cap->ht_su_bfme && hw_cap->ht_su_bfme) ? 1 : 0;
484 proto_cap->ht_su_bfmr =
485 (sw_cap->ht_su_bfmr && hw_cap->ht_su_bfmr) ? 1 : 0;
486
487 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
488 "rtw_hal_get_bf_proto_cap : proto_cap->he_su_bfmr = 0x%x \n",
489 proto_cap->he_su_bfmr);
490 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
491 "rtw_hal_get_bf_proto_cap : proto_cap->he_su_bfme = 0x%x \n",
492 proto_cap->he_su_bfme);
493 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
494 "rtw_hal_get_bf_proto_cap : proto_cap->he_mu_bfmr = 0x%x \n",
495 proto_cap->he_mu_bfmr);
496 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
497 "rtw_hal_get_bf_proto_cap : proto_cap->he_mu_bfme = 0x%x \n",
498 proto_cap->he_mu_bfme);
499 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
500 "rtw_hal_get_bf_proto_cap : proto_cap->non_trig_cqi_fb = 0x%x \n",
501 proto_cap->non_trig_cqi_fb);
502 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
503 "rtw_hal_get_bf_proto_cap : proto_cap->trig_cqi_fb = 0x%x \n",
504 proto_cap->trig_cqi_fb);
505 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
506 "rtw_hal_get_bf_proto_cap : proto_cap->vht_su_bfme = 0x%x \n",
507 proto_cap->vht_su_bfme);
508 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
509 "rtw_hal_get_bf_proto_cap : proto_cap->vht_su_bfmr = 0x%x \n",
510 proto_cap->vht_su_bfmr);
511 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
512 "rtw_hal_get_bf_proto_cap : proto_cap->vht_mu_bfme = 0x%x \n",
513 proto_cap->vht_mu_bfme);
514 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
515 "rtw_hal_get_bf_proto_cap : proto_cap->vht_mu_bfmr = 0x%x \n",
516 proto_cap->vht_mu_bfmr);
517 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
518 "rtw_hal_get_bf_proto_cap : proto_cap->ht_su_bfme = 0x%x \n",
519 proto_cap->ht_su_bfme);
520 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
521 "rtw_hal_get_bf_proto_cap : proto_cap->ht_su_bfmr = 0x%x \n",
522 proto_cap->ht_su_bfmr);
523 #endif
524 return RTW_HAL_STATUS_SUCCESS;
525 }
526
527
528 /**
529 * rtw_hal_get_stbc_proto_cap() - Get the intersection proto_cap of the proto_hw_cap and proto_sw_cap
530 * @phl_com: input, the pointer of phl_com (struct rtw_phl_com_t)
531 * @hal: input, the pointer of hal (struct hal_info_t)
532 * @band: input, the band index
533 * @proto_cap: input_output (struct protocol_cap_t)
534 * The variable pointer to save the ouput proto_cap results.
535 * Here, we update STBC cap into STBC fileds of proto_cap.
536 * Return: return the result of getting proto_cap (enum @rtw_hal_status)
537 */
538 enum rtw_hal_status
rtw_hal_get_stbc_proto_cap(struct rtw_phl_com_t * phl_com,void * hal,u8 band,struct protocol_cap_t * proto_cap)539 rtw_hal_get_stbc_proto_cap(struct rtw_phl_com_t *phl_com, void *hal,
540 u8 band, struct protocol_cap_t *proto_cap)
541 {
542 struct hal_info_t *hal_info = (struct hal_info_t *)hal;
543 struct rtw_hal_com_t *hal_com = hal_info->hal_com;
544 struct protocol_cap_t *hw_cap = NULL;
545 struct protocol_cap_t *sw_cap = NULL;
546
547 if (band >= HW_BAND_MAX) {
548 PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "rtw_hal_get_stbc_proto_cap : invalid band index \n");
549 return RTW_HAL_STATUS_FAILURE;
550 }
551 if (proto_cap == NULL) {
552 PHL_TRACE(COMP_PHL_DBG, _PHL_ERR_, "rtw_hal_get_stbc_proto_cap : input proto_cap is NULL \n");
553 return RTW_HAL_STATUS_FAILURE;
554 }
555
556 hw_cap = &hal_com->proto_hw_cap[band];
557 sw_cap = &phl_com->proto_sw_cap[band];
558
559 proto_cap->stbc_tx =
560 (sw_cap->stbc_tx && hw_cap->stbc_tx) ? 1 : 0; /* Remove later */
561 proto_cap->stbc_ht_tx =
562 (sw_cap->stbc_ht_tx && hw_cap->stbc_ht_tx) ? 1 : 0;
563 proto_cap->stbc_vht_tx =
564 (sw_cap->stbc_vht_tx && hw_cap->stbc_vht_tx) ? 1 : 0;
565 proto_cap->stbc_he_tx =
566 (sw_cap->stbc_he_tx && hw_cap->stbc_he_tx) ? 1 : 0;
567 proto_cap->stbc_tx_greater_80mhz =
568 (sw_cap->stbc_tx_greater_80mhz && hw_cap->stbc_tx_greater_80mhz) ? 1 : 0;
569
570 proto_cap->stbc_ht_rx =
571 (sw_cap->stbc_ht_rx <= hw_cap->stbc_ht_rx) ?
572 sw_cap->stbc_ht_rx : hw_cap->stbc_ht_rx;
573 proto_cap->stbc_vht_rx =
574 (sw_cap->stbc_vht_rx <= hw_cap->stbc_vht_rx) ?
575 sw_cap->stbc_vht_rx : hw_cap->stbc_vht_rx;
576 proto_cap->stbc_he_rx =
577 (sw_cap->stbc_he_rx && hw_cap->stbc_he_rx) ? 1 : 0;
578 proto_cap->stbc_rx_greater_80mhz =
579 (sw_cap->stbc_rx_greater_80mhz && hw_cap->stbc_rx_greater_80mhz) ? 1 : 0;
580
581 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
582 "%s : proto_cap->stbc_tx = 0x%x \n",
583 __func__, proto_cap->stbc_tx); /* Remove later */
584 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
585 "%s : proto_cap->stbc_ht_tx = 0x%x \n",
586 __func__, proto_cap->stbc_ht_tx);
587 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
588 "%s : proto_cap->stbc_vht_tx = 0x%x \n",
589 __func__, proto_cap->stbc_vht_tx);
590 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
591 "%s : proto_cap->stbc_he_tx = 0x%x \n",
592 __func__, proto_cap->stbc_he_tx);
593 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
594 "%s : proto_cap->stbc_tx_greater_80mhz = 0x%x \n",
595 __func__, proto_cap->stbc_tx_greater_80mhz);
596 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
597 "%s : proto_cap->stbc_ht_rx = 0x%x \n",
598 __func__, proto_cap->stbc_ht_rx);
599 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
600 "%s : proto_cap->stbc_vht_rx = 0x%x \n",
601 __func__, proto_cap->stbc_vht_rx);
602 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
603 "%s : proto_cap->stbc_he_rx = 0x%x \n",
604 __func__, proto_cap->stbc_he_rx);
605 PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
606 "%s : proto_cap->stbc_rx_greater_80mhz = 0x%x \n",
607 __func__, proto_cap->stbc_rx_greater_80mhz);
608
609 return RTW_HAL_STATUS_SUCCESS;
610 }
611