Searched refs:SUNXI_DRAM_COM_BASE (Results 1 – 9 of 9) sorted by relevance
91 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mbus_configure_port()113 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h3()138 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_a64()165 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_h5()193 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_master_priority_r40()338 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_cr()423 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_channel_init()688 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in sunxi_dram_init()
36 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_cr()207 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_channel_init()302 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_sys_init()331 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in sunxi_dram_init()
106 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_channel_init()266 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_com_init()297 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_port_cfg()332 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in sunxi_dram_init()
206 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_sys_init()344 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_com_init()829 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in DRAMC_get_dram_size()860 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in sunxi_dram_init()
35 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_set_cr()263 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_channel_init()429 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in sunxi_dram_init()
96 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in mctl_init()270 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; in sunxi_dram_init()
170 #define MCTL_PROTECT (SUNXI_DRAM_COM_BASE + 0x800)171 #define MCTL_MASTER_CFG0(x) (SUNXI_DRAM_COM_BASE + 0x10 + 0x8 * x)172 #define MCTL_MASTER_CFG1(x) (SUNXI_DRAM_COM_BASE + 0x14 + 0x8 * x)
45 #define SUNXI_DRAM_COM_BASE (REGS_AHB0_BASE + 0x62000) macro
155 #define SUNXI_DRAM_COM_BASE 0x01c62000 macro