Searched refs:RPLL (Results 1 – 5 of 5) sorted by relevance
24 RPLL and sdio1_ref clocks before and after this change:26 - Old values: RPLL 1.36 GHz, sdio1_ref 272 MHz27 - New values: RPLL 1.16 GHz, sdio1_ref 233 MHz
17 #define RPLL 6 macro
13 #define RPLL 1 macro
31 #define RPLL 22 macro
141 if (pllreg == EPLL || pllreg == RPLL) { in exynos_get_pll_clk()329 case RPLL: in exynos542x_get_pll_clk()538 sclk = exynos542x_get_pll_clk(RPLL); in exynos542x_get_periph_rate()1016 sclk = get_pll_clk(RPLL); in exynos5420_get_lcd_clk()1051 RPLL}; in exynos5800_get_lcd_clk()