1From e5d72ed8339eb05285448aad3c89d21e4d18fd29 Mon Sep 17 00:00:00 2001
2From: Luca Ceresoli <luca@lucaceresoli.net>
3Date: Mon, 26 Feb 2018 09:40:34 +0100
4Subject: [PATCH] arm64: zynqmp: zcu106: fix SPL MMC booting
5
6The U-Boot SPL generated with the current zcu106 defconfig cannot boot
7from MMC:
8
9  [...]
10  U-Boot SPL 2018.01 (Feb 21 2018 - 17:47:14)
11  EL Level:  EL3
12  Trying to boot from MMC1
13  sdhci_transfer_data: Error detected in status(0x408020)!
14  spl_load_image_fat_os: error reading image u-boot.bin, err - -2
15  spl_load_image_fat: error reading image u-boot.img, err - -6
16  SPL: failed to boot from all boot devices
17  ### ERROR ### Please RESET the board ###
18
19Fix by lowering the rpll value. The new value for the RPLL_CTRL
20register comes from the current psu_init_gpl.c from the HDF file at
21https://github.com/xilinx/hdf-examples/tree/01ad8ea5fd1989abf4ea5a072d019a16cb2bc546/zcu106-zynqmp
22(generated by Vivado v2017.4).
23
24RPLL and sdio1_ref clocks before and after this change:
25
26 - Old values: RPLL 1.36 GHz, sdio1_ref 272 MHz
27 - New values: RPLL 1.16 GHz, sdio1_ref 233 MHz
28
29Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
30Cc: Michal Simek <michal.simek@xilinx.com>
31Upstream-status: accepted upstream in a different form
32---
33
34 board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c | 2 +-
35 1 file changed, 1 insertion(+), 1 deletion(-)
36
37diff --git a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
38index 4d18abe000ca..e6fa477e53e7 100644
39--- a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
40+++ b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c
41@@ -10,7 +10,7 @@
42 static unsigned long psu_pll_init_data(void)
43 {
44 	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4E2C62U);
45-	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00013C00U);
46+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
47 	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
48 	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
49 	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
50--
512.7.4
52
53