1*4882a593SmuzhiyunFrom e5d72ed8339eb05285448aad3c89d21e4d18fd29 Mon Sep 17 00:00:00 2001 2*4882a593SmuzhiyunFrom: Luca Ceresoli <luca@lucaceresoli.net> 3*4882a593SmuzhiyunDate: Mon, 26 Feb 2018 09:40:34 +0100 4*4882a593SmuzhiyunSubject: [PATCH] arm64: zynqmp: zcu106: fix SPL MMC booting 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunThe U-Boot SPL generated with the current zcu106 defconfig cannot boot 7*4882a593Smuzhiyunfrom MMC: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun [...] 10*4882a593Smuzhiyun U-Boot SPL 2018.01 (Feb 21 2018 - 17:47:14) 11*4882a593Smuzhiyun EL Level: EL3 12*4882a593Smuzhiyun Trying to boot from MMC1 13*4882a593Smuzhiyun sdhci_transfer_data: Error detected in status(0x408020)! 14*4882a593Smuzhiyun spl_load_image_fat_os: error reading image u-boot.bin, err - -2 15*4882a593Smuzhiyun spl_load_image_fat: error reading image u-boot.img, err - -6 16*4882a593Smuzhiyun SPL: failed to boot from all boot devices 17*4882a593Smuzhiyun ### ERROR ### Please RESET the board ### 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunFix by lowering the rpll value. The new value for the RPLL_CTRL 20*4882a593Smuzhiyunregister comes from the current psu_init_gpl.c from the HDF file at 21*4882a593Smuzhiyunhttps://github.com/xilinx/hdf-examples/tree/01ad8ea5fd1989abf4ea5a072d019a16cb2bc546/zcu106-zynqmp 22*4882a593Smuzhiyun(generated by Vivado v2017.4). 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunRPLL and sdio1_ref clocks before and after this change: 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun - Old values: RPLL 1.36 GHz, sdio1_ref 272 MHz 27*4882a593Smuzhiyun - New values: RPLL 1.16 GHz, sdio1_ref 233 MHz 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunSigned-off-by: Luca Ceresoli <luca@lucaceresoli.net> 30*4882a593SmuzhiyunCc: Michal Simek <michal.simek@xilinx.com> 31*4882a593SmuzhiyunUpstream-status: accepted upstream in a different form 32*4882a593Smuzhiyun--- 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c | 2 +- 35*4882a593Smuzhiyun 1 file changed, 1 insertion(+), 1 deletion(-) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyundiff --git a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c 38*4882a593Smuzhiyunindex 4d18abe000ca..e6fa477e53e7 100644 39*4882a593Smuzhiyun--- a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c 40*4882a593Smuzhiyun+++ b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c 41*4882a593Smuzhiyun@@ -10,7 +10,7 @@ 42*4882a593Smuzhiyun static unsigned long psu_pll_init_data(void) 43*4882a593Smuzhiyun { 44*4882a593Smuzhiyun psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4E2C62U); 45*4882a593Smuzhiyun- psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00013C00U); 46*4882a593Smuzhiyun+ psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); 47*4882a593Smuzhiyun psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); 48*4882a593Smuzhiyun psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); 49*4882a593Smuzhiyun psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); 50*4882a593Smuzhiyun-- 51*4882a593Smuzhiyun2.7.4 52*4882a593Smuzhiyun 53