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Searched refs:PLL3 (Results 1 – 14 of 14) sorted by relevance

/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Dak4642.c113 #define PLL3 (1 << 7) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
357 pll = PLL3 | PLL2; in ak4642_dai_set_sysclk()
360 pll = PLL3 | PLL2 | PLL0; in ak4642_dai_set_sysclk()
363 pll = PLL3; in ak4642_dai_set_sysclk()
367 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dstm32mp1-clks.h185 #define PLL3 178 macro
H A Dqcom,gcc-ipq806x.h231 #define PLL3 222 macro
H A Dqcom,gcc-mdm9615.h288 #define PLL3 278 macro
H A Dqcom,gcc-msm8960.h286 #define PLL3 278 macro
/OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/
H A Dzl10039.c42 PLL3, enumerator
/OK3568_Linux_fs/u-boot/doc/
H A DREADME.Heterogeneous-SoCs55 PLL5, PLL3 is Reserved(as mentioned in RM), so this define contains the
/OK3568_Linux_fs/u-boot/drivers/video/tegra124/
H A Dsor.c566 DUMP_REG(PLL3); in dump_sor_reg()
707 tegra_sor_write_field(sor, PLL3, in tegra_dc_sor_enable_dp()
H A Dsor.h283 #define PLL3 0x1a macro
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath9k/
H A Dhw.c741 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
743 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
757 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; in ar9003_get_pll_sqsum_dvc()
H A Dreg.h1375 #define PLL3 0x16188 macro
/OK3568_Linux_fs/kernel/drivers/clk/qcom/
H A Dgcc-msm8960.c3142 [PLL3] = &pll3.clkr,
3370 [PLL3] = &pll3.clkr,
H A Dgcc-ipq806x.c2758 [PLL3] = &pll3.clkr,
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-stm32mp1.c1688 PLL(PLL3, "pll3", "ref3", CLK_IGNORE_UNUSED, RCC_PLL3CR),