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Searched refs:NPLL_HZ (Results 1 – 8 of 8) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3399.h84 #define NPLL_HZ (600 * MHz) macro
H A Dcru_rk3288.h17 #define NPLL_HZ (384 * 1000000) macro
H A Dcru_px30.h17 #define NPLL_HZ (1188 * MHz) macro
H A Dcru_rk3588.h18 #define NPLL_HZ (850 * MHz) macro
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3368.c60 #define NPLL_HZ (594 * 1000 * 1000) macro
776 if (!(NPLL_HZ % hz)) { in rk3368_vop_set_clk()
777 rkclk_set_pll(cru, NPLL, rkclk_get_pll_config(NPLL_HZ)); in rk3368_vop_set_clk()
778 lcdc_div = NPLL_HZ / hz; in rk3368_vop_set_clk()
1309 rkclk_set_pll(priv->cru, NPLL, rkclk_get_pll_config(NPLL_HZ)); in rk3368_clk_probe()
H A Dclk_rk3399.c57 static const struct pll_div npll_init_cfg = PLL_DIVISORS(NPLL_HZ, 1, 3, 1);
1412 if (rkclk_pll_get_rate(&cru->npll_con[0]) != NPLL_HZ) in rkclk_init()
H A Dclk_px30.c1921 if (npll_hz != NPLL_HZ) { in px30_clk_init()
1922 ret = px30_clk_set_pll_rate(cru_priv, NPLL, NPLL_HZ); in px30_clk_init()
H A Dclk_rk3288.c459 pll_rate = NPLL_HZ; in rockchip_mac_set_clk()