Searched refs:MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET (Results 1 – 11 of 11) sorted by relevance
447 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); in enable_lvds()535 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); in enable_spi_display()
164 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); in setup_display()
1421 reg |= ((7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET) in select_ldb_di_clock_source()1429 reg |= ((4 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET) in select_ldb_di_clock_source()1437 reg |= ((clk << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET) in select_ldb_di_clock_source()
558 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); in setup_display()
508 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); in setup_display()
588 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); in setup_display()
773 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); in setup_display()
448 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 macro
710 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); in setup_display()
644 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); in setup_display()
448 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); in setup_display()