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Searched refs:MCHBAR_REG (Results 1 – 9 of 9) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/video/
H A Divybridge_igd.c373 u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf; in gma_pm_init_pre_vbios()
381 u32 tdp = readl(MCHBAR_REG(0x5930)) & 0x7fff; in gma_pm_init_pre_vbios()
497 reg32 = readl(MCHBAR_REG(0x5998)); in gma_pm_init_pre_vbios()
753 reg32 = readl(MCHBAR_REG(0x5f00)); in sandybridge_setup_graphics()
755 writel(reg32, MCHBAR_REG(0x5f00)); in sandybridge_setup_graphics()
758 reg32 = readl(MCHBAR_REG(0x5f00)); in sandybridge_setup_graphics()
759 writel(reg32 | 1, MCHBAR_REG(0x5f00)); in sandybridge_setup_graphics()
762 reg32 = readl(MCHBAR_REG(0x5d14)); in sandybridge_setup_graphics()
764 writel(reg32, MCHBAR_REG(0x5d14)); in sandybridge_setup_graphics()
767 reg32 = readl(MCHBAR_REG(0x6120)); in sandybridge_setup_graphics()
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H A Dbroadwell_igd.c594 rp1_gfx_freq = (readl(MCHBAR_REG(0x5998)) >> 8) & 0xff; in igd_pre_init()
/OK3568_Linux_fs/u-boot/arch/x86/cpu/broadwell/
H A Dcpu.c172 if (!(readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) & in pcode_ready()
193 writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE)); in pcode_mailbox_read()
202 return readl(MCHBAR_REG(BIOS_MAILBOX_DATA)); in pcode_mailbox_read()
215 writel(data, MCHBAR_REG(BIOS_MAILBOX_DATA)); in pcode_mailbox_write()
218 writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE)); in pcode_mailbox_write()
312 writel(~0, MCHBAR_REG(BIOS_MAILBOX_DATA)); in calibrate_24mhz_bclk()
314 MCHBAR_REG(BIOS_MAILBOX_INTERFACE)); in calibrate_24mhz_bclk()
320 err_code = readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) & 0xff; in calibrate_24mhz_bclk()
326 MCHBAR_REG(BIOS_MAILBOX_INTERFACE)); in calibrate_24mhz_bclk()
333 readl(MCHBAR_REG(BIOS_MAILBOX_DATA))); in calibrate_24mhz_bclk()
[all …]
H A Dpch.c445 clrsetbits_8(MCHBAR_REG(MCH_PAIR), 0x7, 0x4); /* Fixed Priority */ in systemagent_init()
451 setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 3); in systemagent_init()
/OK3568_Linux_fs/u-boot/arch/x86/cpu/ivybridge/
H A Dnorthbridge.c125 bridge_type = readl(MCHBAR_REG(0x5f10)); in northbridge_init()
130 clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4); in northbridge_init()
138 writel(bridge_type, MCHBAR_REG(0x5f10)); in northbridge_init()
144 setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 1); in northbridge_init()
158 writel(msr.lo, MCHBAR_REG(0x59A0)); in northbridge_init()
159 writel(msr.hi, MCHBAR_REG(0x59A4)); in northbridge_init()
163 writel(0x00100001, MCHBAR_REG(0x5500)); in northbridge_init()
H A Dsdram.c198 setbits_le32(MCHBAR_REG(0x7010), 1); in post_system_agent_init()
551 writew(0xCAFE, MCHBAR_REG(SSKPD)); in dram_init()
H A Dcpu.c137 if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) { in checkcpu()
/OK3568_Linux_fs/u-boot/arch/x86/cpu/intel_common/
H A Dmrc.c102 addr_decoder_common = readl(MCHBAR_REG(0x5000)); in report_memory_config()
103 addr_decode_ch[0] = readl(MCHBAR_REG(0x5004)); in report_memory_config()
104 addr_decode_ch[1] = readl(MCHBAR_REG(0x5008)); in report_memory_config()
107 (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100); in report_memory_config()
241 version = readl(MCHBAR_REG(MCHBAR_PEI_VERSION)); in sdram_initialise()
/OK3568_Linux_fs/u-boot/arch/x86/include/asm/
H A Dintel_regs.h13 #define MCHBAR_REG(reg) (MCH_BASE_ADDRESS + (reg)) macro