1 /*
2 * From Coreboot northbridge/intel/sandybridge/northbridge.c
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 The Chromium Authors
6 *
7 * SPDX-License-Identifier: GPL-2.0
8 */
9
10 #include <common.h>
11 #include <dm.h>
12 #include <asm/msr.h>
13 #include <asm/cpu.h>
14 #include <asm/intel_regs.h>
15 #include <asm/io.h>
16 #include <asm/pci.h>
17 #include <asm/processor.h>
18 #include <asm/arch/pch.h>
19 #include <asm/arch/model_206ax.h>
20 #include <asm/arch/sandybridge.h>
21
22 DECLARE_GLOBAL_DATA_PTR;
23
bridge_silicon_revision(struct udevice * dev)24 int bridge_silicon_revision(struct udevice *dev)
25 {
26 struct cpuid_result result;
27 u16 bridge_id;
28 u8 stepping;
29
30 result = cpuid(1);
31 stepping = result.eax & 0xf;
32 dm_pci_read_config16(dev, PCI_DEVICE_ID, &bridge_id);
33 bridge_id &= 0xf0;
34 return bridge_id | stepping;
35 }
36
37 /*
38 * Reserve everything between A segment and 1MB:
39 *
40 * 0xa0000 - 0xbffff: legacy VGA
41 * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
42 * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
43 */
44 static const int legacy_hole_base_k = 0xa0000 / 1024;
45 static const int legacy_hole_size_k = 384;
46
get_pcie_bar(struct udevice * dev,u32 * base,u32 * len)47 static int get_pcie_bar(struct udevice *dev, u32 *base, u32 *len)
48 {
49 u32 pciexbar_reg;
50
51 *base = 0;
52 *len = 0;
53
54 dm_pci_read_config32(dev, PCIEXBAR, &pciexbar_reg);
55
56 if (!(pciexbar_reg & (1 << 0)))
57 return 0;
58
59 switch ((pciexbar_reg >> 1) & 3) {
60 case 0: /* 256MB */
61 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
62 (1 << 28));
63 *len = 256 * 1024 * 1024;
64 return 1;
65 case 1: /* 128M */
66 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
67 (1 << 28) | (1 << 27));
68 *len = 128 * 1024 * 1024;
69 return 1;
70 case 2: /* 64M */
71 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
72 (1 << 28) | (1 << 27) | (1 << 26));
73 *len = 64 * 1024 * 1024;
74 return 1;
75 }
76
77 return 0;
78 }
79
add_fixed_resources(struct udevice * dev,int index)80 static void add_fixed_resources(struct udevice *dev, int index)
81 {
82 u32 pcie_config_base, pcie_config_size;
83
84 if (get_pcie_bar(dev, &pcie_config_base, &pcie_config_size)) {
85 debug("Adding PCIe config bar base=0x%08x size=0x%x\n",
86 pcie_config_base, pcie_config_size);
87 }
88 }
89
northbridge_dmi_init(struct udevice * dev,int rev)90 static void northbridge_dmi_init(struct udevice *dev, int rev)
91 {
92 /* Clear error status bits */
93 writel(0xffffffff, DMIBAR_REG(0x1c4));
94 writel(0xffffffff, DMIBAR_REG(0x1d0));
95
96 /* Steps prior to DMI ASPM */
97 if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
98 clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20),
99 1 << 21);
100 }
101
102 setbits_le32(DMIBAR_REG(0x238), 1 << 29);
103
104 if (rev >= SNB_STEP_D0) {
105 setbits_le32(DMIBAR_REG(0x1f8), 1 << 16);
106 } else if (rev >= SNB_STEP_D1) {
107 clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16);
108 setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23));
109 }
110
111 /* Enable ASPM on SNB link, should happen before PCH link */
112 if ((rev & BASE_REV_MASK) == BASE_REV_SNB)
113 setbits_le32(DMIBAR_REG(0xd04), 1 << 4);
114
115 setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0));
116 }
117
northbridge_init(struct udevice * dev,int rev)118 static void northbridge_init(struct udevice *dev, int rev)
119 {
120 u32 bridge_type;
121
122 add_fixed_resources(dev, 6);
123 northbridge_dmi_init(dev, rev);
124
125 bridge_type = readl(MCHBAR_REG(0x5f10));
126 bridge_type &= ~0xff;
127
128 if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
129 /* Enable Power Aware Interrupt Routing - fixed priority */
130 clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4);
131
132 /* 30h for IvyBridge */
133 bridge_type |= 0x30;
134 } else {
135 /* 20h for Sandybridge */
136 bridge_type |= 0x20;
137 }
138 writel(bridge_type, MCHBAR_REG(0x5f10));
139
140 /*
141 * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU
142 * that BIOS has initialized memory and power management
143 */
144 setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 1);
145 debug("Set BIOS_RESET_CPL\n");
146
147 /* Configure turbo power limits 1ms after reset complete bit */
148 mdelay(1);
149 set_power_limits(28);
150
151 /*
152 * CPUs with configurable TDP also need power limits set
153 * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT.
154 */
155 if (cpu_config_tdp_levels()) {
156 msr_t msr = msr_read(MSR_PKG_POWER_LIMIT);
157
158 writel(msr.lo, MCHBAR_REG(0x59A0));
159 writel(msr.hi, MCHBAR_REG(0x59A4));
160 }
161
162 /* Set here before graphics PM init */
163 writel(0x00100001, MCHBAR_REG(0x5500));
164 }
165
sandybridge_setup_northbridge_bars(struct udevice * dev)166 static void sandybridge_setup_northbridge_bars(struct udevice *dev)
167 {
168 /* Set up all hardcoded northbridge BARs */
169 debug("Setting up static registers\n");
170 dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1);
171 dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
172 dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1);
173 dm_pci_write_config32(dev, MCHBAR + 4, (0LL + MCH_BASE_ADDRESS) >> 32);
174 /* 64MB - busses 0-63 */
175 dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
176 dm_pci_write_config32(dev, PCIEXBAR + 4,
177 (0LL + DEFAULT_PCIEXBAR) >> 32);
178 dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1);
179 dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32);
180
181 /* Set C0000-FFFFF to access RAM on both reads and writes */
182 dm_pci_write_config8(dev, PAM0, 0x30);
183 dm_pci_write_config8(dev, PAM1, 0x33);
184 dm_pci_write_config8(dev, PAM2, 0x33);
185 dm_pci_write_config8(dev, PAM3, 0x33);
186 dm_pci_write_config8(dev, PAM4, 0x33);
187 dm_pci_write_config8(dev, PAM5, 0x33);
188 dm_pci_write_config8(dev, PAM6, 0x33);
189 }
190
bd82x6x_northbridge_early_init(struct udevice * dev)191 static int bd82x6x_northbridge_early_init(struct udevice *dev)
192 {
193 const int chipset_type = SANDYBRIDGE_MOBILE;
194 u32 capid0_a;
195 u8 reg8;
196
197 /* Device ID Override Enable should be done very early */
198 dm_pci_read_config32(dev, 0xe4, &capid0_a);
199 if (capid0_a & (1 << 10)) {
200 dm_pci_read_config8(dev, 0xf3, ®8);
201 reg8 &= ~7; /* Clear 2:0 */
202
203 if (chipset_type == SANDYBRIDGE_MOBILE)
204 reg8 |= 1; /* Set bit 0 */
205
206 dm_pci_write_config8(dev, 0xf3, reg8);
207 }
208
209 sandybridge_setup_northbridge_bars(dev);
210
211 /* Device Enable */
212 dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
213
214 return 0;
215 }
216
bd82x6x_northbridge_probe(struct udevice * dev)217 static int bd82x6x_northbridge_probe(struct udevice *dev)
218 {
219 int rev;
220
221 if (!(gd->flags & GD_FLG_RELOC))
222 return bd82x6x_northbridge_early_init(dev);
223
224 rev = bridge_silicon_revision(dev);
225 northbridge_init(dev, rev);
226
227 return 0;
228 }
229
230 static const struct udevice_id bd82x6x_northbridge_ids[] = {
231 { .compatible = "intel,bd82x6x-northbridge" },
232 { }
233 };
234
235 U_BOOT_DRIVER(bd82x6x_northbridge_drv) = {
236 .name = "bd82x6x_northbridge",
237 .id = UCLASS_NORTHBRIDGE,
238 .of_match = bd82x6x_northbridge_ids,
239 .probe = bd82x6x_northbridge_probe,
240 };
241