1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2016 Google, Inc 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __ASM_INTEL_REGS_H 8*4882a593Smuzhiyun #define __ASM_INTEL_REGS_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* Access the memory-controller hub */ 11*4882a593Smuzhiyun #define MCH_BASE_ADDRESS 0xfed10000 12*4882a593Smuzhiyun #define MCH_BASE_SIZE 0x8000 13*4882a593Smuzhiyun #define MCHBAR_REG(reg) (MCH_BASE_ADDRESS + (reg)) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define MCHBAR_PEI_VERSION 0x5034 16*4882a593Smuzhiyun #define MCH_PKG_POWER_LIMIT_LO 0x59a0 17*4882a593Smuzhiyun #define MCH_PKG_POWER_LIMIT_HI 0x59a4 18*4882a593Smuzhiyun #define MCH_DDR_POWER_LIMIT_LO 0x58e0 19*4882a593Smuzhiyun #define MCH_DDR_POWER_LIMIT_HI 0x58e4 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* Access the Root Complex Register Block */ 22*4882a593Smuzhiyun #define RCB_BASE_ADDRESS 0xfed1c000 23*4882a593Smuzhiyun #define RCB_REG(reg) (RCB_BASE_ADDRESS + (reg)) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define SOFT_RESET_CTRL 0x38f4 26*4882a593Smuzhiyun #define SOFT_RESET_DATA 0x38f8 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #endif 29