Home
last modified time | relevance | path

Searched refs:MCFSIM_DACR0 (Results 1 – 10 of 10) sorted by relevance

/OK3568_Linux_fs/u-boot/board/freescale/m5253evbe/
H A Dm5253evbe.c40 mbar_writeLong(MCFSIM_DACR0, 0x00002320); in dram_init()
48 mbar_writeLong(MCFSIM_DACR0, 0x00002328); in dram_init()
56 mbar_writeLong(MCFSIM_DACR0, in dram_init()
57 mbar_readLong(MCFSIM_DACR0) | 0x8000); in dram_init()
64 mbar_writeLong(MCFSIM_DACR0, in dram_init()
65 mbar_readLong(MCFSIM_DACR0) | 0x0040); in dram_init()
/OK3568_Linux_fs/u-boot/board/freescale/m5253demo/
H A Dm5253demo.c43 mbar_writeLong(MCFSIM_DACR0, 0x00003224); in dram_init()
52 mbar_writeLong(MCFSIM_DACR0, 0x0000322c); in dram_init()
62 mbar_writeLong(MCFSIM_DACR0, in dram_init()
63 mbar_readLong(MCFSIM_DACR0) | 0x8000); in dram_init()
70 mbar_writeLong(MCFSIM_DACR0, in dram_init()
71 mbar_readLong(MCFSIM_DACR0) | 0x0040); in dram_init()
/OK3568_Linux_fs/u-boot/board/freescale/m5249evb/
H A Dm5249evb.c69 mbar_writeLong(MCFSIM_DACR0, 0x00003324); in dram_init()
75 mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */ in dram_init()
80 mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */ in dram_init()
84 mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ in dram_init()
/OK3568_Linux_fs/u-boot/arch/m68k/include/asm/
H A Dm5249.h65 #define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ macro
/OK3568_Linux_fs/kernel/arch/m68k/include/asm/
H A Dm5407sim.h78 #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ macro
H A Dm5307sim.h95 #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM Addr/Ctrl 0 */ macro
H A Dm523xsim.h64 #define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */ macro
H A Dm528xsim.h64 #define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */ macro
H A Dm525xsim.h72 #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ macro
H A Dm527xsim.h73 #define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */ macro