1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /****************************************************************************/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* 5*4882a593Smuzhiyun * m527xsim.h -- ColdFire 5270/5271 System Integration Module support. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com) 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /****************************************************************************/ 11*4882a593Smuzhiyun #ifndef m527xsim_h 12*4882a593Smuzhiyun #define m527xsim_h 13*4882a593Smuzhiyun /****************************************************************************/ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CPU_NAME "COLDFIRE(m527x)" 16*4882a593Smuzhiyun #define CPU_INSTR_PER_JIFFY 3 17*4882a593Smuzhiyun #define MCF_BUSCLK (MCF_CLK / 2) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #include <asm/m52xxacr.h> 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* 22*4882a593Smuzhiyun * Define the 5270/5271 SIM register set addresses. 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ 25*4882a593Smuzhiyun #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 28*4882a593Smuzhiyun #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 29*4882a593Smuzhiyun #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 30*4882a593Smuzhiyun #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 31*4882a593Smuzhiyun #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 32*4882a593Smuzhiyun #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 33*4882a593Smuzhiyun #define MCFINTC_IRLR 0x18 /* */ 34*4882a593Smuzhiyun #define MCFINTC_IACKL 0x19 /* */ 35*4882a593Smuzhiyun #define MCFINTC_ICR0 0x40 /* Base ICR register */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define MCFINT_VECBASE 64 /* Vector base number */ 38*4882a593Smuzhiyun #define MCFINT_UART0 13 /* Interrupt number for UART0 */ 39*4882a593Smuzhiyun #define MCFINT_UART1 14 /* Interrupt number for UART1 */ 40*4882a593Smuzhiyun #define MCFINT_UART2 15 /* Interrupt number for UART2 */ 41*4882a593Smuzhiyun #define MCFINT_I2C0 17 /* Interrupt number for I2C */ 42*4882a593Smuzhiyun #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ 43*4882a593Smuzhiyun #define MCFINT_FECRX0 23 /* Interrupt number for FEC0 */ 44*4882a593Smuzhiyun #define MCFINT_FECTX0 27 /* Interrupt number for FEC0 */ 45*4882a593Smuzhiyun #define MCFINT_FECENTC0 29 /* Interrupt number for FEC0 */ 46*4882a593Smuzhiyun #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define MCFINT2_VECBASE 128 /* Vector base number 2 */ 49*4882a593Smuzhiyun #define MCFINT2_FECRX1 23 /* Interrupt number for FEC1 */ 50*4882a593Smuzhiyun #define MCFINT2_FECTX1 27 /* Interrupt number for FEC1 */ 51*4882a593Smuzhiyun #define MCFINT2_FECENTC1 29 /* Interrupt number for FEC1 */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) 54*4882a593Smuzhiyun #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) 55*4882a593Smuzhiyun #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) 58*4882a593Smuzhiyun #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) 59*4882a593Smuzhiyun #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) 60*4882a593Smuzhiyun #define MCF_IRQ_FECRX1 (MCFINT2_VECBASE + MCFINT2_FECRX1) 61*4882a593Smuzhiyun #define MCF_IRQ_FECTX1 (MCFINT2_VECBASE + MCFINT2_FECTX1) 62*4882a593Smuzhiyun #define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 65*4882a593Smuzhiyun #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) 66*4882a593Smuzhiyun #define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* 69*4882a593Smuzhiyun * SDRAM configuration registers. 70*4882a593Smuzhiyun */ 71*4882a593Smuzhiyun #ifdef CONFIG_M5271 72*4882a593Smuzhiyun #define MCFSIM_DCR (MCF_IPSBAR + 0x40) /* Control */ 73*4882a593Smuzhiyun #define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */ 74*4882a593Smuzhiyun #define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */ 75*4882a593Smuzhiyun #define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */ 76*4882a593Smuzhiyun #define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */ 77*4882a593Smuzhiyun #endif 78*4882a593Smuzhiyun #ifdef CONFIG_M5275 79*4882a593Smuzhiyun #define MCFSIM_DMR (MCF_IPSBAR + 0x40) /* Mode */ 80*4882a593Smuzhiyun #define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */ 81*4882a593Smuzhiyun #define MCFSIM_DCFG1 (MCF_IPSBAR + 0x48) /* Configuration 1 */ 82*4882a593Smuzhiyun #define MCFSIM_DCFG2 (MCF_IPSBAR + 0x4c) /* Configuration 2 */ 83*4882a593Smuzhiyun #define MCFSIM_DBAR0 (MCF_IPSBAR + 0x50) /* Base address 0 */ 84*4882a593Smuzhiyun #define MCFSIM_DMR0 (MCF_IPSBAR + 0x54) /* Address mask 0 */ 85*4882a593Smuzhiyun #define MCFSIM_DBAR1 (MCF_IPSBAR + 0x58) /* Base address 1 */ 86*4882a593Smuzhiyun #define MCFSIM_DMR1 (MCF_IPSBAR + 0x5c) /* Address mask 1 */ 87*4882a593Smuzhiyun #endif 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* 90*4882a593Smuzhiyun * DMA unit base addresses. 91*4882a593Smuzhiyun */ 92*4882a593Smuzhiyun #define MCFDMA_BASE0 (MCF_IPSBAR + 0x100) 93*4882a593Smuzhiyun #define MCFDMA_BASE1 (MCF_IPSBAR + 0x140) 94*4882a593Smuzhiyun #define MCFDMA_BASE2 (MCF_IPSBAR + 0x180) 95*4882a593Smuzhiyun #define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* 98*4882a593Smuzhiyun * UART module. 99*4882a593Smuzhiyun */ 100*4882a593Smuzhiyun #define MCFUART_BASE0 (MCF_IPSBAR + 0x200) 101*4882a593Smuzhiyun #define MCFUART_BASE1 (MCF_IPSBAR + 0x240) 102*4882a593Smuzhiyun #define MCFUART_BASE2 (MCF_IPSBAR + 0x280) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* 105*4882a593Smuzhiyun * FEC ethernet module. 106*4882a593Smuzhiyun */ 107*4882a593Smuzhiyun #define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000) 108*4882a593Smuzhiyun #define MCFFEC_SIZE0 0x800 109*4882a593Smuzhiyun #ifdef CONFIG_M5275 110*4882a593Smuzhiyun #define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800) 111*4882a593Smuzhiyun #define MCFFEC_SIZE1 0x800 112*4882a593Smuzhiyun #endif 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* 115*4882a593Smuzhiyun * QSPI module. 116*4882a593Smuzhiyun */ 117*4882a593Smuzhiyun #define MCFQSPI_BASE (MCF_IPSBAR + 0x340) 118*4882a593Smuzhiyun #define MCFQSPI_SIZE 0x40 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #ifdef CONFIG_M5271 121*4882a593Smuzhiyun #define MCFQSPI_CS0 91 122*4882a593Smuzhiyun #define MCFQSPI_CS1 92 123*4882a593Smuzhiyun #define MCFQSPI_CS2 99 124*4882a593Smuzhiyun #define MCFQSPI_CS3 103 125*4882a593Smuzhiyun #endif 126*4882a593Smuzhiyun #ifdef CONFIG_M5275 127*4882a593Smuzhiyun #define MCFQSPI_CS0 59 128*4882a593Smuzhiyun #define MCFQSPI_CS1 60 129*4882a593Smuzhiyun #define MCFQSPI_CS2 61 130*4882a593Smuzhiyun #define MCFQSPI_CS3 62 131*4882a593Smuzhiyun #endif 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun /* 134*4882a593Smuzhiyun * GPIO module. 135*4882a593Smuzhiyun */ 136*4882a593Smuzhiyun #ifdef CONFIG_M5271 137*4882a593Smuzhiyun #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) 138*4882a593Smuzhiyun #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) 139*4882a593Smuzhiyun #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) 140*4882a593Smuzhiyun #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003) 141*4882a593Smuzhiyun #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004) 142*4882a593Smuzhiyun #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005) 143*4882a593Smuzhiyun #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006) 144*4882a593Smuzhiyun #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007) 145*4882a593Smuzhiyun #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008) 146*4882a593Smuzhiyun #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009) 147*4882a593Smuzhiyun #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A) 148*4882a593Smuzhiyun #define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B) 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010) 151*4882a593Smuzhiyun #define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011) 152*4882a593Smuzhiyun #define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012) 153*4882a593Smuzhiyun #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013) 154*4882a593Smuzhiyun #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014) 155*4882a593Smuzhiyun #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015) 156*4882a593Smuzhiyun #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016) 157*4882a593Smuzhiyun #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017) 158*4882a593Smuzhiyun #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018) 159*4882a593Smuzhiyun #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019) 160*4882a593Smuzhiyun #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A) 161*4882a593Smuzhiyun #define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B) 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020) 164*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021) 165*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022) 166*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023) 167*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024) 168*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025) 169*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026) 170*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027) 171*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028) 172*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029) 173*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A) 174*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B) 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030) 177*4882a593Smuzhiyun #define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031) 178*4882a593Smuzhiyun #define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032) 179*4882a593Smuzhiyun #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033) 180*4882a593Smuzhiyun #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034) 181*4882a593Smuzhiyun #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035) 182*4882a593Smuzhiyun #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036) 183*4882a593Smuzhiyun #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037) 184*4882a593Smuzhiyun #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038) 185*4882a593Smuzhiyun #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039) 186*4882a593Smuzhiyun #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A) 187*4882a593Smuzhiyun #define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B) 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun /* 190*4882a593Smuzhiyun * Generic GPIO support 191*4882a593Smuzhiyun */ 192*4882a593Smuzhiyun #define MCFGPIO_PODR MCFGPIO_PODR_ADDR 193*4882a593Smuzhiyun #define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR 194*4882a593Smuzhiyun #define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR 195*4882a593Smuzhiyun #define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR 196*4882a593Smuzhiyun #define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun #define MCFGPIO_PIN_MAX 100 199*4882a593Smuzhiyun #define MCFGPIO_IRQ_MAX 8 200*4882a593Smuzhiyun #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun /* 203*4882a593Smuzhiyun * Port Pin Assignment registers. 204*4882a593Smuzhiyun */ 205*4882a593Smuzhiyun #define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040) 206*4882a593Smuzhiyun #define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042) 207*4882a593Smuzhiyun #define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044) 208*4882a593Smuzhiyun #define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045) 209*4882a593Smuzhiyun #define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100046) 210*4882a593Smuzhiyun #define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047) 211*4882a593Smuzhiyun #define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x100048) 212*4882a593Smuzhiyun #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) 213*4882a593Smuzhiyun #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun #define UART0_ENABLE_MASK 0x000f 216*4882a593Smuzhiyun #define UART1_ENABLE_MASK 0x0ff0 217*4882a593Smuzhiyun #define UART2_ENABLE_MASK 0x3000 218*4882a593Smuzhiyun #endif /* CONFIG_M5271 */ 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun #ifdef CONFIG_M5275 221*4882a593Smuzhiyun #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004) 222*4882a593Smuzhiyun #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100005) 223*4882a593Smuzhiyun #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100008) 224*4882a593Smuzhiyun #define MCFGPIO_PODR_FEC0H (MCF_IPSBAR + 0x10000A) 225*4882a593Smuzhiyun #define MCFGPIO_PODR_FEC0L (MCF_IPSBAR + 0x10000B) 226*4882a593Smuzhiyun #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x10000C) 227*4882a593Smuzhiyun #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000D) 228*4882a593Smuzhiyun #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x10000E) 229*4882a593Smuzhiyun #define MCFGPIO_PODR_TIMERH (MCF_IPSBAR + 0x10000F) 230*4882a593Smuzhiyun #define MCFGPIO_PODR_TIMERL (MCF_IPSBAR + 0x100010) 231*4882a593Smuzhiyun #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100011) 232*4882a593Smuzhiyun #define MCFGPIO_PODR_FEC1H (MCF_IPSBAR + 0x100012) 233*4882a593Smuzhiyun #define MCFGPIO_PODR_FEC1L (MCF_IPSBAR + 0x100013) 234*4882a593Smuzhiyun #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100014) 235*4882a593Smuzhiyun #define MCFGPIO_PODR_IRQ (MCF_IPSBAR + 0x100015) 236*4882a593Smuzhiyun #define MCFGPIO_PODR_USBH (MCF_IPSBAR + 0x100016) 237*4882a593Smuzhiyun #define MCFGPIO_PODR_USBL (MCF_IPSBAR + 0x100017) 238*4882a593Smuzhiyun #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100018) 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100020) 241*4882a593Smuzhiyun #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100021) 242*4882a593Smuzhiyun #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100024) 243*4882a593Smuzhiyun #define MCFGPIO_PDDR_FEC0H (MCF_IPSBAR + 0x100026) 244*4882a593Smuzhiyun #define MCFGPIO_PDDR_FEC0L (MCF_IPSBAR + 0x100027) 245*4882a593Smuzhiyun #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100028) 246*4882a593Smuzhiyun #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x100029) 247*4882a593Smuzhiyun #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x10002A) 248*4882a593Smuzhiyun #define MCFGPIO_PDDR_TIMERH (MCF_IPSBAR + 0x10002B) 249*4882a593Smuzhiyun #define MCFGPIO_PDDR_TIMERL (MCF_IPSBAR + 0x10002C) 250*4882a593Smuzhiyun #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x10002D) 251*4882a593Smuzhiyun #define MCFGPIO_PDDR_FEC1H (MCF_IPSBAR + 0x10002E) 252*4882a593Smuzhiyun #define MCFGPIO_PDDR_FEC1L (MCF_IPSBAR + 0x10002F) 253*4882a593Smuzhiyun #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100030) 254*4882a593Smuzhiyun #define MCFGPIO_PDDR_IRQ (MCF_IPSBAR + 0x100031) 255*4882a593Smuzhiyun #define MCFGPIO_PDDR_USBH (MCF_IPSBAR + 0x100032) 256*4882a593Smuzhiyun #define MCFGPIO_PDDR_USBL (MCF_IPSBAR + 0x100033) 257*4882a593Smuzhiyun #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100034) 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x10003C) 260*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x10003D) 261*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100040) 262*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_FEC0H (MCF_IPSBAR + 0x100042) 263*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_FEC0L (MCF_IPSBAR + 0x100043) 264*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100044) 265*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x100045) 266*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100046) 267*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_TIMERH (MCF_IPSBAR + 0x100047) 268*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_TIMERL (MCF_IPSBAR + 0x100048) 269*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100049) 270*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_FEC1H (MCF_IPSBAR + 0x10004A) 271*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_FEC1L (MCF_IPSBAR + 0x10004B) 272*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x10004C) 273*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_IRQ (MCF_IPSBAR + 0x10004D) 274*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_USBH (MCF_IPSBAR + 0x10004E) 275*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_USBL (MCF_IPSBAR + 0x10004F) 276*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100050) 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100058) 279*4882a593Smuzhiyun #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100059) 280*4882a593Smuzhiyun #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x10005C) 281*4882a593Smuzhiyun #define MCFGPIO_PCLRR_FEC0H (MCF_IPSBAR + 0x10005E) 282*4882a593Smuzhiyun #define MCFGPIO_PCLRR_FEC0L (MCF_IPSBAR + 0x10005F) 283*4882a593Smuzhiyun #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100060) 284*4882a593Smuzhiyun #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x100061) 285*4882a593Smuzhiyun #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100062) 286*4882a593Smuzhiyun #define MCFGPIO_PCLRR_TIMERH (MCF_IPSBAR + 0x100063) 287*4882a593Smuzhiyun #define MCFGPIO_PCLRR_TIMERL (MCF_IPSBAR + 0x100064) 288*4882a593Smuzhiyun #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100065) 289*4882a593Smuzhiyun #define MCFGPIO_PCLRR_FEC1H (MCF_IPSBAR + 0x100066) 290*4882a593Smuzhiyun #define MCFGPIO_PCLRR_FEC1L (MCF_IPSBAR + 0x100067) 291*4882a593Smuzhiyun #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100068) 292*4882a593Smuzhiyun #define MCFGPIO_PCLRR_IRQ (MCF_IPSBAR + 0x100069) 293*4882a593Smuzhiyun #define MCFGPIO_PCLRR_USBH (MCF_IPSBAR + 0x10006A) 294*4882a593Smuzhiyun #define MCFGPIO_PCLRR_USBL (MCF_IPSBAR + 0x10006B) 295*4882a593Smuzhiyun #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x10006C) 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun /* 299*4882a593Smuzhiyun * Generic GPIO support 300*4882a593Smuzhiyun */ 301*4882a593Smuzhiyun #define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL 302*4882a593Smuzhiyun #define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL 303*4882a593Smuzhiyun #define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL 304*4882a593Smuzhiyun #define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL 305*4882a593Smuzhiyun #define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun #define MCFGPIO_PIN_MAX 148 308*4882a593Smuzhiyun #define MCFGPIO_IRQ_MAX 8 309*4882a593Smuzhiyun #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun /* 312*4882a593Smuzhiyun * Port Pin Assignment registers. 313*4882a593Smuzhiyun */ 314*4882a593Smuzhiyun #define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100070) 315*4882a593Smuzhiyun #define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100071) 316*4882a593Smuzhiyun #define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100072) 317*4882a593Smuzhiyun #define MCFGPIO_PAR_USB (MCF_IPSBAR + 0x100076) 318*4882a593Smuzhiyun #define MCFGPIO_PAR_FEC0HL (MCF_IPSBAR + 0x100078) 319*4882a593Smuzhiyun #define MCFGPIO_PAR_FEC1HL (MCF_IPSBAR + 0x100079) 320*4882a593Smuzhiyun #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10007A) 321*4882a593Smuzhiyun #define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x10007C) 322*4882a593Smuzhiyun #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E) 323*4882a593Smuzhiyun #define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100080) 324*4882a593Smuzhiyun #define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100082) 325*4882a593Smuzhiyun #define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100084) 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun #define UART0_ENABLE_MASK 0x000f 328*4882a593Smuzhiyun #define UART1_ENABLE_MASK 0x00f0 329*4882a593Smuzhiyun #define UART2_ENABLE_MASK 0x3f00 330*4882a593Smuzhiyun #endif /* CONFIG_M5275 */ 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun /* 333*4882a593Smuzhiyun * PIT timer base addresses. 334*4882a593Smuzhiyun */ 335*4882a593Smuzhiyun #define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000) 336*4882a593Smuzhiyun #define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000) 337*4882a593Smuzhiyun #define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000) 338*4882a593Smuzhiyun #define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000) 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun /* 341*4882a593Smuzhiyun * EPort 342*4882a593Smuzhiyun */ 343*4882a593Smuzhiyun #define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000) 344*4882a593Smuzhiyun #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) 345*4882a593Smuzhiyun #define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003) 346*4882a593Smuzhiyun #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) 347*4882a593Smuzhiyun #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) 348*4882a593Smuzhiyun #define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun /* 351*4882a593Smuzhiyun * Reset Control Unit (relative to IPSBAR). 352*4882a593Smuzhiyun */ 353*4882a593Smuzhiyun #define MCF_RCR (MCF_IPSBAR + 0x110000) 354*4882a593Smuzhiyun #define MCF_RSR (MCF_IPSBAR + 0x110001) 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 357*4882a593Smuzhiyun #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun /* 360*4882a593Smuzhiyun * I2C module. 361*4882a593Smuzhiyun */ 362*4882a593Smuzhiyun #define MCFI2C_BASE0 (MCF_IPSBAR + 0x300) 363*4882a593Smuzhiyun #define MCFI2C_SIZE0 0x40 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun /****************************************************************************/ 366*4882a593Smuzhiyun #endif /* m527xsim_h */ 367