1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2000-2003
3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6*4882a593Smuzhiyun * Hayden Fraser (Hayden.Fraser@freescale.com)
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <common.h>
12*4882a593Smuzhiyun #include <asm/immap.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
16*4882a593Smuzhiyun
checkboard(void)17*4882a593Smuzhiyun int checkboard(void)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun puts("Board: ");
20*4882a593Smuzhiyun puts("Freescale MCF5253 EVBE\n");
21*4882a593Smuzhiyun return 0;
22*4882a593Smuzhiyun };
23*4882a593Smuzhiyun
dram_init(void)24*4882a593Smuzhiyun int dram_init(void)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun /*
27*4882a593Smuzhiyun * Check to see if the SDRAM has already been initialized
28*4882a593Smuzhiyun * by a run control tool
29*4882a593Smuzhiyun */
30*4882a593Smuzhiyun if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
31*4882a593Smuzhiyun u32 RC, dramsize;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun RC = (CONFIG_SYS_CLK / 1000000) >> 1;
34*4882a593Smuzhiyun RC = (RC * 15) >> 4;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* Initialize DRAM Control Register: DCR */
37*4882a593Smuzhiyun mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
38*4882a593Smuzhiyun asm("nop");
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun mbar_writeLong(MCFSIM_DACR0, 0x00002320);
41*4882a593Smuzhiyun asm("nop");
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* Initialize DMR0 */
44*4882a593Smuzhiyun dramsize = ((CONFIG_SYS_SDRAM_SIZE << 20) - 1) & 0xFFFC0000;
45*4882a593Smuzhiyun mbar_writeLong(MCFSIM_DMR0, dramsize | 1);
46*4882a593Smuzhiyun asm("nop");
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun mbar_writeLong(MCFSIM_DACR0, 0x00002328);
49*4882a593Smuzhiyun asm("nop");
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* Write to this block to initiate precharge */
52*4882a593Smuzhiyun *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
53*4882a593Smuzhiyun asm("nop");
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* Set RE bit in DACR */
56*4882a593Smuzhiyun mbar_writeLong(MCFSIM_DACR0,
57*4882a593Smuzhiyun mbar_readLong(MCFSIM_DACR0) | 0x8000);
58*4882a593Smuzhiyun asm("nop");
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* Wait for at least 8 auto refresh cycles to occur */
61*4882a593Smuzhiyun udelay(500);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* Finish the configuration by issuing the MRS */
64*4882a593Smuzhiyun mbar_writeLong(MCFSIM_DACR0,
65*4882a593Smuzhiyun mbar_readLong(MCFSIM_DACR0) | 0x0040);
66*4882a593Smuzhiyun asm("nop");
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun return 0;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
testdram(void)76*4882a593Smuzhiyun int testdram(void)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun /* TODO: XXX XXX XXX */
79*4882a593Smuzhiyun printf("DRAM test not implemented!\n");
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun return (0);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun #ifdef CONFIG_IDE
85*4882a593Smuzhiyun #include <ata.h>
ide_preinit(void)86*4882a593Smuzhiyun int ide_preinit(void)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun return (0);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
ide_set_reset(int idereset)91*4882a593Smuzhiyun void ide_set_reset(int idereset)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
94*4882a593Smuzhiyun long period;
95*4882a593Smuzhiyun /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
96*4882a593Smuzhiyun int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
97*4882a593Smuzhiyun {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
98*4882a593Smuzhiyun {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
99*4882a593Smuzhiyun {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
100*4882a593Smuzhiyun {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun if (idereset) {
104*4882a593Smuzhiyun /* control reset */
105*4882a593Smuzhiyun out_8(&ata->cr, 0);
106*4882a593Smuzhiyun udelay(100);
107*4882a593Smuzhiyun } else {
108*4882a593Smuzhiyun mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun #define CALC_TIMING(t) (t + period - 1) / period
111*4882a593Smuzhiyun period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /*ata->ton = CALC_TIMING (180); */
114*4882a593Smuzhiyun out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
115*4882a593Smuzhiyun out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
116*4882a593Smuzhiyun out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
117*4882a593Smuzhiyun out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
118*4882a593Smuzhiyun out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
119*4882a593Smuzhiyun out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
120*4882a593Smuzhiyun out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun /* IORDY enable */
123*4882a593Smuzhiyun out_8(&ata->cr, 0x40);
124*4882a593Smuzhiyun udelay(2000);
125*4882a593Smuzhiyun /* IORDY enable */
126*4882a593Smuzhiyun setbits_8(&ata->cr, 0x01);
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun #endif /* CONFIG_IDE */
130