1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2004
3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <command.h>
10*4882a593Smuzhiyun #include <malloc.h>
11*4882a593Smuzhiyun #include <asm/immap.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
14*4882a593Smuzhiyun
checkboard(void)15*4882a593Smuzhiyun int checkboard (void) {
16*4882a593Smuzhiyun ulong val;
17*4882a593Smuzhiyun uchar val8;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun puts ("Board: ");
20*4882a593Smuzhiyun puts("Freescale M5249EVB");
21*4882a593Smuzhiyun val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf;
22*4882a593Smuzhiyun printf(" (Switch=%1X)\n", val8);
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /*
25*4882a593Smuzhiyun * Set LED on
26*4882a593Smuzhiyun */
27*4882a593Smuzhiyun val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
28*4882a593Smuzhiyun mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun return 0;
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun
dram_init(void)34*4882a593Smuzhiyun int dram_init(void)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun unsigned long junk = 0xa5a59696;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /*
39*4882a593Smuzhiyun * Note:
40*4882a593Smuzhiyun * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #ifdef CONFIG_SYS_FAST_CLK
44*4882a593Smuzhiyun /*
45*4882a593Smuzhiyun * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
46*4882a593Smuzhiyun * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
47*4882a593Smuzhiyun */
48*4882a593Smuzhiyun mbar_writeShort(MCFSIM_DCR, 0x8239);
49*4882a593Smuzhiyun #elif CONFIG_SYS_PLL_BYPASS
50*4882a593Smuzhiyun /*
51*4882a593Smuzhiyun * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
52*4882a593Smuzhiyun * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
53*4882a593Smuzhiyun */
54*4882a593Smuzhiyun mbar_writeShort(MCFSIM_DCR, 0x8202);
55*4882a593Smuzhiyun #else
56*4882a593Smuzhiyun /*
57*4882a593Smuzhiyun * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K)
58*4882a593Smuzhiyun * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles)
59*4882a593Smuzhiyun */
60*4882a593Smuzhiyun mbar_writeShort(MCFSIM_DCR, 0x8222);
61*4882a593Smuzhiyun #endif
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /*
64*4882a593Smuzhiyun * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port),
65*4882a593Smuzhiyun * PM=1 (continuous page mode)
66*4882a593Smuzhiyun */
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* RE=0 (keep auto-refresh disabled while setting up registers) */
69*4882a593Smuzhiyun mbar_writeLong(MCFSIM_DACR0, 0x00003324);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */
72*4882a593Smuzhiyun mbar_writeLong(MCFSIM_DMR0, 0x01fc0001);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /** Precharge sequence **/
75*4882a593Smuzhiyun mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
76*4882a593Smuzhiyun *((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */
77*4882a593Smuzhiyun udelay(0x10); /* Allow several Precharge cycles */
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /** Refresh Sequence **/
80*4882a593Smuzhiyun mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */
81*4882a593Smuzhiyun udelay(0x7d0); /* Allow gobs of refresh cycles */
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /** Mode Register initialization **/
84*4882a593Smuzhiyun mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
85*4882a593Smuzhiyun *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun return 0;
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun
testdram(void)93*4882a593Smuzhiyun int testdram (void) {
94*4882a593Smuzhiyun /* TODO: XXX XXX XXX */
95*4882a593Smuzhiyun printf ("DRAM test not implemented!\n");
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun return (0);
98*4882a593Smuzhiyun }
99