1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /****************************************************************************/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* 5*4882a593Smuzhiyun * m523xsim.h -- ColdFire 523x System Integration Module support. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * (C) Copyright 2003-2005, Greg Ungerer <gerg@snapgear.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /****************************************************************************/ 11*4882a593Smuzhiyun #ifndef m523xsim_h 12*4882a593Smuzhiyun #define m523xsim_h 13*4882a593Smuzhiyun /****************************************************************************/ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CPU_NAME "COLDFIRE(m523x)" 16*4882a593Smuzhiyun #define CPU_INSTR_PER_JIFFY 3 17*4882a593Smuzhiyun #define MCF_BUSCLK (MCF_CLK / 2) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #include <asm/m52xxacr.h> 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* 22*4882a593Smuzhiyun * Define the 523x SIM register set addresses. 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ 25*4882a593Smuzhiyun #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 28*4882a593Smuzhiyun #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 29*4882a593Smuzhiyun #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 30*4882a593Smuzhiyun #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 31*4882a593Smuzhiyun #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 32*4882a593Smuzhiyun #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 33*4882a593Smuzhiyun #define MCFINTC_IRLR 0x18 /* */ 34*4882a593Smuzhiyun #define MCFINTC_IACKL 0x19 /* */ 35*4882a593Smuzhiyun #define MCFINTC_ICR0 0x40 /* Base ICR register */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define MCFINT_VECBASE 64 /* Vector base number */ 38*4882a593Smuzhiyun #define MCFINT_UART0 13 /* Interrupt number for UART0 */ 39*4882a593Smuzhiyun #define MCFINT_UART1 14 /* Interrupt number for UART1 */ 40*4882a593Smuzhiyun #define MCFINT_UART2 15 /* Interrupt number for UART2 */ 41*4882a593Smuzhiyun #define MCFINT_I2C0 17 /* Interrupt number for I2C */ 42*4882a593Smuzhiyun #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ 43*4882a593Smuzhiyun #define MCFINT_FECRX0 23 /* Interrupt number for FEC */ 44*4882a593Smuzhiyun #define MCFINT_FECTX0 27 /* Interrupt number for FEC */ 45*4882a593Smuzhiyun #define MCFINT_FECENTC0 29 /* Interrupt number for FEC */ 46*4882a593Smuzhiyun #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) 49*4882a593Smuzhiyun #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) 50*4882a593Smuzhiyun #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) 53*4882a593Smuzhiyun #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) 54*4882a593Smuzhiyun #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 57*4882a593Smuzhiyun #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) 58*4882a593Smuzhiyun #define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* 61*4882a593Smuzhiyun * SDRAM configuration registers. 62*4882a593Smuzhiyun */ 63*4882a593Smuzhiyun #define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */ 64*4882a593Smuzhiyun #define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */ 65*4882a593Smuzhiyun #define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */ 66*4882a593Smuzhiyun #define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */ 67*4882a593Smuzhiyun #define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* 70*4882a593Smuzhiyun * Reset Control Unit (relative to IPSBAR). 71*4882a593Smuzhiyun */ 72*4882a593Smuzhiyun #define MCF_RCR (MCF_IPSBAR + 0x110000) 73*4882a593Smuzhiyun #define MCF_RSR (MCF_IPSBAR + 0x110001) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 76*4882a593Smuzhiyun #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* 79*4882a593Smuzhiyun * UART module. 80*4882a593Smuzhiyun */ 81*4882a593Smuzhiyun #define MCFUART_BASE0 (MCF_IPSBAR + 0x200) 82*4882a593Smuzhiyun #define MCFUART_BASE1 (MCF_IPSBAR + 0x240) 83*4882a593Smuzhiyun #define MCFUART_BASE2 (MCF_IPSBAR + 0x280) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* 86*4882a593Smuzhiyun * FEC ethernet module. 87*4882a593Smuzhiyun */ 88*4882a593Smuzhiyun #define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000) 89*4882a593Smuzhiyun #define MCFFEC_SIZE0 0x800 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* 92*4882a593Smuzhiyun * QSPI module. 93*4882a593Smuzhiyun */ 94*4882a593Smuzhiyun #define MCFQSPI_BASE (MCF_IPSBAR + 0x340) 95*4882a593Smuzhiyun #define MCFQSPI_SIZE 0x40 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define MCFQSPI_CS0 91 98*4882a593Smuzhiyun #define MCFQSPI_CS1 92 99*4882a593Smuzhiyun #define MCFQSPI_CS2 103 100*4882a593Smuzhiyun #define MCFQSPI_CS3 99 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* 103*4882a593Smuzhiyun * GPIO module. 104*4882a593Smuzhiyun */ 105*4882a593Smuzhiyun #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) 106*4882a593Smuzhiyun #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) 107*4882a593Smuzhiyun #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) 108*4882a593Smuzhiyun #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003) 109*4882a593Smuzhiyun #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004) 110*4882a593Smuzhiyun #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005) 111*4882a593Smuzhiyun #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006) 112*4882a593Smuzhiyun #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007) 113*4882a593Smuzhiyun #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008) 114*4882a593Smuzhiyun #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009) 115*4882a593Smuzhiyun #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A) 116*4882a593Smuzhiyun #define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B) 117*4882a593Smuzhiyun #define MCFGPIO_PODR_ETPU (MCF_IPSBAR + 0x10000C) 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010) 120*4882a593Smuzhiyun #define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011) 121*4882a593Smuzhiyun #define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012) 122*4882a593Smuzhiyun #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013) 123*4882a593Smuzhiyun #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014) 124*4882a593Smuzhiyun #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015) 125*4882a593Smuzhiyun #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016) 126*4882a593Smuzhiyun #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017) 127*4882a593Smuzhiyun #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018) 128*4882a593Smuzhiyun #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019) 129*4882a593Smuzhiyun #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A) 130*4882a593Smuzhiyun #define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B) 131*4882a593Smuzhiyun #define MCFGPIO_PDDR_ETPU (MCF_IPSBAR + 0x10001C) 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020) 134*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021) 135*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022) 136*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023) 137*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024) 138*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025) 139*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026) 140*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027) 141*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028) 142*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029) 143*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A) 144*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B) 145*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_ETPU (MCF_IPSBAR + 0x10002C) 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030) 148*4882a593Smuzhiyun #define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031) 149*4882a593Smuzhiyun #define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032) 150*4882a593Smuzhiyun #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033) 151*4882a593Smuzhiyun #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034) 152*4882a593Smuzhiyun #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035) 153*4882a593Smuzhiyun #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036) 154*4882a593Smuzhiyun #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037) 155*4882a593Smuzhiyun #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038) 156*4882a593Smuzhiyun #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039) 157*4882a593Smuzhiyun #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A) 158*4882a593Smuzhiyun #define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B) 159*4882a593Smuzhiyun #define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C) 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* 162*4882a593Smuzhiyun * PIT timer base addresses. 163*4882a593Smuzhiyun */ 164*4882a593Smuzhiyun #define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000) 165*4882a593Smuzhiyun #define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000) 166*4882a593Smuzhiyun #define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000) 167*4882a593Smuzhiyun #define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000) 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun /* 170*4882a593Smuzhiyun * EPort 171*4882a593Smuzhiyun */ 172*4882a593Smuzhiyun #define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000) 173*4882a593Smuzhiyun #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) 174*4882a593Smuzhiyun #define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003) 175*4882a593Smuzhiyun #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) 176*4882a593Smuzhiyun #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) 177*4882a593Smuzhiyun #define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun /* 180*4882a593Smuzhiyun * Generic GPIO support 181*4882a593Smuzhiyun */ 182*4882a593Smuzhiyun #define MCFGPIO_PODR MCFGPIO_PODR_ADDR 183*4882a593Smuzhiyun #define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR 184*4882a593Smuzhiyun #define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR 185*4882a593Smuzhiyun #define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR 186*4882a593Smuzhiyun #define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun #define MCFGPIO_PIN_MAX 107 189*4882a593Smuzhiyun #define MCFGPIO_IRQ_MAX 8 190*4882a593Smuzhiyun #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun /* 193*4882a593Smuzhiyun * Pin Assignment 194*4882a593Smuzhiyun */ 195*4882a593Smuzhiyun #define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040) 196*4882a593Smuzhiyun #define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042) 197*4882a593Smuzhiyun #define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044) 198*4882a593Smuzhiyun #define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045) 199*4882a593Smuzhiyun #define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100046) 200*4882a593Smuzhiyun #define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047) 201*4882a593Smuzhiyun #define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x100048) 202*4882a593Smuzhiyun #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) 203*4882a593Smuzhiyun #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) 204*4882a593Smuzhiyun #define MCFGPIO_PAR_ETPU (MCF_IPSBAR + 0x10004E) 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun /* 207*4882a593Smuzhiyun * DMA unit base addresses. 208*4882a593Smuzhiyun */ 209*4882a593Smuzhiyun #define MCFDMA_BASE0 (MCF_IPSBAR + 0x100) 210*4882a593Smuzhiyun #define MCFDMA_BASE1 (MCF_IPSBAR + 0x140) 211*4882a593Smuzhiyun #define MCFDMA_BASE2 (MCF_IPSBAR + 0x180) 212*4882a593Smuzhiyun #define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0) 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun /* 215*4882a593Smuzhiyun * I2C module. 216*4882a593Smuzhiyun */ 217*4882a593Smuzhiyun #define MCFI2C_BASE0 (MCF_IPSBAR + 0x300) 218*4882a593Smuzhiyun #define MCFI2C_SIZE0 0x40 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun /****************************************************************************/ 221*4882a593Smuzhiyun #endif /* m523xsim_h */ 222