1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /****************************************************************************/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* 5*4882a593Smuzhiyun * m528xsim.h -- ColdFire 5280/5282 System Integration Module support. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com) 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /****************************************************************************/ 11*4882a593Smuzhiyun #ifndef m528xsim_h 12*4882a593Smuzhiyun #define m528xsim_h 13*4882a593Smuzhiyun /****************************************************************************/ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CPU_NAME "COLDFIRE(m528x)" 16*4882a593Smuzhiyun #define CPU_INSTR_PER_JIFFY 3 17*4882a593Smuzhiyun #define MCF_BUSCLK MCF_CLK 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #include <asm/m52xxacr.h> 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* 22*4882a593Smuzhiyun * Define the 5280/5282 SIM register set addresses. 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ 25*4882a593Smuzhiyun #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 28*4882a593Smuzhiyun #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 29*4882a593Smuzhiyun #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 30*4882a593Smuzhiyun #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 31*4882a593Smuzhiyun #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 32*4882a593Smuzhiyun #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 33*4882a593Smuzhiyun #define MCFINTC_IRLR 0x18 /* */ 34*4882a593Smuzhiyun #define MCFINTC_IACKL 0x19 /* */ 35*4882a593Smuzhiyun #define MCFINTC_ICR0 0x40 /* Base ICR register */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define MCFINT_VECBASE 64 /* Vector base number */ 38*4882a593Smuzhiyun #define MCFINT_UART0 13 /* Interrupt number for UART0 */ 39*4882a593Smuzhiyun #define MCFINT_UART1 14 /* Interrupt number for UART1 */ 40*4882a593Smuzhiyun #define MCFINT_UART2 15 /* Interrupt number for UART2 */ 41*4882a593Smuzhiyun #define MCFINT_I2C0 17 /* Interrupt number for I2C */ 42*4882a593Smuzhiyun #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ 43*4882a593Smuzhiyun #define MCFINT_FECRX0 23 /* Interrupt number for FEC */ 44*4882a593Smuzhiyun #define MCFINT_FECTX0 27 /* Interrupt number for FEC */ 45*4882a593Smuzhiyun #define MCFINT_FECENTC0 29 /* Interrupt number for FEC */ 46*4882a593Smuzhiyun #define MCFINT_PIT1 55 /* Interrupt number for PIT1 */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) 49*4882a593Smuzhiyun #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) 50*4882a593Smuzhiyun #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) 53*4882a593Smuzhiyun #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) 54*4882a593Smuzhiyun #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 57*4882a593Smuzhiyun #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) 58*4882a593Smuzhiyun #define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* 61*4882a593Smuzhiyun * SDRAM configuration registers. 62*4882a593Smuzhiyun */ 63*4882a593Smuzhiyun #define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */ 64*4882a593Smuzhiyun #define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */ 65*4882a593Smuzhiyun #define MCFSIM_DMR0 (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */ 66*4882a593Smuzhiyun #define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */ 67*4882a593Smuzhiyun #define MCFSIM_DMR1 (MCF_IPSBAR + 0x00000054) /* Address mask 1 */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* 70*4882a593Smuzhiyun * DMA unit base addresses. 71*4882a593Smuzhiyun */ 72*4882a593Smuzhiyun #define MCFDMA_BASE0 (MCF_IPSBAR + 0x00000100) 73*4882a593Smuzhiyun #define MCFDMA_BASE1 (MCF_IPSBAR + 0x00000140) 74*4882a593Smuzhiyun #define MCFDMA_BASE2 (MCF_IPSBAR + 0x00000180) 75*4882a593Smuzhiyun #define MCFDMA_BASE3 (MCF_IPSBAR + 0x000001C0) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* 78*4882a593Smuzhiyun * UART module. 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun #define MCFUART_BASE0 (MCF_IPSBAR + 0x00000200) 81*4882a593Smuzhiyun #define MCFUART_BASE1 (MCF_IPSBAR + 0x00000240) 82*4882a593Smuzhiyun #define MCFUART_BASE2 (MCF_IPSBAR + 0x00000280) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* 85*4882a593Smuzhiyun * FEC ethernet module. 86*4882a593Smuzhiyun */ 87*4882a593Smuzhiyun #define MCFFEC_BASE0 (MCF_IPSBAR + 0x00001000) 88*4882a593Smuzhiyun #define MCFFEC_SIZE0 0x800 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* 91*4882a593Smuzhiyun * QSPI module. 92*4882a593Smuzhiyun */ 93*4882a593Smuzhiyun #define MCFQSPI_BASE (MCF_IPSBAR + 0x340) 94*4882a593Smuzhiyun #define MCFQSPI_SIZE 0x40 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define MCFQSPI_CS0 147 97*4882a593Smuzhiyun #define MCFQSPI_CS1 148 98*4882a593Smuzhiyun #define MCFQSPI_CS2 149 99*4882a593Smuzhiyun #define MCFQSPI_CS3 150 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* 102*4882a593Smuzhiyun * GPIO registers 103*4882a593Smuzhiyun */ 104*4882a593Smuzhiyun #define MCFGPIO_PODR_A (MCF_IPSBAR + 0x00100000) 105*4882a593Smuzhiyun #define MCFGPIO_PODR_B (MCF_IPSBAR + 0x00100001) 106*4882a593Smuzhiyun #define MCFGPIO_PODR_C (MCF_IPSBAR + 0x00100002) 107*4882a593Smuzhiyun #define MCFGPIO_PODR_D (MCF_IPSBAR + 0x00100003) 108*4882a593Smuzhiyun #define MCFGPIO_PODR_E (MCF_IPSBAR + 0x00100004) 109*4882a593Smuzhiyun #define MCFGPIO_PODR_F (MCF_IPSBAR + 0x00100005) 110*4882a593Smuzhiyun #define MCFGPIO_PODR_G (MCF_IPSBAR + 0x00100006) 111*4882a593Smuzhiyun #define MCFGPIO_PODR_H (MCF_IPSBAR + 0x00100007) 112*4882a593Smuzhiyun #define MCFGPIO_PODR_J (MCF_IPSBAR + 0x00100008) 113*4882a593Smuzhiyun #define MCFGPIO_PODR_DD (MCF_IPSBAR + 0x00100009) 114*4882a593Smuzhiyun #define MCFGPIO_PODR_EH (MCF_IPSBAR + 0x0010000A) 115*4882a593Smuzhiyun #define MCFGPIO_PODR_EL (MCF_IPSBAR + 0x0010000B) 116*4882a593Smuzhiyun #define MCFGPIO_PODR_AS (MCF_IPSBAR + 0x0010000C) 117*4882a593Smuzhiyun #define MCFGPIO_PODR_QS (MCF_IPSBAR + 0x0010000D) 118*4882a593Smuzhiyun #define MCFGPIO_PODR_SD (MCF_IPSBAR + 0x0010000E) 119*4882a593Smuzhiyun #define MCFGPIO_PODR_TC (MCF_IPSBAR + 0x0010000F) 120*4882a593Smuzhiyun #define MCFGPIO_PODR_TD (MCF_IPSBAR + 0x00100010) 121*4882a593Smuzhiyun #define MCFGPIO_PODR_UA (MCF_IPSBAR + 0x00100011) 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #define MCFGPIO_PDDR_A (MCF_IPSBAR + 0x00100014) 124*4882a593Smuzhiyun #define MCFGPIO_PDDR_B (MCF_IPSBAR + 0x00100015) 125*4882a593Smuzhiyun #define MCFGPIO_PDDR_C (MCF_IPSBAR + 0x00100016) 126*4882a593Smuzhiyun #define MCFGPIO_PDDR_D (MCF_IPSBAR + 0x00100017) 127*4882a593Smuzhiyun #define MCFGPIO_PDDR_E (MCF_IPSBAR + 0x00100018) 128*4882a593Smuzhiyun #define MCFGPIO_PDDR_F (MCF_IPSBAR + 0x00100019) 129*4882a593Smuzhiyun #define MCFGPIO_PDDR_G (MCF_IPSBAR + 0x0010001A) 130*4882a593Smuzhiyun #define MCFGPIO_PDDR_H (MCF_IPSBAR + 0x0010001B) 131*4882a593Smuzhiyun #define MCFGPIO_PDDR_J (MCF_IPSBAR + 0x0010001C) 132*4882a593Smuzhiyun #define MCFGPIO_PDDR_DD (MCF_IPSBAR + 0x0010001D) 133*4882a593Smuzhiyun #define MCFGPIO_PDDR_EH (MCF_IPSBAR + 0x0010001E) 134*4882a593Smuzhiyun #define MCFGPIO_PDDR_EL (MCF_IPSBAR + 0x0010001F) 135*4882a593Smuzhiyun #define MCFGPIO_PDDR_AS (MCF_IPSBAR + 0x00100020) 136*4882a593Smuzhiyun #define MCFGPIO_PDDR_QS (MCF_IPSBAR + 0x00100021) 137*4882a593Smuzhiyun #define MCFGPIO_PDDR_SD (MCF_IPSBAR + 0x00100022) 138*4882a593Smuzhiyun #define MCFGPIO_PDDR_TC (MCF_IPSBAR + 0x00100023) 139*4882a593Smuzhiyun #define MCFGPIO_PDDR_TD (MCF_IPSBAR + 0x00100024) 140*4882a593Smuzhiyun #define MCFGPIO_PDDR_UA (MCF_IPSBAR + 0x00100025) 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_A (MCF_IPSBAR + 0x00100028) 143*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_B (MCF_IPSBAR + 0x00100029) 144*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_C (MCF_IPSBAR + 0x0010002A) 145*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_D (MCF_IPSBAR + 0x0010002B) 146*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_E (MCF_IPSBAR + 0x0010002C) 147*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_F (MCF_IPSBAR + 0x0010002D) 148*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_G (MCF_IPSBAR + 0x0010002E) 149*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_H (MCF_IPSBAR + 0x0010002F) 150*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_J (MCF_IPSBAR + 0x00100030) 151*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_DD (MCF_IPSBAR + 0x00100031) 152*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_EH (MCF_IPSBAR + 0x00100032) 153*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_EL (MCF_IPSBAR + 0x00100033) 154*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_AS (MCF_IPSBAR + 0x00100034) 155*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_QS (MCF_IPSBAR + 0x00100035) 156*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_SD (MCF_IPSBAR + 0x00100036) 157*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_TC (MCF_IPSBAR + 0x00100037) 158*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_TD (MCF_IPSBAR + 0x00100038) 159*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_UA (MCF_IPSBAR + 0x00100039) 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun #define MCFGPIO_PCLRR_A (MCF_IPSBAR + 0x0010003C) 162*4882a593Smuzhiyun #define MCFGPIO_PCLRR_B (MCF_IPSBAR + 0x0010003D) 163*4882a593Smuzhiyun #define MCFGPIO_PCLRR_C (MCF_IPSBAR + 0x0010003E) 164*4882a593Smuzhiyun #define MCFGPIO_PCLRR_D (MCF_IPSBAR + 0x0010003F) 165*4882a593Smuzhiyun #define MCFGPIO_PCLRR_E (MCF_IPSBAR + 0x00100040) 166*4882a593Smuzhiyun #define MCFGPIO_PCLRR_F (MCF_IPSBAR + 0x00100041) 167*4882a593Smuzhiyun #define MCFGPIO_PCLRR_G (MCF_IPSBAR + 0x00100042) 168*4882a593Smuzhiyun #define MCFGPIO_PCLRR_H (MCF_IPSBAR + 0x00100043) 169*4882a593Smuzhiyun #define MCFGPIO_PCLRR_J (MCF_IPSBAR + 0x00100044) 170*4882a593Smuzhiyun #define MCFGPIO_PCLRR_DD (MCF_IPSBAR + 0x00100045) 171*4882a593Smuzhiyun #define MCFGPIO_PCLRR_EH (MCF_IPSBAR + 0x00100046) 172*4882a593Smuzhiyun #define MCFGPIO_PCLRR_EL (MCF_IPSBAR + 0x00100047) 173*4882a593Smuzhiyun #define MCFGPIO_PCLRR_AS (MCF_IPSBAR + 0x00100048) 174*4882a593Smuzhiyun #define MCFGPIO_PCLRR_QS (MCF_IPSBAR + 0x00100049) 175*4882a593Smuzhiyun #define MCFGPIO_PCLRR_SD (MCF_IPSBAR + 0x0010004A) 176*4882a593Smuzhiyun #define MCFGPIO_PCLRR_TC (MCF_IPSBAR + 0x0010004B) 177*4882a593Smuzhiyun #define MCFGPIO_PCLRR_TD (MCF_IPSBAR + 0x0010004C) 178*4882a593Smuzhiyun #define MCFGPIO_PCLRR_UA (MCF_IPSBAR + 0x0010004D) 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun #define MCFGPIO_PBCDPAR (MCF_IPSBAR + 0x00100050) 181*4882a593Smuzhiyun #define MCFGPIO_PFPAR (MCF_IPSBAR + 0x00100051) 182*4882a593Smuzhiyun #define MCFGPIO_PEPAR (MCF_IPSBAR + 0x00100052) 183*4882a593Smuzhiyun #define MCFGPIO_PJPAR (MCF_IPSBAR + 0x00100054) 184*4882a593Smuzhiyun #define MCFGPIO_PSDPAR (MCF_IPSBAR + 0x00100055) 185*4882a593Smuzhiyun #define MCFGPIO_PASPAR (MCF_IPSBAR + 0x00100056) 186*4882a593Smuzhiyun #define MCFGPIO_PEHLPAR (MCF_IPSBAR + 0x00100058) 187*4882a593Smuzhiyun #define MCFGPIO_PQSPAR (MCF_IPSBAR + 0x00100059) 188*4882a593Smuzhiyun #define MCFGPIO_PTCPAR (MCF_IPSBAR + 0x0010005A) 189*4882a593Smuzhiyun #define MCFGPIO_PTDPAR (MCF_IPSBAR + 0x0010005B) 190*4882a593Smuzhiyun #define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C) 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun /* 193*4882a593Smuzhiyun * PIT timer base addresses. 194*4882a593Smuzhiyun */ 195*4882a593Smuzhiyun #define MCFPIT_BASE1 (MCF_IPSBAR + 0x00150000) 196*4882a593Smuzhiyun #define MCFPIT_BASE2 (MCF_IPSBAR + 0x00160000) 197*4882a593Smuzhiyun #define MCFPIT_BASE3 (MCF_IPSBAR + 0x00170000) 198*4882a593Smuzhiyun #define MCFPIT_BASE4 (MCF_IPSBAR + 0x00180000) 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun /* 201*4882a593Smuzhiyun * Edge Port registers 202*4882a593Smuzhiyun */ 203*4882a593Smuzhiyun #define MCFEPORT_EPPAR (MCF_IPSBAR + 0x00130000) 204*4882a593Smuzhiyun #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x00130002) 205*4882a593Smuzhiyun #define MCFEPORT_EPIER (MCF_IPSBAR + 0x00130003) 206*4882a593Smuzhiyun #define MCFEPORT_EPDR (MCF_IPSBAR + 0x00130004) 207*4882a593Smuzhiyun #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x00130005) 208*4882a593Smuzhiyun #define MCFEPORT_EPFR (MCF_IPSBAR + 0x00130006) 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun /* 211*4882a593Smuzhiyun * Queued ADC registers 212*4882a593Smuzhiyun */ 213*4882a593Smuzhiyun #define MCFQADC_PORTQA (MCF_IPSBAR + 0x00190006) 214*4882a593Smuzhiyun #define MCFQADC_PORTQB (MCF_IPSBAR + 0x00190007) 215*4882a593Smuzhiyun #define MCFQADC_DDRQA (MCF_IPSBAR + 0x00190008) 216*4882a593Smuzhiyun #define MCFQADC_DDRQB (MCF_IPSBAR + 0x00190009) 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun /* 219*4882a593Smuzhiyun * General Purpose Timers registers 220*4882a593Smuzhiyun */ 221*4882a593Smuzhiyun #define MCFGPTA_GPTPORT (MCF_IPSBAR + 0x001A001D) 222*4882a593Smuzhiyun #define MCFGPTA_GPTDDR (MCF_IPSBAR + 0x001A001E) 223*4882a593Smuzhiyun #define MCFGPTB_GPTPORT (MCF_IPSBAR + 0x001B001D) 224*4882a593Smuzhiyun #define MCFGPTB_GPTDDR (MCF_IPSBAR + 0x001B001E) 225*4882a593Smuzhiyun /* 226*4882a593Smuzhiyun * 227*4882a593Smuzhiyun * definitions for generic gpio support 228*4882a593Smuzhiyun * 229*4882a593Smuzhiyun */ 230*4882a593Smuzhiyun #define MCFGPIO_PODR MCFGPIO_PODR_A /* port output data */ 231*4882a593Smuzhiyun #define MCFGPIO_PDDR MCFGPIO_PDDR_A /* port data direction */ 232*4882a593Smuzhiyun #define MCFGPIO_PPDR MCFGPIO_PPDSDR_A/* port pin data */ 233*4882a593Smuzhiyun #define MCFGPIO_SETR MCFGPIO_PPDSDR_A/* set output */ 234*4882a593Smuzhiyun #define MCFGPIO_CLRR MCFGPIO_PCLRR_A /* clr output */ 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun #define MCFGPIO_IRQ_MAX 8 237*4882a593Smuzhiyun #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 238*4882a593Smuzhiyun #define MCFGPIO_PIN_MAX 180 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun /* 241*4882a593Smuzhiyun * Reset Control Unit (relative to IPSBAR). 242*4882a593Smuzhiyun */ 243*4882a593Smuzhiyun #define MCF_RCR (MCF_IPSBAR + 0x110000) 244*4882a593Smuzhiyun #define MCF_RSR (MCF_IPSBAR + 0x110001) 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 247*4882a593Smuzhiyun #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun /* 250*4882a593Smuzhiyun * I2C module 251*4882a593Smuzhiyun */ 252*4882a593Smuzhiyun #define MCFI2C_BASE0 (MCF_IPSBAR + 0x300) 253*4882a593Smuzhiyun #define MCFI2C_SIZE0 0x40 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun /****************************************************************************/ 256*4882a593Smuzhiyun #endif /* m528xsim_h */ 257