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/rk3399_ARM-atf/plat/mediatek/drivers/thermal/mt8189/
H A Dsoc_temp_lvts.c134 unsigned int msr_raw, cur_msr_raw, d_index, i; in set_tc_hw_reboot_threshold() local
152 for (i = 0; i < tc[tc_id].num_sensor; i++) { in set_tc_hw_reboot_threshold()
154 &(tc[tc_id].coeff), i, trip_point); in set_tc_hw_reboot_threshold()
261 unsigned int i; in init_controller_v1() local
267 for (i = 0; i < lvts_data->num_tc; i++) { in init_controller_v1()
268 if (tc[i].ctrl_on_off == CTRL_OFF) in init_controller_v1()
271 base = GET_BASE_ADDR(lvts_data, i); in init_controller_v1()
277 set_polling_speed(lvts_data, i); in init_controller_v1()
278 set_hw_filter(lvts_data, i); in init_controller_v1()
284 unsigned int i; in mt8189_device_enable_and_init() local
[all …]
/rk3399_ARM-atf/plat/imx/imx8ulp/
H A Ddram.c163 unsigned int i; in ddr_init() local
166 for (i = 0U; i < CTL_NUM; i++) { in ddr_init()
167 mmio_write_32(IMX_DDRC_BASE + i * 4, dram_timing_cfg->ctl_cfg[i]); in ddr_init()
171 for (i = 0U; i < PI_NUM; i++) { in ddr_init()
172 mmio_write_32(IMX_DDRC_BASE + 0x2000 + i * 4, dram_timing_cfg->pi_cfg[i]); in ddr_init()
179 for (i = 0U; i < PHY_NUM; i++) { in ddr_init()
181 if (i >= 121U && i <= 255U) { in ddr_init()
184 if (i >= 377U && i <= 511U) { in ddr_init()
187 if (i >= 633U && i <= 767U) { in ddr_init()
190 if (i >= 889U && i <= 1023U) { in ddr_init()
[all …]
/rk3399_ARM-atf/drivers/nxp/trdc/
H A Dimx_trdc.c250 unsigned int i; in is_trdc_mgr_slot() local
252 for (i = 0U; i < trdc_mgr_num; i++) { in is_trdc_mgr_slot()
253 if (trdc_mgr_blks[i].trdc_base == trdc_base) { in is_trdc_mgr_slot()
254 if (mbc_id == trdc_mgr_blks[i].mbc_id && in is_trdc_mgr_slot()
255 mem_id == trdc_mgr_blks[i].mbc_mem_id && in is_trdc_mgr_slot()
256 (blk_id == trdc_mgr_blks[i].blk_mgr || in is_trdc_mgr_slot()
257 blk_id == trdc_mgr_blks[i].blk_mc)) { in is_trdc_mgr_slot()
272 unsigned int i; in trdc_mgr_mbc_setup() local
281 for (i = 0U; i < 16U; i++) { in trdc_mgr_mbc_setup()
282 trdc_mbc_blk_config(mgr->trdc_base, mgr->mbc_id, i, in trdc_mgr_mbc_setup()
[all …]
/rk3399_ARM-atf/plat/imx/common/
H A Dimx7_clock.c11 unsigned int i; in imx7_clock_uart_init() local
13 for (i = 0; i < MXC_MAX_UART_NUM; i++) in imx7_clock_uart_init()
14 imx_clock_disable_uart(i); in imx7_clock_uart_init()
19 unsigned int i; in imx7_clock_wdog_init() local
21 for (i = 0; i < MXC_MAX_WDOG_NUM; i++) in imx7_clock_wdog_init()
22 imx_clock_disable_wdog(i); in imx7_clock_wdog_init()
H A Dimx_aips.c15 int i; in imx_aips_set_default_access() local
40 for (i = 0; i < AIPSTZ_OAPCR_COUNT; i++) { in imx_aips_set_default_access()
41 addr = (uintptr_t)&aips_regs->aipstz_opacr[i]; in imx_aips_set_default_access()
48 int i; in imx_aips_init() local
55 for (i = 0; i < ARRAY_SIZE(aips_regs); i++) in imx_aips_init()
56 imx_aips_set_default_access(aips_regs[i]); in imx_aips_init()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/soc/
H A Dsoc.c156 int i; in save_pll() local
158 for (i = 0; i < PLL_CON_COUNT; i++) in save_pll()
159 dst[i] = mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, i)); in save_pll()
183 uint32_t i = 0; in clk_gate_con_save() local
185 for (i = 0; i < PMUCRU_GATE_COUNT; i++) in clk_gate_con_save()
186 slp_data.pmucru_gate_con[i] = in clk_gate_con_save()
187 mmio_read_32(PMUCRU_BASE + PMUCRU_GATE_CON(i)); in clk_gate_con_save()
189 for (i = 0; i < CRU_GATE_COUNT; i++) in clk_gate_con_save()
190 slp_data.cru_gate_con[i] = in clk_gate_con_save()
191 mmio_read_32(CRU_BASE + CRU_GATE_CON(i)); in clk_gate_con_save()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/soc/
H A Dsoc.h42 #define CRU_PLLS_CON(pll_id, i) (0x160 + (pll_id) * 0x20 + (i) * 0x4) argument
43 #define CRU_PLL_CON(i) ((i) * 0x4) argument
45 #define CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300) argument
46 #define CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800) argument
48 #define CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00) argument
80 #define SECURECRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800) argument
86 #define CENTER_GRF_CON(i) ((i) * 4) argument
113 #define PVTM_CON(i) (0x4 + (i) * 4) argument
116 #define PVTM_STATUS(i) (0x80 + (i) * 4) argument
193 #define DDRGRF_CHA_CON(i) ((i) * 4) argument
[all …]
/rk3399_ARM-atf/drivers/renesas/rcar/qos/V3M/
H A Dqos_init_v3m.c88 uint32_t i; in qos_init_v3m() local
90 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_v3m()
91 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); in qos_init_v3m()
92 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); in qos_init_v3m()
94 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_v3m()
95 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); in qos_init_v3m()
96 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); in qos_init_v3m()
/rk3399_ARM-atf/lib/cpus/aarch64/
H A Dcpuamu.c23 unsigned int i; in cpuamu_context_save() local
35 for (i = 0; i < nr_counters; i++) in cpuamu_context_save()
36 ctx->cnts[i] = cpuamu_cnt_read(i); in cpuamu_context_save()
42 unsigned int i; in cpuamu_context_restore() local
54 for (i = 0; i < nr_counters; i++) in cpuamu_context_restore()
55 cpuamu_cnt_write(i, ctx->cnts[i]); in cpuamu_context_restore()
/rk3399_ARM-atf/services/std_svc/drtm/
H A Ddrtm_res_address_map.c49 unsigned int i; in drtm_build_address_map() local
56 for (i = 0U; mmap[i].base_pa != 0UL; i++) { in drtm_build_address_map()
58 map->region[i].region_address = mmap[i].base_pa; in drtm_build_address_map()
61 map->region[i].region_size_type = 0; in drtm_build_address_map()
63 map->region[i].region_size_type, in drtm_build_address_map()
64 mmap[i].size / PAGE_SIZE_4KB); in drtm_build_address_map()
67 switch (MT_TYPE(mmap[i].attr)) { in drtm_build_address_map()
70 map->region[i].region_size_type, in drtm_build_address_map()
75 map->region[i].region_size_type, in drtm_build_address_map()
78 map->region[i].region_size_type, in drtm_build_address_map()
[all …]
/rk3399_ARM-atf/drivers/nxp/ddr/nxp-ddr/
H A Dddr.c269 unsigned int i; in cal_odt() local
301 for (i = 0U; i < DDRC_NUM_CS; i++) { in cal_odt()
302 debug("cs %d\n", i); in cal_odt()
303 popts->cs_odt[i].odt_rd_cfg = pdodt[i].odt_rd_cfg; in cal_odt()
305 popts->cs_odt[i].odt_rd_cfg); in cal_odt()
306 popts->cs_odt[i].odt_wr_cfg = pdodt[i].odt_wr_cfg; in cal_odt()
308 popts->cs_odt[i].odt_wr_cfg); in cal_odt()
309 popts->cs_odt[i].odt_rtt_norm = pdodt[i].odt_rtt_norm; in cal_odt()
311 popts->cs_odt[i].odt_rtt_norm); in cal_odt()
312 popts->cs_odt[i].odt_rtt_wr = pdodt[i].odt_rtt_wr; in cal_odt()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_vcore_dvfsrc_plat.c122 int i; in dvfsrc_init() local
128 for (i = 0; i < ARRAY_SIZE(dvfsrc_init_configs); i++) in dvfsrc_init()
129 mmio_write_32(dvfsrc_init_configs[i].offset, in dvfsrc_init()
130 dvfsrc_init_configs[i].val); in dvfsrc_init()
133 for (i = 0; i < ARRAY_SIZE(lp5_8533_init_configs_auto); i++) in dvfsrc_init()
134 mmio_write_32(lp5_8533_init_configs_auto[i].offset, in dvfsrc_init()
135 lp5_8533_init_configs_auto[i].val); in dvfsrc_init()
139 for (i = 0; i < ARRAY_SIZE(lp5_7500_init_configs); i++) in dvfsrc_init()
140 mmio_write_32(lp5_7500_init_configs[i].offset, in dvfsrc_init()
141 lp5_7500_init_configs[i].val); in dvfsrc_init()
[all …]
/rk3399_ARM-atf/plat/intel/soc/common/sip/
H A Dsocfpga_sip_fcs.c345 unsigned int i; in intel_fcs_random_number_gen() local
368 for (i = 0U; i < FCS_RANDOM_WORD_SIZE; i++) { in intel_fcs_random_number_gen()
369 mmio_write_32(addr, random_data[i]); in intel_fcs_random_number_gen()
1045 uint32_t i; in intel_fcs_export_crypto_service_key() local
1086 for (i = 1U; i < resp_len; i++) { in intel_fcs_export_crypto_service_key()
1087 mmio_write_32(dst_addr, resp_data[i]); in intel_fcs_export_crypto_service_key()
1206 uint32_t i; in intel_fcs_get_digest_update_finalize() local
1254 i = 0; in intel_fcs_get_digest_update_finalize()
1255 payload[i] = fcs_sha_get_digest_param.session_id; in intel_fcs_get_digest_update_finalize()
1256 i++; in intel_fcs_get_digest_update_finalize()
[all …]
/rk3399_ARM-atf/drivers/renesas/rcar/qos/H3/
H A Dqos_init_h3_v10.c71 uint32_t i; in qos_init_h3_v10() local
73 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_h3_v10()
74 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); in qos_init_h3_v10()
75 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); in qos_init_h3_v10()
77 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_h3_v10()
78 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); in qos_init_h3_v10()
79 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); in qos_init_h3_v10()
/rk3399_ARM-atf/plat/arm/board/neoverse_rd/platform/rdn2/
H A Drdn2_security.c51 unsigned int i; in plat_arm_security_setup() local
55 for (i = 0; i < TZC400_COUNT; i++) { in plat_arm_security_setup()
56 arm_tzc400_setup(TZC400_BASE(i), tzc_regions); in plat_arm_security_setup()
62 for (i = 1; i < NRD_CHIP_COUNT; i++) { in plat_arm_security_setup()
63 INFO("Configuring TrustZone Controller for Chip %u\n", i); in plat_arm_security_setup()
66 arm_tzc400_setup(NRD_REMOTE_CHIP_MEM_OFFSET(i) in plat_arm_security_setup()
67 + TZC400_BASE(j), tzc_regions_mc[i-1]); in plat_arm_security_setup()
/rk3399_ARM-atf/plat/mediatek/common/lpm/
H A Dmt_lp_rq.c29 int i; in mt_lp_resource_request() local
40 for (i = 0; i < plat_mt_rqm.resource_num; i++) { in mt_lp_resource_request()
41 if ((resource & rs[i]->res_id) != 0) { in mt_lp_resource_request()
42 rs[i]->res_usage |= this->umask; in mt_lp_resource_request()
54 int i; in mt_lp_resource_release() local
64 for (i = 0; i < plat_mt_rqm.resource_num; i++) { in mt_lp_resource_release()
65 rs[i]->res_usage &= ~(this->umask); in mt_lp_resource_release()
98 int i, len; in mt_lp_resource_user_register() local
114 for (i = 0; i < len; i++) { in mt_lp_resource_user_register()
115 uname |= (user[i] << (MT_LP_RQ_USER_CHAR_U * i)); in mt_lp_resource_user_register()
[all …]
/rk3399_ARM-atf/plat/renesas/common/
H A Dbl2_secure_setting.c351 uint32_t i; in lifec_security_setting() local
353 for (i = 0; i < ARRAY_SIZE(lifec); i++) in lifec_security_setting()
354 mmio_write_32(lifec[i].reg, lifec[i].val); in lifec_security_setting()
360 uint32_t i; in axi_security_setting() local
362 for (i = 0; i < ARRAY_SIZE(axi); i++) in axi_security_setting()
363 mmio_write_32(axi[i].reg, axi[i].val); in axi_security_setting()
369 uint32_t i; in bl2_ram_security_setting_finish() local
371 for (i = 0; i < ARRAY_SIZE(axi_dram); i++) in bl2_ram_security_setting_finish()
372 mmio_write_32(axi_dram[i].reg, axi_dram[i].val); in bl2_ram_security_setting_finish()
/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_ddr.c156 for (int i = 0; i < io96b_ctrl->num_instance; i++) { in config_io96b_csr_addr() local
157 switch (i) { in config_io96b_csr_addr()
198 uint32_t i; in sdram_set_firewall_non_f2sdram() local
202 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { in sdram_set_firewall_non_f2sdram()
203 if (ddr_info_set[i].size == 0) { in sdram_set_firewall_non_f2sdram()
207 value = ddr_info_set[i].start; in sdram_set_firewall_non_f2sdram()
221 (i * 4 * sizeof(uint32_t))); in sdram_set_firewall_non_f2sdram()
224 (i * 4 * sizeof(uint32_t))); in sdram_set_firewall_non_f2sdram()
229 (i * 4 * sizeof(uint32_t))); in sdram_set_firewall_non_f2sdram()
232 (i * 4 * sizeof(uint32_t))); in sdram_set_firewall_non_f2sdram()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/
H A Dmt_spm_cond.c135 unsigned int i; in mt_spm_cond_check() local
142 for (i = 0; i < PLAT_SPM_COND_MAX; i++) { in mt_spm_cond_check()
144 res->table_cg[i] = (src->table_cg[i] & dest->table_cg[i]); in mt_spm_cond_check()
145 if (is_system_suspend && ((res->table_cg[i]) != 0U)) { in mt_spm_cond_check()
147 dest->name, i, idle_cg_info[i].addr, in mt_spm_cond_check()
148 res->table_cg[i]); in mt_spm_cond_check()
151 if ((res->table_cg[i]) != 0U) { in mt_spm_cond_check()
152 b_res |= BIT(i); in mt_spm_cond_check()
154 } else if ((src->table_cg[i] & dest->table_cg[i]) != 0U) { in mt_spm_cond_check()
155 b_res |= BIT(i); in mt_spm_cond_check()
[all …]
/rk3399_ARM-atf/plat/marvell/armada/a8k/a80x0_puzzle/board/
H A Dsystem_power.c25 unsigned int i; in add_xor_checksum() local
27 for (i = 0; i < xor_len; i++) in add_xor_checksum()
28 xor_sum ^= buf[i]; in add_xor_checksum()
39 int i, len; in system_power_off() local
48 for (i = 0; i < len; i++) { in system_power_off()
49 console.putc(system_off_now[i], &console); in system_power_off()
/rk3399_ARM-atf/plat/arm/common/
H A Darm_pm.c29 unsigned int i; in arm_validate_power_state() local
48 for (i = ARM_PWR_LVL0; i <= pwr_lvl; i++) in arm_validate_power_state()
49 req_state->pwr_domain_state[i] = in arm_validate_power_state()
76 int i; in arm_validate_power_state() local
85 for (i = 0; !!arm_pm_idle_states[i]; i++) { in arm_validate_power_state()
87 arm_pm_idle_states[i]) in arm_validate_power_state()
92 if (!arm_pm_idle_states[i]) in arm_validate_power_state()
95 i = 0; in arm_validate_power_state()
99 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) { in arm_validate_power_state()
100 req_state->pwr_domain_state[i] = state_id & in arm_validate_power_state()
/rk3399_ARM-atf/plat/imx/imx8m/imx8mp/
H A Dgpc.c128 unsigned int i; in imx_noc_qos() local
158 for (i = 0; i < ARRAY_SIZE(noc_setting); i++) { in imx_noc_qos()
159 if (noc_setting[i].domain_id == domain_id) { in imx_noc_qos()
161 uint32_t offset = noc_setting[i].start; in imx_noc_qos()
163 while (offset <= noc_setting[i].end) { in imx_noc_qos()
164 mmio_write_32(IMX_NOC_BASE + offset + 0x8, noc_setting[i].prioriy); in imx_noc_qos()
165 mmio_write_32(IMX_NOC_BASE + offset + 0xc, noc_setting[i].mode); in imx_noc_qos()
166 mmio_write_32(IMX_NOC_BASE + offset + 0x18, noc_setting[i].socket_qos_en); in imx_noc_qos()
176 unsigned int i; in imx_gpc_pm_domain_enable() local
184 for (i = 0; i < ARRAY_SIZE(hsiomix_clk); i++) { in imx_gpc_pm_domain_enable()
[all …]
/rk3399_ARM-atf/lib/extensions/ras/
H A Dstd_err_record.c17 unsigned int num_records, num_group_regs, i; in ser_probe_memmap() local
32 for (i = 0; i < num_group_regs; i++) { in ser_probe_memmap()
33 gsr = mmio_read_64(ERR_GSR(base, size_num_k, i)); in ser_probe_memmap()
39 *probe_data = (((int) (i << 6U)) + __builtin_ctzll(gsr)); in ser_probe_memmap()
54 unsigned int i; in ser_probe_sysreg() local
63 for (i = 0; i < num_idx; i++) { in ser_probe_sysreg()
65 ser_sys_select_record(idx_start + i); in ser_probe_sysreg()
73 *probe_data = (int) i; in ser_probe_sysreg()
/rk3399_ARM-atf/drivers/nxp/clk/s32cc/
H A Ds32cc_clk_utils.c35 size_t i; in s32cc_get_clk_from_table() local
37 for (i = 0; i < size; i++) { in s32cc_get_clk_from_table()
38 clk = s32cc_clk_get_from_array(clk_arr[i], clk_id); in s32cc_get_clk_from_table()
51 size_t i, j; in s32cc_get_id_from_table() local
53 for (i = 0; i < size; i++) { in s32cc_get_id_from_table()
54 for (j = 0; j < clk_arr[i]->n_clks; j++) { in s32cc_get_id_from_table()
55 if (clk_arr[i]->clks[j] != clk) { in s32cc_get_id_from_table()
59 *clk_index = S32CC_CLK(clk_arr[i]->type_mask, j); in s32cc_get_id_from_table()
/rk3399_ARM-atf/plat/mediatek/common/lpm_v2/
H A Dmt_lp_rq.c35 int i; in mt_lp_resource_request() local
47 for (i = 0; i < plat_mt_rqm.resource_num; i++) { in mt_lp_resource_request()
48 if ((resource & rs[i]->res_id) != 0) in mt_lp_resource_request()
49 rs[i]->res_usage |= this->umask; in mt_lp_resource_request()
62 int i; in mt_lp_resource_release() local
72 for (i = 0; i < plat_mt_rqm.resource_num; i++) in mt_lp_resource_release()
73 rs[i]->res_usage &= ~(this->umask); in mt_lp_resource_release()
107 int i, len; in mt_lp_resource_user_register() local
116 for (i = 0; i < len; i++) in mt_lp_resource_user_register()
117 uname |= (user[i] << (MT_LP_RQ_USER_CHAR_U * i)); in mt_lp_resource_user_register()
[all …]

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