269 	unsigned int i;  in cal_odt()  local
301 	for (i = 0U; i < DDRC_NUM_CS; i++) {  in cal_odt()
302 		debug("cs %d\n", i);  in cal_odt()
303 		popts->cs_odt[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;  in cal_odt()
305 			  popts->cs_odt[i].odt_rd_cfg);  in cal_odt()
306 		popts->cs_odt[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;  in cal_odt()
308 			  popts->cs_odt[i].odt_wr_cfg);  in cal_odt()
309 		popts->cs_odt[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;  in cal_odt()
311 			  popts->cs_odt[i].odt_rtt_norm);  in cal_odt()
312 		popts->cs_odt[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;  in cal_odt()
314 			  popts->cs_odt[i].odt_rtt_wr);  in cal_odt()
315 		popts->cs_odt[i].auto_precharge = 0;  in cal_odt()
317 			  popts->cs_odt[i].auto_precharge);  in cal_odt()
441 	int i;  in cal_board_params()  local
443 	for (i = 0; i < len; i++) {  in cal_board_params()
444 		if (pdimm->rc == dimm[i].rc) {  in cal_board_params()
445 			prt = dimm[i].p;  in cal_board_params()
466 	popts->wrlvl_ctl_2 = (prt->wrlvl * 0x01010101 + dimm[i].add1) &  in cal_board_params()
468 	popts->wrlvl_ctl_3 = (prt->wrlvl * 0x01010101 + dimm[i].add2) &  in cal_board_params()
530 	int ret, addr, i;  in parse_spd()  local
533 	for (i = 0; i < num_ctlrs; i++) {  in parse_spd()
534 		debug("Controller %d\n", i);  in parse_spd()
581 		debug("done with controller %d\n", i);  in parse_spd()
663 	int i;  in assign_intlv_addr()  local
698 	for (i = 0; i < ctlr_density_mul; i++) {  in assign_intlv_addr()
699 		conf->cs_base_addr[i] = current_mem_base;  in assign_intlv_addr()
700 		conf->cs_size[i] = total_ctlr_mem;  in assign_intlv_addr()
701 		debug("CS %d\n", i);  in assign_intlv_addr()
702 		debug("    base_addr 0x%llx\n", conf->cs_base_addr[i]);  in assign_intlv_addr()
703 		debug("    size 0x%llx\n", conf->cs_size[i]);  in assign_intlv_addr()
715 	int i;  in assign_non_intlv_addr()  local
726 		for (i = 0; i < DDRC_NUM_CS; i++) {  in assign_non_intlv_addr()
727 			conf->cs_base_addr[i] = current_mem_base;  in assign_non_intlv_addr()
728 			conf->cs_size[i] = rank_density << 2;  in assign_non_intlv_addr()
733 		for (i = 0; ((conf->cs_in_use & (1 << i)) != 0) && i < 2; i++) {  in assign_non_intlv_addr()
734 			conf->cs_base_addr[i] = current_mem_base;  in assign_non_intlv_addr()
735 			conf->cs_size[i] = rank_density << 1;  in assign_non_intlv_addr()
739 		for (; ((conf->cs_in_use & (1 << i)) != 0) && i < DDRC_NUM_CS;  in assign_non_intlv_addr()
740 		     i++) {  in assign_non_intlv_addr()
741 			conf->cs_base_addr[i] = current_mem_base;  in assign_non_intlv_addr()
742 			conf->cs_size[i] = rank_density;  in assign_non_intlv_addr()
748 		for (i = 0; ((conf->cs_in_use & (1 << i)) != 0) &&  in assign_non_intlv_addr()
749 			     (i < DDRC_NUM_CS); i++) {  in assign_non_intlv_addr()
750 			conf->cs_base_addr[i] = current_mem_base;  in assign_non_intlv_addr()
751 			conf->cs_size[i] = rank_density;  in assign_non_intlv_addr()
760 	for (i = 0; ((conf->cs_in_use & (1 << i)) != 0) &&  in assign_non_intlv_addr()
761 		     (i < DDRC_NUM_CS); i++) {  in assign_non_intlv_addr()
762 		debug("CS %d\n", i);  in assign_non_intlv_addr()
763 		debug("    base_addr 0x%llx\n", conf->cs_base_addr[i]);  in assign_non_intlv_addr()
764 		debug("    size 0x%llx\n", conf->cs_size[i]);  in assign_non_intlv_addr()
822 	int i;  in write_ddrc_regs()  local
825 	for (i = 0; i < priv->num_ctlrs; i++) {  in write_ddrc_regs()
826 		ret = ddrc_set_regs(priv->clk, &priv->ddr_reg, priv->ddr[i], 0);  in write_ddrc_regs()