163 	unsigned int i;  in ddr_init()  local
166 	for (i = 0U; i < CTL_NUM; i++) {  in ddr_init()
167 		mmio_write_32(IMX_DDRC_BASE + i * 4, dram_timing_cfg->ctl_cfg[i]);  in ddr_init()
171 	for (i = 0U; i < PI_NUM; i++) {  in ddr_init()
172 		mmio_write_32(IMX_DDRC_BASE + 0x2000 + i * 4, dram_timing_cfg->pi_cfg[i]);  in ddr_init()
179 	for (i = 0U; i < PHY_NUM; i++) {  in ddr_init()
181 		if (i >= 121U && i <= 255U) {  in ddr_init()
184 		if (i >= 377U && i <= 511U) {  in ddr_init()
187 		if (i >= 633U && i <= 767U) {  in ddr_init()
190 		if (i >= 889U && i <= 1023U) {  in ddr_init()
193 		if (i >= 1065U && i <= 1279U) {  in ddr_init()
196 		if (i >= 1321U && i <= 1535U) {  in ddr_init()
199 		mmio_write_32(IMX_DDRC_BASE + 0x4000 + i * 4, dram_timing_cfg->phy_full[i]);  in ddr_init()
205 		for (i = 0U; i < PHY_DIFF_NUM; i++) {  in ddr_init()
206 			mmio_write_32(IMX_DDRC_BASE + 0x4000 + freq_specific_reg_array[i] * 4,  in ddr_init()
207 				      dram_timing_cfg->phy_diff[i]);  in ddr_init()
320 	unsigned int i;  in dram_enter_retention()  local
362 		for (i = 0U; i < CTL_NUM; i++) {  in dram_enter_retention()
363 			dram_timing_cfg->ctl_cfg[i] = mmio_read_32(IMX_DDRC_BASE + i * 4);  in dram_enter_retention()
368 		for (i = 0U; i < PI_NUM; i++) {  in dram_enter_retention()
369 			dram_timing_cfg->pi_cfg[i] = mmio_read_32(IMX_DDRC_BASE + 0x2000 + i * 4);  in dram_enter_retention()
379 			for (i = 0U; i < PHY_NUM; i++) {  in dram_enter_retention()
381 				if (i == 1537U) {  in dram_enter_retention()
382 					dram_timing_cfg->phy_full[i] = 0x100;  in dram_enter_retention()
384 					dram_timing_cfg->phy_full[i] = mmio_read_32(IMX_DDRC_BASE + 0x4000 + i * 4);  in dram_enter_retention()
394 			for (i = 0U; i < PHY_DIFF_NUM; i++) {  in dram_enter_retention()
395 				dram_timing_cfg->phy_diff[i] = mmio_read_32(IMX_DDRC_BASE + 0x4000 +  in dram_enter_retention()
396 									    freq_specific_reg_array[i] * 4);  in dram_enter_retention()
400 			for (i = 0U; i < info->phy_f1_cfg_num; i++) {  in dram_enter_retention()
401 				info->phy_f1_cfg[i].val = mmio_read_32(info->phy_f1_cfg[i].reg);  in dram_enter_retention()
750 	for (unsigned int i = 0; i < PLATFORM_CORE_COUNT; i++)  in dram_dvfs_handler()  local
752 		if (i != cpu_id) {  in dram_dvfs_handler()
753 			plat_ic_raise_el3_sgi(0x8, i);  in dram_dvfs_handler()
779 	unsigned int i;  in dram_init()  local
791 	for (i = 0; i < MAX_FSP_NUM; i++) {  in dram_init()
792 		if (!info->fsp_table[i]) {  in dram_init()
797 	num_fsp = (i > MAX_FSP_NUM) ? MAX_FSP_NUM : i;  in dram_init()